Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/66—Digital/analogue converters
  • H03M1/662—Multiplexed conversion systems
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/66—Digital/analogue converters
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/66—Digital/analogue converters
  • H03M1/74—Simultaneous conversion
  • H03M1/80—Simultaneous conversion using weighted impedances
  • H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices

Definitions

• the invention relates to the generation of analog signals from a digital code with a high output frequency, in particular greater than the sampling frequency, while retaining performance close to the first Nyquist area and limiting the number of components in the signal processing chain.
• a real digital-analog converter has a step output or provides pulses of finite width.
• the spectral response of the converter results in a cardinal sine.
• the power response of the converter thus makes it possible to generate a signal with high dynamics in the first and second Nyquist zones, that is to say between 0 and fs / 2 and between fs / 2 and fs with fs the sampling frequency. of the digital signal.
• the sampling frequency fs for example at 2fs or more
• the invention aims to overcome the aforementioned drawbacks and limitations of the prior art. More specifically, it aims to propose a device for generating analog signals making it possible to optimize the output power of a digital-analog converter and the digital bit rate at the input of the converter.
• An object of the invention is therefore a signal generation device
• analog comprising a digital-analog converter comprising at least a digital input and an analog output, a circuit for generating a first clock signal of frequency fs, and a digital register configured to receive at input and store N bits representative of an analog signal output from the digital-analog converter, N being an integer greater than or equal to 1, and receiving the first clock signal, the register comprising for each bit two complementary digital outputs, characterized in that it also comprises a circuit for generating a second clock signal of frequency mx fs, with m an integer greater than 1, and N multiplexer circuits, placed between the outputs of the digital register and the inputs of the converter digital-analog and configured to each receive, on a control input, the second clock signal and to each receive, on a data input, signals from two digital outputs of the register corresponding to the same input bit of the register, so that the frequency of the signals leaving the multiplexer circuits is 2 xmx fs.
• the circuit for generating the first and second clock signals comprises a clock configured so as to generate a clock signal at the frequency mx fs, and a divider circuit configured so that the signal at the output of the divider circuit either a clock signal of frequency fs;
• the converter is a digital-analog current converter or a digital-analog voltage converter
• the multiplexer circuits include at least one dipole multiplexer.
• Another object of the invention is a method of generating signals
• N bits representative of an analog signal, N being an integer greater than or equal to 1, and apply to this digital register a first clock signal of frequency fs, the register comprising for each input bit two complementary digital outputs;
• the multiplexer circuit n receiving the two outputs from the same input bit n, n being an integer between 1 and N;
• Fig. 1 a device according to a first embodiment of the invention
• FIG. 2 a device according to a second embodiment of the invention
• Fig. 3 a device according to a third embodiment of the invention.
• Fig. 4 a method of generating analog signals according to the invention.
• Fig. 1 presents a device for generating analog signals according to a first embodiment of the invention.
• the device comprises a digital register REG which receives digital data to be converted into an input IN.
• This digital data is for example a binary word comprising three bits: B1, B2 and B3.
• the register REG comprises for each bit two complementary outputs, respectively a first output providing the bit and a second output providing its complementary.
• B1, B2, B3 only three inputs for three bits (B1, B2, B3), and six outputs (B1, Bl, B2, B2, B3, B3) are represented, but more generally the register can receive N bits as input with N a integer greater than or equal to 1 and will therefore have N inputs and 2N outputs.
• a first circuit C1 for generating a clock signal sends a clock signal Clk1 of frequency fs to the register REG so that the bits and their complements (B1, Bl, B2, B2, B3, B3) come out with a frequency fs of the REG register.
• a second circuit C2 for generating a clock signal Clk2 is present. It sends a clock signal Clk2 of frequency m x fs to the control inputs of the multiplexer circuits M1, M2 and M3, with m an integer greater than 1.
• the multiplexer circuits M1, M2 and M3 are placed at the output of the register REG.
• Each multiplexer circuit (M1, M2, M3) receives, at the input, two output signals from the register REG, and more precisely receives a bit and its complementary, therefore the two output signals corresponding to the same input bit in the REG register.
• the multiplexer circuit M1 receives (B1, Bl), the circuit M2 (B2,
• each multiplexer circuit will output either the bit B1, B2 or B3, or its complementary Bl, B2 or B3 according to the rising or falling edge of the clock signal Clk2. This makes it possible to obtain at the output of the multiplexer circuits (M1, M2, M3) the bits or their complementary at a frequency 2 x m x fs.
• a digital to analog converter DAC which includes three digital inputs IN_DAC and an analog output OUT.
• IN_DAC digital to analog converter
• OUT analog output OUT.
• only three IN_DAC inputs are represented because there are three bits bit1, bit2 and bit3 at the input of the REG register, but more generally there will be as many inputs as there are bits at the input of the REG register.
• the bits are converted into analog data, and the spectral response of the analog signal obtained at output OUT of
• Fig. 2 presents a device for generating analog signals according to a second embodiment of the invention.
• this embodiment as in FIG. 1, only three bits bit1, bit2 and bit3 are represented at the input IN of the digital register REG, but there can be N bits at the input of the register REG with N, an integer greater than or equal to 1.
• the circuits for generating the two clock signals are combined.
• a clock signal Clk at a frequency mx fs, with m an integer greater than or equal to 1.
• the clock signal Clk is sent directly to the multiplexer circuits M1, M2 and M3, which allows, as in [Fig. 1], to obtain at the output of the multiplexer circuits M1, M2 and M3, the bits and their complementary at a frequency 2 xmx fs.
• the clock signal Clk before being sent to the register REG, the clock signal Clk first passes through a divider circuit D which divides the frequency of the clock signal by m, which makes it possible to have a clock signal Clk 1 at the input of the frequency register fs.
• Fig. 3 shows a third embodiment of the invention.
• the register REG receives two bits bit1 and bit2 at input, which emerge from the register at the frequency of the clock signal Clk1, fs, in (B1, Bl) and (B2, B2). Then (B1, Bl) and (B2, B2) enter multiplexer circuits M1 and M2 and exit at the frequency 2 xmx fs, thanks to the clock signal Clk2 of frequency mx fs sent to the two multiplexer circuits.
• a REG_DAC register receives a clock signal Clk2 from
• the REG_DAC register For each incoming bit (B1, Bl, B2, B2), the REG_DAC register provides the bit or its complement as an output.
• the REG_DAC register includes two outputs for an input: an even output (PAIR1, PAIR2) which provides the complement of the bit and an odd output (IMP1, IMP2) which provides the bit.
• a set of two odd and even outputs for the same input bit is called a differential branch.
• Two differential branches BD1 and BD2 are shown in this embodiment. The two current sources S1 and S2 are used to supply the two differential branches BD1 and BD2.
• the transistors present (T1, T2, T3, T4) in the two differential branches BD1, BD2 are made conductive according to the value of the bit (0 or 1) in the register REG_DAC. For example, if a bit 1 comes out on the odd branch IMP1, the transistor T 1 will be conductive and if a bit 0 comes out on the odd branch IMP1, then the transistor T2 will be blocked. For the PAIR1 branch, it is the opposite, the output bit must be 0 so that the transistor T2 is conductive or the output bit is 1 so that the transistor T2 is blocked. The same principle applies for the even and odd outputs of the second differential branch BD2.
• the output currents of the odd branches are added in an addition circuit, which in this embodiment is a resistor R1.
• the output currents of the even branches are also added in an addition circuit, which is also a resistor R2 in this embodiment.
• the voltage difference between the voltages across the resistors R1 and R2 represents the digital value of the binary word to be converted, supplied as input IN of the device with the bits bit1 and bit2.
• This voltage difference is provided on the output OUT of the DAC converter.
• the output OUT is a current or voltage value.
• the multiplexer circuits (M1, M2, M3) comprise at least one bipolar multiplexer.
• the DAC converter comprises
• the DAC converter comprises MOSFET transistors, that is to say insulated gate field effect transistors.
• the DAC converter is a
• the DAC converter is more particularly:
• Fig. 4 presents a method for generating analog signals according to
• the first step (step a) consists in supplying, at the input of a digital register, N bits representative of an analog signal, N being an integer greater than or equal to 1, and applying to this digital register a first clock signal of frequency fs, the register comprising for each input bit two complementary digital outputs.
• the next step b consists in applying a second clock signal of frequency 2 xmx fs to N multiplexer circuits, m being an integer greater than or equal to 1, and supplying input from the N multiplexer circuits signals from the two complementary digital outputs of the register, the multiplexer circuit n receiving the two outputs from the same input bit n, n being an integer between 1 and N.
• step c the output signals of the N multiplexer circuits are supplied at input d '' a digital-analog converter and finally in the last step (step d), we recover the converter output signal which corresponds to a voltage or current value whose spectral response is centered around the frequency mx fs.
• This method of generating analog signals can be implemented on a device according to the invention, such as those described above.

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• 2018
  • 2018-11-29 FR FR1872049A patent/FR3089370B1/fr active Active
• 2019
  • 2019-11-18 US US17/286,571 patent/US11528032B2/en active Active
  • 2019-11-18 CA CA3117276A patent/CA3117276A1/en active Pending
  • 2019-11-18 CN CN201980078697.5A patent/CN113169743A/zh active Pending
  • 2019-11-18 WO PCT/EP2019/081587 patent/WO2020109041A1/fr unknown
  • 2019-11-18 KR KR1020217017272A patent/KR20210095877A/ko not_active Application Discontinuation
  • 2019-11-18 EP EP19805282.1A patent/EP3888248A1/de active Pending
  • 2019-11-18 JP JP2021530796A patent/JP7449288B2/ja active Active

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