EP3867945A2 - Verfahren zur herstellung von modulen für mikroelektronische bauelemente mittels eines fotopolymerisationsverfahrens - Google Patents
Verfahren zur herstellung von modulen für mikroelektronische bauelemente mittels eines fotopolymerisationsverfahrensInfo
- Publication number
- EP3867945A2 EP3867945A2 EP19800919.3A EP19800919A EP3867945A2 EP 3867945 A2 EP3867945 A2 EP 3867945A2 EP 19800919 A EP19800919 A EP 19800919A EP 3867945 A2 EP3867945 A2 EP 3867945A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- components
- component
- electrical
- wafer
- optical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000004377 microelectronic Methods 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 230000003287 optical effect Effects 0.000 claims abstract description 22
- 238000012856 packing Methods 0.000 claims abstract description 6
- 238000005520 cutting process Methods 0.000 claims abstract description 4
- 239000004020 conductor Substances 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 7
- 238000004806 packaging method and process Methods 0.000 claims description 5
- 238000007740 vapor deposition Methods 0.000 claims description 5
- 238000001465 metallisation Methods 0.000 claims description 3
- 239000013307 optical fiber Substances 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 24
- 239000002131 composite material Substances 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 238000004026 adhesive bonding Methods 0.000 description 2
- 238000013016 damping Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000006116 polymerization reaction Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 230000000379 polymerizing effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
- H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
- B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
- B01L2200/00—Solutions for specific problems relating to chemical or physical laboratory apparatus
- B01L2200/12—Specific details about manufacturing devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/0347—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/0347—Manufacturing methods using a lift-off mask
- H01L2224/0348—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Definitions
- the invention relates to a method for producing modules for electronic and / or optical and / or fluidic applications, starting from at least one wafer, on the surface of which microelectronic components are provided in a regular and rectangular arrangement, with electrical contacts in the edge area of the respective component, optical connections are also arranged on the surface of the respective component.
- Microelectronic components such as ICs, transistors, diodes, photodiodes etc. are produced on semiconductor wafers.
- the components usually arranged on round wafers have their electrical or optical functions on the surface at the end of production, the electrical contacts being on the edge of the component. There is an area between the components that is used to separate the components. The separation is done by wafer sawing or by laser processing. After being separated, the microelectronic components, the so-called chips, lie on a bluetape and are processed from here using the so-called "pick and place process". In the simplest case, the components are placed on a lead frame and electrically contacted with wire bonders. However, they can also be merged into modules using the 3D CSP process. No wire bonders are used here, rather the electrical connections are made using a PVD process, all the necessary contacts being made in one process step, which leads to a cost reduction compared to the serial wire bonders.
- the invention is therefore based on the object of carrying out a method of the type mentioned at the outset in such a way that the workflows can be carried out more precisely and in a time-saving manner when the components are further processed.
- the invention proposes, according to the characterizing part of claim 1, that by means of a photopolymerization process (RMPD mask process) dielectric packing structures firmly connected to the wafer in layers around the respective components and / or above the components for all these components are generated in parallel and at the same time, the electrical and / or optical contacts for each component likewise being produced, after which the modules thus produced are finally separated by cutting the wafer in the area between the individual modules after all the connections have been completed.
- RMPD mask process photopolymerization process
- the method according to the invention takes advantage of the large order of the wafer (all components are in equidistant positions with accuracies in the nanometer range), which is maintained during further processing of the components until the modules are finally completed.
- the order remains intact and the contacts (both electrical, optical and fluidic) are made in a network. Only then are the completed modules separated.
- the layered structure of the modules enveloping the microelectronic components is known, for example, from DE 1 982 6971 C2.
- a single microelectronic component is surrounded by a housing in the method described in this document, channels being simultaneously generated from the connection surfaces to the surface of the module.
- the components still firmly arranged on the wafer are encased in parallel and at the same time, and all electrical, optical and also fluidic connections to the lateral and / or upper surface of the modules are produced in three dimensions.
- This procedure results in the modules being smaller and can be produced in parallel in large numbers.
- the serial process steps of the pick and place are eliminated.
- Higher precision can be achieved with optical contacts, in particular, because the positioning tolerances are eliminated.
- the dielectric structures generated around the microelectronic components arranged in the fixed wafer composite have different tasks. On the one hand, they serve for the electrical and / or optical insulation of the respective component.
- a base plate can first be attached to the side of the wafer facing away from the components, either by gluing or polymerizing.
- openings and / or channels for the electrical and optical connections or for the capillary line of liquids be left out in the layered structure of the packing structure, these connection structures running three-dimensionally.
- metallic areas are created on the surface of the packaging structure or on corresponding layers when the packaging structure is built up by vapor deposition, which, according to claim 5, represent conductor tracks leading from the tiny connections (pads) present in / on the component to contact areas lead that have a larger area on the side of the component than the connections existing in / on the component, which simplifies subsequent soldering.
- lift-off masks means that the areas of the conductor tracks or contact areas are left out in the layer-by-layer structure and are subsequently vapor-coated with metal, as proposed in claim 9.
- layer by layer and step by step all components arranged on the wafer are simultaneously provided with the appropriate connections, be it electrical, optical (optical fibers) or also fluid (for capillary flow of liquids into and out of the module, for example for analysis tasks ).
- connection structures mentioned above can also be generated above the component composite, as proposed in claim 6.
- one of the layers above the respective component is designed as a cavity. This is particularly advantageous if the components are RF chips. The cavities then reduce the damping of the electromagnetic waves on the chip.
- claim 8 proposes that an antenna be arranged above the last layer on the packaging structure, which antenna is connected to corresponding electrical connections in / on the component by means of metallization. This is also achieved, for example, by using a lift-off mask.
- 1 and 2 show sections of a wafer on which microelectronic components are arranged; 3: cross section through a wafer which is glued to a floor;
- Connection structures 8: Separation of the modules created according to FIGS. 5-7;
- Fig. 9-1 1 step-by-layer and layer-by-layer structure for producing optical windows above the component;
- Fig. 13 and 14 Generation of microfluidic channels for the capillary transport of liquids
- Fig. 15-18 electrical connection structures generated by layer-by-layer construction and use of a lift-off mask that lead to the outside of the module.
- FIG. 1 shows a round wafer with microelectronic components 2 arranged thereon, such as ICs, for example, and is generally provided with the reference symbol 1.
- FIG. 2 shows an enlarged illustration from FIG. 1. As can be seen more clearly from FIG. 2, the components 2 are regularly arranged at defined distances 3 from one another. FIG. 2 also shows that electrical connections 4 (pads) are arranged on the components 2.
- FIG. 3 relates to a cross section through the wafer 1 on which a component 2 is arranged, a base 5 being attached to the underside of the wafer 1 (either by gluing or by polymerization).
- FIG. 4 shows the wafer 1 with a plurality of adjacent components 2 on the base 5, reference number 6 denoting the point at which two components 2 are separated from one another after the machining process has ended.
- FIGS. 5-7 show the process steps in which the component 2 is encased layer by layer by means of a photo polymerization process, the shell 7 thus produced having openings at the locations under which the pads 4 are arranged.
- a lift-off mask 8 is placed over the covering layer 7, which has recesses which, on the one hand, leave the pads 4 free and, furthermore, further areas in which, as shown in FIG. 7, electrical conductor tracks are deposited by metallic vapor deposition 9 are generated.
- the lift-off mask 8 is then removed again and the layer-by-layer construction can be continued.
- FIG. 8 shows the construction of the module 1 has ended due to the generation of the electrical conductor tracks 9, it is detached from the wafer composite on the base 5 by sawing or cutting. This is shown in FIG. 8.
- FIGS. 9-11 show the method steps in which a further structure 11 is built up above the wafer 1, openings 11 for optical waveguides in the structure 11, which are connected to lasers or diode connections, being omitted and being used as Recordings 13 serve for the optical fiber.
- a lift-off mask 14 is placed according to FIG. 10, which leaves the openings 12 free, so that in a further process step, electrically conductive surfaces 15 are again generated using metal vapor deposition.
- the resulting modules 2 with the structure 11 arranged thereon are separated from one another at 16.
- FIGS. 13 and 16 show a further possible variant of the method, in which 17 channels 18 are generated in a further structure, which are intended to serve for the capillary transport of liquids. With the aid of these channels 18, the resulting chip analysis can be carried out.
- the channel 18 is provided with a layer 19 of the structure 17 with a cover 19, in which openings 20 are left, which serve as inlet and outlet connections for the liquid to be examined.
- modules 2 are separated from one another, as shown in FIG.
- modules 2, already isolated at 16 are produced by the aforementioned method, via which a cavity 24 was generated, which is covered by a further layer 22 and delimited by walls 21, an antenna 23 being evaporated on layer 22 which is connected to the metallic side walls 15 'via conductor tracks also produced by metallic vapor deposition.
- the cavity 24 is used, for example in the case of RF chips, to achieve less damping of the electromagnetic waves on the chip.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Micromachines (AREA)
- Optical Couplings Of Light Guides (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102018008254 | 2018-10-18 | ||
PCT/EP2019/078141 WO2020079110A2 (de) | 2018-10-18 | 2019-10-17 | Verfahren zur herstellung von modulen |
Publications (1)
Publication Number | Publication Date |
---|---|
EP3867945A2 true EP3867945A2 (de) | 2021-08-25 |
Family
ID=68501560
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19800919.3A Pending EP3867945A2 (de) | 2018-10-18 | 2019-10-17 | Verfahren zur herstellung von modulen für mikroelektronische bauelemente mittels eines fotopolymerisationsverfahrens |
Country Status (2)
Country | Link |
---|---|
EP (1) | EP3867945A2 (de) |
WO (1) | WO2020079110A2 (de) |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19826971C2 (de) | 1998-06-18 | 2002-03-14 | Reiner Goetzen | Verfahren zum mechanischen und elektrischen Verbinden von Systembauteilen |
JP2001176898A (ja) * | 1999-12-20 | 2001-06-29 | Mitsui High Tec Inc | 半導体パッケージの製造方法 |
-
2019
- 2019-10-17 EP EP19800919.3A patent/EP3867945A2/de active Pending
- 2019-10-17 WO PCT/EP2019/078141 patent/WO2020079110A2/de unknown
Also Published As
Publication number | Publication date |
---|---|
WO2020079110A3 (de) | 2020-08-13 |
WO2020079110A2 (de) | 2020-04-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE10157280B4 (de) | Verfahren zum Anschließen von Schaltungseinheiten | |
DE102012109905B4 (de) | Verfahren zur Herstellung einer Vielzahl von optoelektronischen Halbleiterbauteilen | |
WO2014154632A1 (de) | Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements | |
DE102015111492B4 (de) | Bauelemente und Verfahren zur Herstellung von Bauelementen | |
EP0152818A2 (de) | Leistungshalbleitermodul | |
DE102015106444A1 (de) | Optoelektronische Bauelementanordnung und Verfahren zur Herstellung einer Vielzahl von optoelektronischen Bauelementanordnungen | |
DE102013103580A1 (de) | Dreidimensional gestapelte Gehäuseanordnung und Verfahren zum Herstellen derselben | |
DE102015115824A1 (de) | Optoelektronisches Bauelement | |
DE10356885A1 (de) | Verfahren zum Gehäusen von Bauelementen und gehäustes Bauelement | |
DE102013202910A1 (de) | Optoelektronisches Bauelement und Verfahren zu seiner Herstellung | |
WO2016202794A1 (de) | Bauelement und verfahren zur herstellung eines bauelements | |
DE112006003664B4 (de) | Herstellung eines QFN-Gehäuses für eine integrierte Schaltung und damit hergestelltes QFN-Gehäuse und Verwendung eines Leiterrahmens dabei | |
WO2017016957A1 (de) | Verfahren zur herstellung eines bauelements und ein bauelement | |
EP1522095B1 (de) | Verfahren zur herstellung eines bauelementes mit tiefliegenden anschlussflächen | |
WO2015055670A1 (de) | Optoelektronisches bauelement und verfahren zu seiner herstellung | |
DE102018104382A1 (de) | Optoelektronisches bauelement und herstellungsverfahren | |
DE102014103034A1 (de) | Optoelektronisches Bauelement und Verfahren zu seiner Herstellung | |
WO2020079110A2 (de) | Verfahren zur herstellung von modulen | |
DE102015100575A1 (de) | Verfahren zur Herstellung einer Mehrzahl von optoelektronischen Halbleiterbauelementen und optoelektronisches Halbleiterbauelement | |
DE10153615C1 (de) | Verfahren zur Herstellung von elektronischen Bauteilen | |
WO2021122112A1 (de) | Verfahren zur herstellung von halbleiterbauelementen und halbleiterbauelement | |
DE19826971C2 (de) | Verfahren zum mechanischen und elektrischen Verbinden von Systembauteilen | |
DE102004010703B4 (de) | Bauelement mit WLP-fähiger Verkapselung und Herstellverfahren | |
DE102016202548B3 (de) | Verfahren zur Herstellung eines elektronischen Bauelements und elektronisches Bauelement | |
DE10147375A1 (de) | Elektronisches Bauteil mit einem Halbleiterchip und Verfahren zur Herstellung desselben |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: UNKNOWN |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
17P | Request for examination filed |
Effective date: 20210518 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
DAV | Request for validation of the european patent (deleted) | ||
DAX | Request for extension of the european patent (deleted) | ||
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: EXAMINATION IS IN PROGRESS |