WO2020079110A3 - Verfahren zur herstellung von modulen für mikroelektronische bauelemente mittels eines fotopolymerisationsverfahrens - Google Patents

Verfahren zur herstellung von modulen für mikroelektronische bauelemente mittels eines fotopolymerisationsverfahrens Download PDF

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Publication number
WO2020079110A3
WO2020079110A3 PCT/EP2019/078141 EP2019078141W WO2020079110A3 WO 2020079110 A3 WO2020079110 A3 WO 2020079110A3 EP 2019078141 W EP2019078141 W EP 2019078141W WO 2020079110 A3 WO2020079110 A3 WO 2020079110A3
Authority
WO
WIPO (PCT)
Prior art keywords
modules
wafer
components
optical
respective component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2019/078141
Other languages
English (en)
French (fr)
Other versions
WO2020079110A2 (de
Inventor
Reiner Götzen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to EP19800919.3A priority Critical patent/EP3867945A2/de
Publication of WO2020079110A2 publication Critical patent/WO2020079110A2/de
Publication of WO2020079110A3 publication Critical patent/WO2020079110A3/de
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/141—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being on at least the sidewalls of the semiconductor body
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L2200/00—Solutions for specific problems relating to chemical or physical laboratory apparatus
    • B01L2200/12—Specific details about manufacturing devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/241—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements
    • H10W44/248—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements for antennas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
    • H10W72/01938—Manufacture or treatment of bond pads using blanket deposition in gaseous form, e.g. by CVD or PVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01951—Changing the shapes of bond pads
    • H10W72/01955—Changing the shapes of bond pads by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optical Couplings Of Light Guides (AREA)
  • Micromachines (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

Die Erfindung betrifft ein Verfahren zur Herstellung von Modulen für elektronische und/oder optische und/oder fluidische Anwendungen, ausgehend von mindestens einem Wafer (1), auf dessen Oberfläche mikroelektronische Bauelemente (2) in regelmäßiger und rechteckiger Anordnung vorgesehen sind, wobei elektrische Kontakte (4) im Randbereich des jeweiligen Bauteils, optische Anschlüsse auch an der Oberfläche des jeweiligen Bauteils angeordnet sind, wobei mittels eines Fotopolymerisationsverfahrens (RMPD-Mask-Verfahren) schichtweise fest mit dem Wafer (1) verbundene dielektrische Packungsstrukturen (17) um das jeweilige Bauteil herum und/oder oberhalb der Bauteile für alle diese Bauteile parallel und gleichzeitig generiert werden, wobei hierbei ebenso die elektrischen und/oder optischen Kontaktierungen für jedes Bauteil hergestellt werden, wonach zum Schluss die so erzeugten Module nach Fertigstellung aller Anschlüsse durch Schneiden des Wafers im Bereich (16) zwischen den einzelnen Modulen vereinzelt werden.
PCT/EP2019/078141 2018-10-18 2019-10-17 Verfahren zur herstellung von modulen Ceased WO2020079110A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP19800919.3A EP3867945A2 (de) 2018-10-18 2019-10-17 Verfahren zur herstellung von modulen für mikroelektronische bauelemente mittels eines fotopolymerisationsverfahrens

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102018008254 2018-10-18
DE102018008254.8 2018-10-18

Publications (2)

Publication Number Publication Date
WO2020079110A2 WO2020079110A2 (de) 2020-04-23
WO2020079110A3 true WO2020079110A3 (de) 2020-08-13

Family

ID=68501560

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2019/078141 Ceased WO2020079110A2 (de) 2018-10-18 2019-10-17 Verfahren zur herstellung von modulen

Country Status (2)

Country Link
EP (1) EP3867945A2 (de)
WO (1) WO2020079110A2 (de)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001176898A (ja) * 1999-12-20 2001-06-29 Mitsui High Tec Inc 半導体パッケージの製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19826971C2 (de) 1998-06-18 2002-03-14 Reiner Goetzen Verfahren zum mechanischen und elektrischen Verbinden von Systembauteilen
US7468544B2 (en) * 2006-12-07 2008-12-23 Advanced Chip Engineering Technology Inc. Structure and process for WL-CSP with metal cover

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001176898A (ja) * 1999-12-20 2001-06-29 Mitsui High Tec Inc 半導体パッケージの製造方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
BERTSCH A ET AL: "Microstereolithography: concepts and applications", EMERGING TECHNOLOGIES AND FACTORY AUTOMATION, 2001. PROCEEDINGS. 2001 8TH IEEE INTERNATIONAL CONFERENCE ON OCT. 15-18, 2001, PISCATAWAY, NJ, USA,IEEE, 15 October 2001 (2001-10-15), pages 289 - 298vol.2, XP032155782, ISBN: 978-0-7803-7241-2, DOI: 10.1109/ETFA.2001.997697 *
DIPL REINER ING ET AL: "Generative Serienproduktion von Mikrokomponenten Technologieführer aus dem Mittelstand", RTEJOURNAL AUSGABE, 2004, XP055671092, Retrieved from the Internet <URL:https://www.rtejournal.de/ausgabe1/26> [retrieved on 20200224] *

Also Published As

Publication number Publication date
EP3867945A2 (de) 2021-08-25
WO2020079110A2 (de) 2020-04-23

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