EP3734828A1 - Dispositif de conversion de puissance - Google Patents

Dispositif de conversion de puissance Download PDF

Info

Publication number
EP3734828A1
EP3734828A1 EP17936427.8A EP17936427A EP3734828A1 EP 3734828 A1 EP3734828 A1 EP 3734828A1 EP 17936427 A EP17936427 A EP 17936427A EP 3734828 A1 EP3734828 A1 EP 3734828A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor device
control
pulse width
leg
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP17936427.8A
Other languages
German (de)
English (en)
Other versions
EP3734828A4 (fr
EP3734828B1 (fr
Inventor
Hiroto Mizutani
Takaaki TAKAHARA
Hiroyasu Iwabuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of EP3734828A1 publication Critical patent/EP3734828A1/fr
Publication of EP3734828A4 publication Critical patent/EP3734828A4/fr
Application granted granted Critical
Publication of EP3734828B1 publication Critical patent/EP3734828B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/01—Resonant DC/DC converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33573—Full-bridge at primary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/06—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/007—Plural converter units in cascade
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a power conversion apparatus and more particularly to a power conversion apparatus that converts input power from an AC power supply to desired DC power.
  • a power conversion apparatus that converts AC power supplied from an AC power supply to DC power while isolating the same and supplies the DC power to a DC load is typically configured with two converters: a power converter converting AC power to DC power; and an isolated power converter outputting desired DC power using an isolation transformer.
  • a power conversion apparatus that integrates two converters into one converter to achieve higher efficiency is proposed (for example, see Japanese Patent Laying-Open No. 2012-249415 (PTL 1)).
  • 2012-249415 includes an AC/DC converter circuit including a power factor improvement unit and a current resonant converter unit, in which a first switch element Q1 and a second switch element Q2 of the current resonant converter unit are common to the switch elements of the power factor improvement unit.
  • the output voltage of the power factor improvement unit is controlled by changing the ON duty of switch elements Q1 to Q4 and the output voltage of the AC/DC converter circuit is controlled by changing the switching frequency of switch elements Q1 to Q4, and in addition, the dead time control of switch elements Q1 to Q2 and Q3 to Q4 is performed in accordance with the ON duty of switch elements Q1 to Q4, whereby the power factor is improved.
  • a power conversion apparatus performs power conversion between an AC power supply and a load and includes an inverter circuit including a first leg, a second leg, a third leg, and a DC capacitor connected in parallel.
  • the first leg has a first semiconductor device and a second semiconductor device connected in series, and a first AC end that is a connection point between the first semiconductor device and the second semiconductor device is connected to one end of the AC power supply.
  • the second leg has a third semiconductor device and a fourth semiconductor device connected in series.
  • the third leg has a fifth semiconductor device and a sixth semiconductor device connected in series. A connection point between the fifth semiconductor device and the sixth semiconductor device is connected to another end of the AC power supply.
  • the first semiconductor device, the third semiconductor device, and the fifth semiconductor device are connected.
  • the power conversion apparatus further includes: a transformer having a primary-side winding and a secondary-side winding, the primary-side winding having one end connected to the first AC end and another end connected to a second AC end that is a connection point between the third semiconductor device and the fourth semiconductor device, the secondary-side winding being magnetically coupled to the primary-side winding; a parallel resonance reactor connected in parallel with the primary-side winding of the transformer; a secondary-side rectifying circuit to rectify AC output from the secondary-side winding of the transformer; an output smoothing circuit disposed between the secondary-side rectifying circuit and the load and including at least one smoothing capacitor; and a control circuit to control the inverter circuit.
  • the control circuit performs at least pulse width modulation control on the first leg and selects to perform pulse width modulation control and pulse frequency modulation control, to perform pulse width modulation control and phase shift modulation control, or to perform pulse width modulation control, pulse frequency modulation control, and phase shift modulation control on the second leg, based on comparison of a voltage conversion ratio between DC voltage of the DC capacitor and output voltage to the load with at least one threshold.
  • the control circuit performs at least pulse width modulation control on the first leg and selects to perform pulse width modulation control and pulse frequency modulation control, to perform pulse width modulation control and phase shift modulation control, or to perform pulse width modulation control, pulse frequency modulation control, and phase shift modulation control on the second leg, based on comparison of a voltage conversion ratio between DC voltage of the DC capacitor and output voltage to the load with at least one threshold.
  • This configuration can reduce power loss of the semiconductor devices and the magnetic components.
  • a power conversion apparatus in a first embodiment is applied to a power supply system centering on a charger of an electric vehicle.
  • FIG. 1 is a diagram illustrating a configuration of a power conversion apparatus 5000 according to the first embodiment.
  • Power conversion apparatus 5000 converts AC power supplied from a commercial AC power supply 1 to DC power and supplies the DC power to a DC load 13.
  • Power conversion apparatus 5000 includes a power factor-improving reactor 2, a DC capacitor 4, a third leg 300, an inverter circuit 655, a series resonance reactor 7, a parallel resonance reactor 8, a transformer 9, a series resonance capacitor 10, a secondary-side rectifying circuit 11, and an output smoothing circuit 1200.
  • Inverter circuit 655 includes a first leg 500 and a second leg 600.
  • AC power supply 1 is, for example, a commercial AC system or a self-generator.
  • DC load 13 is, for example, a high voltage battery for vehicle driving or a lead-acid battery that is a power supply for vehicle electric components.
  • DC load 13 may be a DC load that requires isolation from other AC inputs and may be configured with, for example, an electric double layer capacitor (EDLC).
  • EDLC electric double layer capacitor
  • First leg 500, second leg 600, third leg 300, and DC capacitor 4 are connected in parallel.
  • First leg 500 includes a first semiconductor device 501 and a second semiconductor device 502 connected in series.
  • Second leg 600 includes a third semiconductor device 601 and a fourth semiconductor device 602 connected in series.
  • Third leg 300 includes a fifth semiconductor device 301 and a sixth semiconductor device 302 connected in series.
  • First semiconductor device 501, third semiconductor device 601, and fifth semiconductor device 301 are connected.
  • Second semiconductor device 502, fourth semiconductor device 602, and sixth semiconductor device 302 are connected.
  • First semiconductor device 501 is positioned diagonally to fourth semiconductor device 602.
  • Second semiconductor device 502 is positioned diagonally to third semiconductor device 601.
  • Two semiconductor devices positioned diagonally to each other that are included in first leg 500 and second leg 600 are set to the ON state, whereby rectangular wave voltage is applied to the primary-side terminal of transformer 9 and power is transmitted to DC load 13.
  • a diode is connected in anti-parallel with and a capacitor is connected in parallel with each of first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, and fourth semiconductor device 602.
  • the diode connected in anti-parallel with a semiconductor device may be an external diode or may be a body diode of the semiconductor device.
  • the capacitor connected in parallel with a semiconductor device may be an external capacitor or may be a parasitic capacitor of the semiconductor device.
  • a first AC end ND1 that is a connection point between first semiconductor device 501 and second semiconductor device 502 is connected to one end of AC power supply 1 through power factor-improving reactor 2.
  • Third semiconductor device 601 and fourth semiconductor device 602 are connected at a second AC end ND2.
  • a third AC end ND3 that is a connection point between fifth semiconductor device 301 and sixth semiconductor device 302 is connected to the other end of AC power supply 1.
  • Power factor-improving reactor 2 is a current decreasing reactor having one end connected to AC power supply 1 and the other end connected to inverter circuit 655. Power factor-improving reactor 2 may be connected to another terminal side of AC power supply 1 or may be connected in a distributed manner to each of both ends of AC power supply 1.
  • the side connected to AC power supply 1 with respect to transformer 9 is referred to as the primary side, and the side connected to DC load 13 with respect to transformer 9 is referred to as the secondary side.
  • transformer 9 One end of the primary-side winding of transformer 9 is connected to first AC end ND1 through series resonance reactor 7. The other end of the primary-side winding of transformer 9 is connected to second AC end ND2 through series resonance capacitor 10. The secondary-side winding of transformer 9 is magnetically coupled to the primary winding.
  • Parallel resonance reactor 8 is connected in parallel with the primary-side winding of transformer 9.
  • Series resonance reactor 7, parallel resonance reactor 8, and series resonance capacitor 10 constitute a resonance circuit.
  • Secondary-side rectifying circuit 11 rectifies AC output from the secondary-side winding of transformer 9.
  • Secondary-side rectifying circuit 11 includes a plurality of diodes.
  • Output smoothing circuit 1200 is disposed between secondary-side rectifying circuit 11 and DC load 13.
  • Output smoothing circuit 1200 includes a first output smoothing capacitor 1201 and a second output smoothing capacitor 1203 connected in parallel.
  • Output smoothing circuit 1200 includes an output smoothing reactor 1202 disposed between first output smoothing capacitor 1201 and second output smoothing capacitor 1203.
  • Power conversion apparatus 5000 includes a first voltage detector 675, a second voltage detector 676, a third voltage detector 677, a first current detector 678, and a second current detector 679.
  • First voltage detector 675 detects DC voltage Vdc of DC capacitor 4.
  • Second voltage detector 676 detects output voltage Vout by detecting voltage across both ends of second output smoothing capacitor 1203.
  • Third voltage detector 677 detects voltage vac of AC power supply 1.
  • First current detector 678 detects current iac of AC power supply 1.
  • Second current detector 679 detects output current iout.
  • control circuit 14 The detected values of the voltages and the currents are supplied to a control circuit 14, so that control circuit 14 performs arithmetic operation.
  • Control circuit 14 outputs the arithmetic operation results to the gate terminals of semiconductor devices 301 to 302, 501 to 502, and 601 to 602.
  • the ON state and the OFF state of fifth semiconductor device 301 and sixth semiconductor device 302 are switched in accordance with the polarity of voltage input from AC power supply 1. Specifically, in a time period in which voltage vac of AC power supply 1 has positive polarity, sixth semiconductor device 302 is in the ON state and fifth semiconductor device 301 is in the OFF state. On the other hand, in a time period in which voltage vac of AC power supply 1 has negative polarity, fifth semiconductor device 301 is in the ON state and sixth semiconductor device 302 is in the OFF state.
  • Fifth semiconductor device 301 and sixth semiconductor device 302 are active semiconductor. Conduction loss of active semiconductor is reduced by performing synchronous rectification.
  • Fifth semiconductor device 301 and sixth semiconductor device 302 are not limited to insulated gate bipolar transistors (IGBTs) or metal oxide semiconductor field effect transistors (MOSFETs), and active semiconductor such as SiC (silicon carbide)-MOSFETs, gallium nitride (GaN)-FETs, and GaN-HEMTs (high electron mobility transistors) may be used.
  • IGBTs insulated gate bipolar transistors
  • MOSFETs metal oxide semiconductor field effect transistors
  • active semiconductor such as SiC (silicon carbide)-MOSFETs, gallium nitride (GaN)-FETs, and GaN-HEMTs (high electron mobility transistors) may be used.
  • Equation (1) and Equation (2) voltage vac and current iac of AC power supply 1 with an input power factor of 1 are represented by Equation (1) and Equation (2).
  • Power pac of AC power supply 1 is represented by Equation (3) and transmitted to DC load 13.
  • output current iout supplied to DC load 13 is represented by Equation (4).
  • co is the angular frequency of voltage vac and current iac of AC power supply 1 and represented by Equation (5).
  • the period of voltage vac and current iac of AC power supply 1 is Tac.
  • Equation (6) n is the ratio of primary turns N1 to secondary turns N2 of transformer 9 and represented by Equation (7).
  • fr is a resonance frequency calculated from the inductance (Lr) of series resonance reactor 7 and the capacitance (Cr) of series resonance capacitor 10 and represented by Equation (8).
  • k is the ratio of the inductance (Lm) of parallel resonance reactor 8 to the inductance (Lr) of series resonance reactor 7 and represented by Equation (9).
  • Q is the resonance sharpness and represented by Equation (10).
  • fs is the switching frequency of semiconductor devices 501 to 502 and 601 to 602.
  • FIG. 2 is a diagram illustrating the characteristics of the voltage conversion ratio in Equation (6).
  • the horizontal axis in FIG. 2 represents the ratio of switching frequency fs to resonance frequency fr, that is, normalized frequency.
  • the vertical axis represents the voltage conversion ratio.
  • a voltage conversion ratio higher than the turn ratio n can be obtained.
  • the switching frequency having a larger value is selected. Of two switching frequencies, the switching frequency having a smaller value may be selected.
  • the sensitivity of the voltage conversion ratio to the normalized frequency is high.
  • a voltage conversion ratio equal to or smaller than the reciprocal (1/n) of the turn ratio n is obtained, and the sensitivity of the voltage conversion ratio to the normalized frequency is deteriorated. Therefore, when step-down control of output voltage Vout is performed in a wide range only by frequency modulation control, the frequency variation range has to be significantly increased. Consequently, power loss of the semiconductor devices and the magnetic components increases, leading to reduction in power conversion efficiency and possibly destruction of the semiconductor devices and the magnetic components.
  • Power conversion apparatus 5000 in the present embodiment therefore simultaneously performs high power factor control and output control by selecting and performing at least one of pulse frequency modulation control and phase shift control, in addition to pulse width modulation control, for second leg 600, based on the comparison of a target value of the voltage conversion ratio set as desired with a threshold.
  • voltage control in a wide range becomes possible without significantly increasing the frequency variation range.
  • FIG. 3 is a diagram for explaining two thresholds of the power conversion ratio.
  • threshold TH1 and threshold TH2 can be set as follow.
  • FIG. 4 is a diagram illustrating a control method in the first embodiment.
  • first semiconductor device 501 and second semiconductor device 502 that constitute first leg 500 perform high power factor control
  • third semiconductor device 601 and the fourth semiconductor device constitute second leg 600 perform output control
  • fifth semiconductor device 301 and sixth semiconductor device 302 that constitute third leg 300 perform rectifying operation in accordance with the polarity of voltage of AC power supply 1.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on a first control method, in a region in which target value M* of voltage conversion ratio M is larger than threshold TH1.
  • Control circuit 14 controls first leg 500 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 allows third leg 300 to perform rectification control.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on a second control method, in a region in which target value M* of voltage conversion ratio M is equal to or smaller than threshold TH1 and is larger than threshold TH2.
  • Control circuit 14 controls first leg 500 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control, pulse frequency modulation control, and phase shift modulation control.
  • Control circuit 14 allows third leg 300 to perform rectification control.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on a third control method, in a region in which target value M* of voltage conversion ratio M is equal to or smaller than threshold TH2.
  • Control circuit 14 controls first leg 500 by pulse width modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control and phase shift modulation control.
  • Control circuit 14 allows third leg 300 to perform rectification control.
  • pulse width modulation control is essential for inverter circuit 655 to operate. Further, when it is necessary to lower the output voltage relative to the input voltage, only with frequency modulation control, higher frequency is limitlessly needed to cause excessive loss. On the other hand, if the phase shift amount is limitlessly increased in phase shift control, reactive power becomes excessive to cause excessive loss. Based on these, appropriate control can be achieved by combining three kinds of modulation control. In addition, in the first embodiment, voltage control is possible in a narrow frequency band. In the first embodiment, considering that phase shift is to lower the output voltage relative to the input voltage, phase shift is used in a region in which the power conversion ratio is small.
  • Control circuit 14 inverts the timing when fifth semiconductor device 301 is conducting and the timing when sixth semiconductor device 302 is conducting, thereby allowing third leg 300 to perform rectification operation.
  • Control circuit 14 switches the ON state and the OFF state of fifth semiconductor device 301 and sixth semiconductor device 302 in accordance with the polarity of voltage input from AC power supply 1. Specifically, control circuit 14 sets sixth semiconductor device 302 to the ON state and sets fifth semiconductor device 301 to the OFF state in a time period in which voltage vac of AC power supply 1 has positive polarity. On the other hand, control circuit 14 sets fifth semiconductor device 301 to the ON state and sets sixth semiconductor device 302 to the OFF state in a time period in which voltage vac of AC power supply 1 has negative polarity.
  • Control circuit 14 regulates current iac of AC power supply 1 to a high power factor by controlling first semiconductor device 501 and second semiconductor device 502 that constitute first leg 500, using pulse width modulation control.
  • Power conversion apparatus 5000 has the configuration of a bridgeless rectifier and therefore has to switch the duty ratio in accordance with the polarity of voltage vac of AC power supply 1.
  • Duty ratio D501 and duty ratio D502 of first leg 500 are defined as in the following equations.
  • D 501 v ac V dc
  • D 502 V dc ⁇ v ac V dc
  • Vdc in Equation (13) and Equation (14) is voltage of DC capacitor 4.
  • FIG. 5 is a duty ratio trajectory diagram for duty ratio D501 and duty ratio D502 when voltage of AC power supply 1 has positive polarity.
  • voltage of AC power supply 1 is zero, and therefore duty ratio D501 is extremely close to zero and duty ratio D502 is extremely close to one.
  • control circuit 14 switches first semiconductor device 501 at duty ratio D501 in Equation (13) and controls second semiconductor device 502 at duty ratio D502 in Equation (14).
  • FIG. 6 is a duty ratio trajectory diagram for duty ratio D501 and duty ratio D502 when voltage of AC power supply 1 has negative polarity.
  • voltage of AC power supply 1 is zero, and therefore duty ratio D501 is extremely close to one and duty ratio D502 is extremely close to zero.
  • control circuit 14 switches first semiconductor device 501 at the duty ratio in Equation (14) and switches second semiconductor device 502 at the duty ratio in Equation (13).
  • the smaller duty ratio of duty ratio D501 and duty ratio D502 is defined as low duty ratio Dlimit.
  • D limit min D 501
  • D 502 min v ac V dc V dc ⁇ v ac V dc
  • first semiconductor device 501 and second semiconductor device 502 irrespective of the magnitude relation between the threshold of the voltage conversion ratio and the target value of the voltage conversion ratio set as desired, high power factor control is performed using pulse width modulation control by generating a gate signal while switching the duty ratio in accordance with the voltage polarity of AC power supply 1.
  • the semiconductor devices are not limited to insulated gate bipolar transistors (IGBTs) or metal oxide semiconductor field effect transistors (MOSFETs), and SiC (silicon carbide)-MOSFETs, GaN (gallium nitride)-FETs, and GaN-HEMTs (high electron mobility transistors) may be used.
  • FIG. 7 is a diagram illustrating an example of gate pulses for first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, and fourth semiconductor device 602 in the first control method.
  • First semiconductor device 501 and second semiconductor device 502 are subjected to high power factor control using pulse width modulation control and pulse frequency modulation control.
  • Third semiconductor device 601 and fourth semiconductor device 602 are subjected to output control using pulse width modulation control and pulse frequency modulation control.
  • the timing when first semiconductor device 501 turns on and the timing when fourth semiconductor device 602 turns on are synchronized with each other, and the timing when second semiconductor device 502 turns off and the timing when third semiconductor device 601 turns off are synchronized with each other.
  • the pulse width for first semiconductor device 501 and the pulse width for third semiconductor device 601 are equal, and the pulse width for second semiconductor device 502 and the pulse width for fourth semiconductor device 602 are equal.
  • Control circuit 14 controls first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, and fourth semiconductor device 602 such that switching frequency fs common to first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, and fourth semiconductor device 602 changes while those conditions are satisfied.
  • FIG. 8 is a diagram illustrating another example of gate pulses for first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, and fourth semiconductor device 602 in the first control method.
  • the center phase of the gate pulse for first semiconductor device 501 and the center phase of the gate pulse for fourth semiconductor device 602 are synchronized with each other, and the center phase of the gate pulse for second semiconductor device 502 and the center phase of the gate pulse for third semiconductor device 601 are synchronized with each other. Further, the pulse width for first semiconductor device 501 and the pulse width for third semiconductor device 601 are equal, and the pulse width for second semiconductor device 502 and the pulse width for fourth semiconductor device 602 are equal.
  • Control circuit 14 controls first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, and fourth semiconductor device 602 such that switching frequency fs common to first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, and fourth semiconductor device 602 changes while those conditions are satisfied.
  • the duration in which the diagonally-positioned first semiconductor device 501 and fourth semiconductor device 602 turn on simultaneously can be identical to the duration in which the diagonally-positioned second semiconductor device 502 and third semiconductor device 601 turn on simultaneously, thereby enabling stable power supply.
  • phase shift control the pulse phase for second leg 600 is shifted from the pulse phase for first leg 500 by phase shift amount Dps.
  • the phase shift amount is expressed as the duty ratio in accordance with duty ratio D501 and duty ratio D502 of first leg 500.
  • phase shift amount Dps need to be always below duty ratio D501 and duty ratio D502. That is, as shown in Equation (15), phase shift amount Dps has to be always below the smaller duty ratio Dlimit of duty ratio D501 and duty ratio D502. This relation can be represented by Equation (16). D ps ⁇ min v ac V dc V dc ⁇ v ac V dc
  • FIG. 9 is a diagram illustrating the trajectory of duty ratio D501 and duty ratio D502 and the phase shift amount Dps that satisfy the relation in Equation (16).
  • the horizontal axis shows the phase of voltage vac of AC power supply 1.
  • low duty ratio Dlimit is extremely close to zero in principle and fails to satisfy the relation in Equation (16).
  • control phase shift amount Dps_limit represented by Equation (17) is used for control so that the phase shift amount is always equal to or smaller than duty ratio Dlimit.
  • D ps _ limit min D ps D limit
  • phase shift amount Dps obtained by control circuit 14 is equal to or smaller than Dlimit
  • phase shift amount Dps is used for control.
  • phase shift amount Dps obtained by control circuit 14 exceeds Dlimit, Dlimit is used for control.
  • control phase shift amount Dps_limit can be always equal to or smaller than the variable upper limit duty ratio Dlimit, irrespective of the phase of voltage vac of AC power supply 1.
  • FIG. 10 is a diagram illustrating an example of gate pulses for first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, and fourth semiconductor device 602 in the third control method.
  • the initial state of phase shift control is defined as a state in which the timing when first semiconductor device 501 turns on and the timing when fourth semiconductor device 602 turns on are synchronized with each other, and the timing when second semiconductor device 502 turns off and the timing when third semiconductor device 601 turns off are synchronized with each other.
  • the pulse phase for third semiconductor device 601 and the pulse phase for fourth semiconductor device 602 are shifted.
  • the pulse width for first semiconductor device 501 and the pulse width for third semiconductor device 601 are equal
  • the pulse width for second semiconductor device 502 and the pulse width for fourth semiconductor device 602 are equal.
  • Control circuit 14 controls first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, and fourth semiconductor device 602 such that those conditions are satisfied.
  • FIG. 11 is a diagram illustrating another example of gate pulses for first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, and fourth semiconductor device 602 in the third control method.
  • the initial state of phase shift control is defined as a state in which the timing when first semiconductor device 501 turns on and the timing when third semiconductor device 601 turns on are synchronized with each other, and the timing when second semiconductor device 502 turns on and the timing when fourth semiconductor device 602 turns on are synchronized with each other.
  • the pulse phase for third semiconductor device 601 and the pulse phase for fourth semiconductor device 602 are shifted.
  • the pulse width for first semiconductor device 501 and the pulse width for third semiconductor device 601 are equal
  • the pulse width for second semiconductor device 502 and the pulse width for fourth semiconductor device 602 are equal.
  • Control circuit 14 controls first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, and fourth semiconductor device 602 such that those conditions are satisfied.
  • the duration in which the diagonally-positioned first semiconductor device 501 and fourth semiconductor device 602 turn on simultaneously can be identical to the duration in which the diagonally-positioned second semiconductor device 502 and third semiconductor device 601 turn on simultaneously, thereby enabling stable power supply.
  • FIG. 12 is a diagram illustrating an example of gate pulses for first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, and fourth semiconductor device 602 in the second control method.
  • the initial state of phase shift control is defined as a state in which the timing when first semiconductor device 501 turns on and the timing when fourth semiconductor device 602 turns on are synchronized with each other, and the timing when second semiconductor device 502 turns off and the timing when third semiconductor device 601 turns off are synchronized with each other.
  • the pulse phase for third semiconductor device 601 and the pulse phase for fourth semiconductor device 602 are shifted. Further, the pulse width for first semiconductor device 501 and the pulse width for third semiconductor device 601 are equal, and the pulse width for second semiconductor device 502 and the pulse width for fourth semiconductor device 602 are equal.
  • Control circuit 14 controls first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, and fourth semiconductor device 602 such that switching frequency fs common to first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, and fourth semiconductor device 602 changes while those conditions are satisfied.
  • FIG. 13 is a diagram illustrating another example of gate pulses for first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, and fourth semiconductor device 602 in the second control method.
  • the initial state of phase shift control is defined as a state in which the timing when first semiconductor device 501 turns on and the timing when third semiconductor device 601 turns on are synchronized with each other, and the timing when second semiconductor device 502 turns on and the timing when fourth semiconductor device 602 turns on are synchronized with each other.
  • the pulse phase for third semiconductor device 601 and the pulse phase for fourth semiconductor device 602 are shifted. Further, the pulse width for first semiconductor device 501 and the pulse width for third semiconductor device 601 are equal, and the pulse width for second semiconductor device 502 and the pulse width for fourth semiconductor device 602 are equal.
  • Control circuit 14 controls first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, and fourth semiconductor device 602 such that switching frequency fs common to first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, and fourth semiconductor device 602 changes while those conditions are satisfied.
  • the duration in which the diagonally-positioned first semiconductor device 501 and fourth semiconductor device 602 turn on simultaneously can be identical to the duration in which the diagonally-positioned second semiconductor device 502 and third semiconductor device 601 turn on simultaneously, thereby enabling stable power supply.
  • control circuit 14 generates a gate signal based on at least one of frequency modulation control and phase shift control and performs output control, in addition to pulse width modulation control of third semiconductor device 601 and fourth semiconductor device 602.
  • the semiconductor devices are not limited to insulated gate bipolar transistors (IGBTs) or metal oxide semiconductor field effect transistors (MOSFETs), and SiC (silicon carbide)-MOSFETs, GaN (gallium nitride)-FETs, and GaN-HEMTs (high electron mobility transistors) may be used.
  • Control circuit 14 includes a plurality of control blocks.
  • Power conversion apparatus 5000 has a constant power (CP) control mode in which input power pac (lac ⁇ Vac ⁇ power factor) is constant and a constant current (CC) control mode in which output current iout is constant.
  • CP constant power
  • CC constant current
  • FIG. 14 is a diagram illustrating a plurality of control blocks serving to perform the first control method.
  • control block 151 brings gate signal g5 of fifth semiconductor device 301 to Low level to turn off fifth semiconductor device 301 and brings gate signal g6 of sixth semiconductor device 302 to High level to turn on sixth semiconductor device 302.
  • control block 151 brings gate signal g5 of fifth semiconductor device 301 to High level to turn on fifth semiconductor device 301 and brings gate signal g6 of sixth semiconductor device 302 to Low level to turn off sixth semiconductor device 302.
  • control block 152 In the CP control mode, control block 152 outputs the externally applied current command value iac_ref_cp of AC power supply 1 for CP control mode, as current command value iac_ref of AC power supply 1. In the CC control mode, control block 152 outputs current command value iac_ref_cp of AC power supply 1 for the CC control mode that is obtained by performing proportional integral control of the feedback amount obtained by subtracting DC voltage Vdc of DC capacitor 4 from voltage command value Vdc_ref of DC capacitor 4, as current command value iac_ref of AC power supply 1.
  • Control block 153 generates command value D501c of duty ratio D501 and command value D502c of duty ratio D502, based on voltage vac of AC power supply 1, effective voltage Vac of AC power supply 1, current iac of AC power supply 1, current command value iac_ref of AC power supply 1, DC voltage Vdc of DC capacitor 4, and DC voltage command value Vdc_ref of DC capacitor 4.
  • control block 154 When voltage vac of AC power supply 1 has positive polarity, control block 154 outputs command value D501c of duty ratio D501 as command value D1c of the duty ratio of first semiconductor device 501. When voltage vac of AC power supply 1 has negative polarity, control block 154 outputs command value D502c of duty ratio D502 as command value D1c of the duty ratio of first semiconductor device 501.
  • control block 155 When voltage vac of AC power supply 1 has positive polarity, control block 155 outputs command value D502c of duty ratio D502 as command value D2c of the duty ratio of second semiconductor device 502. When voltage vac of AC power supply 1 has negative polarity, control block 155 outputs command value D501c of duty ratio D501 as command value D2c of the duty ratio of second semiconductor device 502.
  • control block 157 In the CC control mode, control block 157 outputs the externally applied current command value iout_ref_cc of output current for the CC control mode, as current command value iout_ref of output current. In the CP control mode, control block 157 outputs current command value iout_ref_cc of output current for the CP control mode that is obtained by performing proportional integral control of the feedback amount obtained by subtracting DC voltage Vdc of DC capacitor 4 from voltage command value Vdc_ref of DC capacitor 4, as current command value iout ref of output current.
  • Control block 169 calculates differential current by subtracting output current iout from command value iout ref of output current output from control block 157 and performs proportional control of the differential current to output command value fs_ref of switching frequency.
  • control block 165 brings first gate signal g11 for the first leg to High level and brings second gate signal g12 for the first leg to Low level.
  • command value D502c of duty ratio D502 output from control block 153 is equal to or larger than a carrier wave having a frequency component of command value fs ref of switching frequency output from control block 169, control block 165 brings first gate signal g11 for the first leg to Low level and brings second gate signal g12 for the first leg to High level.
  • control block 175 brings first gate signal g21 for the second leg to High level and brings second gate signal g22 for the second leg to Low level.
  • command value D501c of duty ratio D501 output from control block 153 is equal to or larger than a carrier wave having a frequency component of command value fs ref of switching frequency output from control block 169, control block 175 brings first gate signal g21 for the second leg to Low level and brings second gate signal g22 for the second leg to High level.
  • control block 167 When voltage vac of AC power supply 1 has positive polarity, control block 167 outputs first gate signal g11 for the first leg as gate signal g1 of first semiconductor device 501 and outputs second gate signal g12 for the first leg as gate signal g2 of second semiconductor device 502. When voltage vac of AC power supply 1 has negative polarity, control block 167 outputs second gate signal g12 for the first leg as gate signal g1 of first semiconductor device 501 and outputs first gate signal g11 for the first leg as gate signal g2 of second semiconductor device 502.
  • control block 168 When voltage vac of AC power supply 1 has positive polarity, control block 168 outputs first gate signal g21 for the second leg as gate signal g3 of third semiconductor device 601 and outputs second gate signal g22 for the second leg as gate signal g4 of fourth semiconductor device 602. When voltage vac of AC power supply 1 has negative polarity, control block 168 outputs second gate signal g22 for the second leg as gate signal g3 of third semiconductor device 601 and outputs first gate signal g21 for the second leg as gate signal g4 of fourth semiconductor device 602.
  • FIG. 15 is a diagram illustrating a plurality of control blocks serving to perform the third control method.
  • a plurality of control blocks in the third control method differ from a plurality of control blocks in the first control method in that a plurality of control blocks in the third control method include control blocks 156, 158, and 159 instead of control block 169 and includes control blocks 176 and 177 instead of control blocks 165 and 175.
  • control block 156 When command value D1c of the duty ratio of first semiconductor device 501 is smaller than command value D2c of the duty ratio of second semiconductor device 502, control block 156 outputs command value D1c of the duty ratio of first semiconductor device 501 as low duty ratio Dlimit.
  • command value D1c of the duty ratio of first semiconductor device 501 is equal to or larger than command value D2c of the duty ratio of second semiconductor device 502, control block 156 outputs command value D2c of the duty ratio of second semiconductor device 502 as low duty ratio Dlimit.
  • Control block 158 outputs command value Dpsc of phase shift amount Dps that is obtained by performing proportional control of differential current as the feedback amount obtained by subtracting output current iout form command value iout_ref of output current.
  • control block 159 When low duty ratio Dlimit is equal to or larger than command value Dpsc, control block 159 outputs command value Dpsc as command value Dps_limitc of control phase shift amount Dps_limit. When low duty ratio Dlimit is smaller than command value Dpsc, control block 159 outputs low duty ratio Dlimit as command value Dps limitc of control phase shift amount Dps_limit.
  • control block 176 brings first gate signal g11 for the first leg to High level and brings second gate signal g12 for the first leg to Low level.
  • command value D502c of duty ratio D502 is equal to or larger than a carrier wave having a frequency component of the fixed switching frequency fs0
  • control block 176 brings first gate signal g11 for the first leg to Low level and brings second gate signal g12 for the first leg to High level.
  • Control block 177 obtains the sum W of command value D2c of the duty ratio of second semiconductor device 502 (when voltage vac of AC power supply 1 has positive polarity) or command value D1c of the duty ratio of first semiconductor device 501 (when voltage vac of AC power supply 1 has negative polarity) and command value Dps_limitc of control phase shift amount Dps_limit output from control block 159.
  • control block 177 sets second gate signal g22 for the second leg to High level and sets first gate signal g11 for the first leg to Low level.
  • control block 177 sets second gate signal g22 for the second leg to Low level and sets first gate signal g11 for the first leg to High level.
  • control block 177 sets second gate signal g22 for the second leg to Low level and sets first gate signal g11 for the first leg to High level.
  • control block 177 sets second gate signal g22 for the second leg to Low level and sets first gate signal g11 for the first leg to High level.
  • FIG. 16 is a diagram illustrating a plurality of control blocks serving to perform the second control method.
  • a plurality of control blocks in the second control method differ from a plurality of control blocks in the first control method in that a plurality of control blocks in the second control method include control blocks 156, 158, 159, and 160 instead of control block 169 and includes control block 166 instead of control block 175.
  • Control blocks 156, 158, and 159 are the same as those described in the third control method and will not be further elaborated.
  • Control block 160 divides output power PW1 obtained by multiplying output voltage Vout by output current iout by input power PW2 obtained by multiplying effective voltage Vac of AC power supply 1 by effective current lac of AC power supply 1 to obtain conversion efficiency ⁇ .
  • Control block 160 performs proportional integration of differential efficiency S ⁇ as the feedback amount obtained by performing subtraction between a predetermined target efficiency ⁇ ref and conversion efficiency ⁇ and outputs command value fs_ref of switching frequency.
  • Control block 166 obtains the sum W of command value D2c of the duty ratio of second semiconductor device 502 (when voltage vac of AC power supply 1 has positive polarity) or command value D1c of the duty ratio of first semiconductor device 501 (when voltage vac of AC power supply 1 has negative polarity) and command value Dps_limitc of control phase shift amount Dps_limit output from control block 159.
  • control block 166 sets second gate signal g22 for the second leg to High level and sets first gate signal g11 for the first leg to Low level.
  • control block 166 sets second gate signal g22 for the second leg to Low level and sets first gate signal g11 for the first leg to High level.
  • control block 166 sets second gate signal g22 for the second leg to Low level and sets first gate signal g11 for the first leg to High level.
  • control block 166 sets second gate signal g22 for the second leg to Low level and sets first gate signal g11 for the first leg to High level.
  • FIG. 17 is a diagram illustrating control block 151 generating gate signal g5 of fifth semiconductor device 301 and gate signal g6 of sixth semiconductor device 302 in third leg 300.
  • Control block 151 includes a comparator 15 and a logical NOT circuit 979.
  • Comparator 15 compares voltage vac of AC power supply 1 detected by third voltage detector 677 with the ground voltage.
  • Logical NOT circuit 979 receives the output of comparator 15.
  • Gate signal g6 of sixth semiconductor device 302 is output from comparator 15.
  • Gate signal g5 of fifth semiconductor device 301 is output from logical NOT circuit 979.
  • control block 151 The operation of control block 151 is described.
  • FIG. 18 is a diagram illustrating control block 152 generating current command value iac_ref of AC power supply 1.
  • Control block 152 includes a subtracter 68, a PI controller 69, and a selector 18.
  • Subtracter 68 subtracts DC voltage Vdc of DC capacitor 4 detected by first voltage detector 675 from voltage command value Vdc_ref of the DC capacitor to obtain the feedback amount.
  • PI controller 68 performs proportional integral control of the output of subtracter 68 to output current command value iac_ref_cc of AC power supply 1 for the CC control mode.
  • Selector 18 receives current command value iac_ref_cc of AC power supply 1 for the CC control mode output from PI controller 68 and current command value iac_ref_cp of AC power supply 1 for the CP control mode.
  • current command value iac_ref_cp is a predetermined target current effective value.
  • a multiplexer may be used instead of selector 18.
  • control block 152 The operation of control block 152 is described.
  • current command value iac_ref_cp of AC power supply 1 for the CP control mode is selected by selector 18 and output as current command value iac_ref of AC power supply 1.
  • current command value iac_ref_cc obtained by subtracter 68 and PI controller 69 is selected by selector 18 and output as current command value iac_ref of AC power supply 1.
  • FIG. 19 is a diagram illustrating control block 153 generating command value D501c of duty ratio D501 and command value D502c of duty ratio D502.
  • Control block 153 includes a divider 969, a multiplier 968, an absolute value output unit 964, an absolute value output unit 963, a subtracter 20, a proportional controller 21, a divider 965, an absolute value output unit 962, a subtracter 967, a divider 966, an adder 23, and a subtracter 25.
  • Divider 969 outputs a value obtained by dividing voltage vac of AC power supply 1 obtained from third voltage detector 677 by effective voltage Vac of AC power supply 1.
  • Multiplier 968 multiplies current command value iac_ref of AC power supply 1 by the output of divider 969 to generate a target sinusoidal current waveform of AC power supply 1 in phase with sinusoidal voltage vac of AC power supply 1.
  • Absolute value output unit 964 outputs the absolute value of the target sinusoidal current waveform of AC power supply 1.
  • Absolute value output unit 963 outputs the absolute value of current iac of AC power supply 1 obtained from first current detector 678.
  • Subtracter 20 calculates the current difference between the absolute value of the target sinusoidal current waveform output from absolute value output unit 964 and the absolute value of current iac of AC power supply 1 output from absolute value output unit 963, as the feedback amount.
  • Proportional controller 21 performs proportional control of the feedback amount output from subtracter 20.
  • Divider 965 divides the output of proportional controller 21 by DC voltage Vdc of DC capacitor 4.
  • Absolute value output unit 962 outputs the absolute value of voltage vac of AC power supply 1 obtained from third voltage detector 677.
  • Subtracter 967 calculates the difference between target value Vdc_ref of voltage of DC capacitor 4 and the absolute value of voltage vac of AC power supply 1 output from absolute value output unit 962.
  • Divider 966 divides the output of subtracter 967 by target value Vdc_ref of voltage of DC capacitor 4 to calculate a feedforward term represented by Equation (14).
  • Adder 23 adds the feedforward term output from divider 966 to the value output from divider 965 to output command value D502c of duty ratio D502.
  • Subtracter 25 subtracts command value D502c of duty ratio D502 from a numerical value "1" to output command value D501c of duty ratio D501.
  • FIG. 20 is a diagram illustrating control block 154 generating duty ratio command value D1c of first semiconductor device 501.
  • Control block 154 includes a multiplexer (MUX) 27 and a comparator 26.
  • MUX multiplexer
  • Comparator 26 compares voltage vac of AC power supply 1 detected by third voltage detector 677 with the ground voltage to output a signal indicating the comparison result.
  • Multiplexer (MUX) 27 receives command value D501c of duty ratio D501 and command value D502c of duty ratio D502. Multiplexer (MUX) 27 outputs one of the inputs command values as command value D1c of the duty ratio of first semiconductor device 501, in accordance with an output signal of comparator 26.
  • control block 154 The operation of control block 154 is described.
  • Multiplexer (MUX) 27 outputs command value D501c of duty ratio D501 as command value D1c of the duty ratio of first semiconductor device 501.
  • FIG. 21 is a diagram illustrating control block 155 generating duty ratio command value D2c of second semiconductor device 502.
  • Control block 155 includes a multiplexer (MUX) 30 and a comparator 29.
  • MUX multiplexer
  • Comparator 29 compares voltage vac of AC power supply 1 detected by third voltage detector 677 with the ground voltage to output a signal indicating the comparison result.
  • Multiplexer (MUX) 30 receives command value D501c of duty ratio D501 and command value D502c of duty ratio D502. Multiplexer (MUX) 30 outputs one of the input command values as command value D2c of the duty ratio of second semiconductor device 502, in accordance with an output signal of comparator 29.
  • control block 155 The operation of control block 155 is described.
  • FIG. 22 is a diagram illustrating control block 156 generating low duty ratio Dlimit.
  • Control block 156 includes a comparator 32 and a multiplexer (MUX) 33.
  • Comparator 32 compares command value D2c of the duty ratio of second semiconductor device 502 with command value D1c of the duty ratio of first semiconductor device 501 to output a signal indicating the comparison result.
  • Multiplexer (MUX) 33 receives command value D2c of the duty ratio of second semiconductor device 502 and command value D1c of the duty ratio of first semiconductor device 501. Multiplexer (MUX) 33 outputs one of the input command values as low duty ratio Dlimit, in accordance with an output signal of comparator 32.
  • control block 156 The operation of control block 156 is described.
  • command value D1c of the duty ratio of first semiconductor device 501 is smaller than command value D2c of the duty ratio of second semiconductor device 502, the output 32 of the comparator is High level.
  • Multiplexer (MUX) 33 outputs command value D1c of the duty ratio of first semiconductor device 501 as low duty ratio Dlimit.
  • command value D1c of the duty ratio of first semiconductor device 501 is equal to or larger than command value D2c of the duty ratio of second semiconductor device 502, the output 32 of the comparator is Low level.
  • Multiplexer (MUX) 33 outputs command value D2c of the duty ratio of second semiconductor device 502 as low duty ratio Dlimit.
  • FIG. 23 is a diagram illustrating control block 157 generating command value iout_ref of output current.
  • Control block 157 includes a subtracter 35, a PI controller 36, and a selector 37.
  • Subtracter 35 subtracts DC voltage Vdc of DC capacitor 4 detected by first voltage detector 675 from voltage command value Vdc_ref of the DC capacitor to obtain the feedback amount.
  • PI controller 36 performs proportional integral control of the output of subtracter 35 to output current command value iout_ref_cp of output current for the CP control mode.
  • Selector 37 receives current command value iout ref cp of output current for the CP control mode output from PI controller 36 and current command value iout_ref_cc of output current for the CC control mode.
  • current command value iout_ref_cc is a predetermined target current effective value.
  • a multiplexer may be used instead of selector 37.
  • control block 157 The operation of control block 157 is described.
  • current command value iout_ref_cc of output current for the CC control mode is selected by selector 37 and output as current command value iout_ref of output current.
  • current command value iout ref cp of output current for the CP control mode obtained by subtracter 35 and PI controller 36 is selected by selector 37 and output as current command value iout_ref of output current.
  • FIG. 24 is a diagram illustrating control block 158 generating command value Dpsc of phase shift amount Dps.
  • Control block 158 includes a subtracter 39a and a proportional controller 40.
  • Subtracter 39a subtracts output current iout detected by second current detector 679 from command value iout ref of output current output from control block 157 in FIG. 23 to calculate differential current as the feedback amount.
  • Proportional controller 40 performs proportional control of the differential current to output command value Dpsc of phase shift amount Dps.
  • FIG. 25 is a diagram illustrating control block 159 generating command value Dps_limitc of control phase shift amount Dps_limit.
  • Control block 159 includes a comparator 41 and a multiplexer (MUX) 42.
  • Comparator 41 compares low duty ratio Dlimit calculated by control block 156 in FIG. 22 with command value Dpsc of phase shift amount Dps calculated by control block 158 in FIG. 24 and outputs a signal indicating the comparison result.
  • Multiplexer (MUX) 42 receives the low duty ratio and command value Dpsc. Multiplexer (MUX) 42 outputs one of the inputs as command value Dps limitc of control phase shift amount Dps limit, in accordance with an output signal of comparator 41.
  • control block 159 The operation of control block 159 is described.
  • FIG. 26 is a diagram illustrating control block 160 generating command value fs_ref of switching frequency.
  • Control block 160 includes a multiplier 44, a multiplier 45, a divider 46, a subtracter 47a, and a PI controller 48.
  • Multiplier 44 multiplies output voltage Vout obtained from second voltage detector 676 by output current iout obtained from second current detector 679 to output output power PW1.
  • Multiplier 45 multiplies effective voltage Vac of AC power supply 1 obtained from third voltage detector 677 by effective current lac of AC power supply 1 obtained from first current detector 678 to output input power PW2.
  • Divider 46 divides output power PW1 by input power PW2 to output conversion efficiency ⁇ .
  • Subtracter 47a performs subtraction between a predetermined target efficiency ⁇ ref and conversion efficiency ⁇ output from divider 46 to calculate differential efficiency S ⁇ as the feedback amount.
  • PI controller 48 performs proportional integral control of differential efficiency S ⁇ to output command value fs_ref of switching frequency. It is noted that input power PW2 is active power that reflects the input power factor.
  • FIG. 27 is a diagram illustrating control block 165 generating gate signals g11 and g12 for semiconductor devices that constitute first leg 500.
  • Control block 165 includes a comparator 49 and a comparator 50.
  • Comparator 49 compares a carrier wave having a frequency component of command value fs_ref of switching frequency with command value D502c of duty ratio D502 calculated by control block 153 in FIG. 19 to set the level of first gate signal g11 for the first leg based on the comparison result.
  • Comparator 50 compares command value D502c of duty ratio D502 calculated by control block 153 in FIG. 19 with a carrier wave having a frequency component of command value fs_ref of switching frequency to set the level of second gate signal g12 for the first leg based on the comparison result.
  • control block 165 The operation of control block 165 is described.
  • command value D502c of duty ratio D502 is smaller than a carrier wave having a frequency component of command value fs_ref of switching frequency
  • first gate signal g11 for the first leg output by comparator 49 goes to High level
  • second gate signal g12 for the first leg output by comparator 50 goes to Low level.
  • command value D502c of duty ratio D502 is equal to or larger than a carrier wave having a frequency component of command value fs_ref of switching frequency
  • first gate signal g11 for the first leg output by comparator 49 goes to Low level
  • second gate signal g12 for the first leg output by comparator 50 goes to High level.
  • FIG. 28 is a diagram illustrating control block 166 generating gate signals g21 and g22 for semiconductor devices that constitute second leg 600.
  • Control block 166 includes a comparator 51, a multiplexer (MUX) 52, an adder 53, a comparator 54, a comparator 55, a logical AND circuit 56, and a logical NOT circuit 57.
  • MUX multiplexer
  • Adder 53 adds command value Dps_limitc of control phase shift amount Dps_limit output from control block 159 to the output value of multiplexer (MUX) 52 to calculate an arithmetic operation value.
  • MUX multiplexer
  • Comparator 54 compares a carrier wave having a frequency component of command value fs_ref of switching frequency calculated by control block 160 with command value Dps limitc and outputs comparison result OP1.
  • Comparator 54 compares a carrier wave having a frequency component of command value fs_ref of switching frequency calculated by control block 160 with the output value of adder 53 and outputs comparison result OP2.
  • Logical AND circuit 56 performs logical AND operation of comparison result OP1 and comparison result OP2, so that second gate signal g22 for the second leg is output.
  • Logical NOT circuit 57 inverts the logical AND of comparison result OP1 and comparison result OP2 and outputs first gate signal g21 for the second leg.
  • FIG. 29 is a diagram illustrating control block 167 generating gate signal g1 of first semiconductor device 501 and gate signal g2 of second semiconductor device 502.
  • Control block 167 includes a comparator 58, a multiplexer 59, and a multiplexer 61.
  • Comparator 58 compares voltage vac of AC power supply 1 detected by third voltage detector 677 with the ground voltage and outputs a signal representing the comparison result.
  • Multiplexer (MUX) 59 receives first gate signal g11 for the first leg and second gate signal g12 for the first leg. Multiplexer (MUX) 59 outputs one of the input gate signals as gate signal g1 of first semiconductor device 501, in accordance with an output signal of comparator 58.
  • Multiplexer (MUX) 61 receives first gate signal g11 for the first leg and second gate signal g12 for the first leg. Multiplexer (MUX) 61 outputs one of the input gate signals as gate signal g2 of second semiconductor device 502, in accordance with an output signal of comparator 58.
  • control block 167 The operation of control block 167 is described.
  • Multiplexer (MUX) 59 outputs first gate signal g11 for the first leg as gate signal g1 of first semiconductor device 501.
  • Multiplexer (MUX) 61 outputs second gate signal g12 for the first leg as gate signal g2 of second semiconductor device 502.
  • Multiplexer (MUX) 59 outputs second gate signal g12 for the first leg as gate signal g1 of first semiconductor device 501.
  • Multiplexer (MUX) 61 outputs first gate signal g11 for the first leg as gate signal g2 of second semiconductor device 502.
  • FIG. 30 is a diagram illustrating control block 168 generating gate signal g3 of third semiconductor device 601 and gate signal g4 of fourth semiconductor device 602.
  • Control block 168 includes a comparator 49, a multiplexer 64, and a multiplexer 65.
  • Comparator 49 compares voltage vac of AC power supply 1 detected by third voltage detector 677 with the ground voltage and outputs a signal representing the comparison result.
  • Multiplexer (MUX) 64 receives first gate signal g21 for the second leg and second gate signal g22 for the second leg. Multiplexer (MUX) 64 outputs one of the input gate signals as gate signal g3 of third semiconductor device 601, in accordance with an output signal of comparator 49.
  • Multiplexer (MUX) 66 receives first gate signal g21 for the second leg and second gate signal g22 for the second leg. Multiplexer (MUX) 66 outputs one of the input gate signals as gate signal g4 of fourth semiconductor device 602, in accordance with an output signal of comparator 49.
  • control block 168 The operation of control block 168 is described.
  • Multiplexer (MUX) 64 outputs first gate signal g21 for the second leg as gate signal g3 of third semiconductor device 601.
  • Multiplexer (MUX) 66 outputs second gate signal g22 for the second leg as gate signal g4 of fourth semiconductor device 602.
  • Multiplexer (MUX) 64 outputs second gate signal g22 for the second leg as gate signal g3 of third semiconductor device 601.
  • Multiplexer (MUX) 66 outputs first gate signal g21 for the second leg as gate signal g4 of fourth semiconductor device 602.
  • FIG. 31 is a diagram illustrating control block 169 generating command value fs_ref of switching frequency.
  • Control block 169 includes a subtracter 39b and a proportional controller 448.
  • Subtracter 39b subtracts output current iout detected by second current detector 679 from command value iout ref of output current output from control block 157 in FIG. 23 to calculate differential current as the feedback amount.
  • Proportional controller 448 performs proportional control of the differential current to output command value fs_ref of switching frequency.
  • FIG. 32 is a diagram illustrating control block 175 generating gate signals g21 and g22 for semiconductor devices that constitute second leg 600.
  • Control block 175 includes a comparator 357 and a comparator 356.
  • Comparator 357 compares a carrier wave having a frequency component of command value fs_ref of switching frequency with command value D501c of duty ratio D501 calculated by control block 153 in FIG. 19 to set the level of first gate signal g21 for the second leg based on the comparison result.
  • Comparator 356 compares command value D501c of duty ratio D501 calculated by control block 153 in FIG. 19 with a carrier wave having a frequency component of command value fs_ref of switching frequency to set the level of second gate signal g22 for the second leg based on the comparison result.
  • control block 175 The operation of control block 175 is described.
  • first gate signal g21 for the second leg output by comparator 357 is High level
  • second gate signal g22 for the second leg output by comparator 356 is Low level.
  • command value D501c of duty ratio D501 is equal to or larger than a carrier wave having a frequency component of command value fs_ref of switching frequency
  • first gate signal g21 for the second leg output by comparator 357 is Low level
  • second gate signal g22 for the second leg output by comparator 356 is High level.
  • FIG. 33 is a diagram illustrating control block 176 generating gate signals g11 and g12 for semiconductor devices that constitute first leg 500.
  • Control block 176 includes a comparator 849 and a comparator 850.
  • Comparator 849 compares a carrier wave having a component of the fixed switching frequency with command value D502c of duty ratio D502 calculated by control block 153 in FIG. 19 to set the level of first gate signal g11 for the first leg based on the comparison result.
  • Comparator 850 compares command value D502c of duty ratio D502 calculated by control block 153 in FIG. 19 with a carrier wave having a component of the fixed switching frequency to set the level of second gate signal g12 for the first leg based on the comparison result.
  • control block 176 The operation of control block 176 is described.
  • first gate signal g11 for the first leg output by comparator 849 is High level
  • second gate signal g12 for the first leg output by comparator 850 is Low level.
  • first gate signal g11 for the first leg output by comparator 849 is Low level
  • second gate signal g12 for the first leg output by comparator 850 is High level.
  • FIG. 34 is a diagram illustrating control block 177 generating gate signals g21 and g22 for semiconductor devices that constitute second leg 600.
  • Control block 177 includes a comparator 851, a multiplexer (MUX) 852, an adder 853, a comparator 854, a comparator 855, a logical AND circuit 856, and a logical NOT circuit 857.
  • MUX multiplexer
  • Adder 853 adds command value Dps_limitc of control phase shift amount Dps_limit output from control block 159 to the output value of multiplexer (MUX) 852 to calculate an arithmetic operation value.
  • MUX multiplexer
  • Comparator 854 compares a carrier wave having a frequency component of the fixed switching frequency with command value Dps_limitc and outputs comparison result OP1.
  • Comparator 855 compares a carrier wave having a frequency component of command value fs_ref of the fixed switching frequency with the output value of adder 853 and outputs comparison result OP2.
  • Logical AND circuit 856 performs logical AND operation of comparison result OP1 and comparison result OP2 to output second gate signal g22 for the second leg.
  • Logical NOT circuit 857 inverts the logical AND of comparison result OP1 and comparison result OP2 and outputs first gate signal g21 for the second leg.
  • At least one of frequency modulation control and phase shift control is used at the same time in addition to pulse frequency modulation control, whereby high power factor control and output control are achieved at the same time with one full-bridge inverter circuit.
  • FIG. 35 is a diagram illustrating a control method in a first modification to the first embodiment.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on the third control method, in a region in which target value M* of voltage conversion ratio M is larger than threshold TH1.
  • Control circuit 14 controls first leg 500 by pulse width modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control and phase shift modulation control.
  • Control circuit 14 allows third leg 300 to perform rectification control.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on the second control method, in a region in which target value M* of voltage conversion ratio M is equal to or smaller than threshold TH1 and is larger than threshold TH2.
  • Control circuit 14 controls first leg 500 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control, pulse frequency modulation control, and phase shift modulation.
  • Control circuit 14 allows third leg 300 to perform rectification control.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on the first control method, in a region in which target value M* of voltage conversion ratio M is equal to or smaller than threshold TH2.
  • Control circuit 14 controls first leg 500 by pulse width modulation control and pulse frequency control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 allows third leg 300 to perform rectification control.
  • FIG. 36 is a diagram illustrating a control method in a second modification to the first embodiment.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on the first control method, in a region in which target value M* of voltage conversion ratio M is larger than threshold TH.
  • Control circuit 14 controls first leg 500 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 allows third leg 300 to perform rectification control.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on the second control method, in a region in which target value M* of voltage conversion ratio M is equal to or smaller than threshold TH.
  • Control circuit 14 controls first leg 500 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control, pulse frequency modulation control, and phase shift modulation.
  • Control circuit 14 allows third leg 300 to perform rectification control.
  • FIG. 37 is a diagram illustrating a control method in a third modification to the first embodiment.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on the second control method, in a region in which target value M* of voltage conversion ratio M is larger than threshold TH.
  • Control circuit 14 controls first leg 500 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control, pulse frequency modulation control, and phase shift modulation.
  • Control circuit 14 allows third leg 300 to perform rectification control.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on the third control method, in a region in which target value M* of voltage conversion ratio M is equal to or smaller than threshold TH.
  • Control circuit 14 controls first leg 500 by pulse width modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control and phase shift modulation.
  • Control circuit 14 allows third leg 300 to perform rectification control.
  • the circuit configuration of the power conversion apparatus in the present embodiment is generally similar to the case shown in the first embodiment, and a detailed description of the configuration will not be repeated.
  • first semiconductor device 501 and second semiconductor device 502 that constitute first leg 500 and fifth semiconductor device 301 and sixth semiconductor device 302 that constitute third leg 300 are subjected to high power factor control, and third semiconductor device 601 and the fourth semiconductor device that constitute second leg 600 are subjected to output control.
  • FIG. 38 is a diagram illustrating a control method in the second embodiment.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on a fourth control method, in a region in which target value M* of voltage conversion ratio M is larger than threshold TH1.
  • Control circuit 14 controls first leg 500 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls third leg 300 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on a fifth control method, in a region in which target value M* of voltage conversion ratio M is equal to or smaller than threshold TH1 and is larger than threshold TH2.
  • Control circuit 14 controls first leg 500 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control, pulse frequency modulation control, and phase shift modulation.
  • Control circuit 14 controls third leg 300 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on a sixth control method, in a region in which target value M* of voltage conversion ratio M is equal to or smaller than threshold TH2.
  • Control circuit 14 controls first leg 500 by pulse width modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control and phase shift modulation control.
  • Control circuit 14 controls third leg 300 by pulse width modulation control.
  • FIG. 39 is a diagram illustrating an example of gate pulses for first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, fourth semiconductor device 602, fifth semiconductor device 301, and sixth semiconductor device 302 in the fourth control method.
  • the pulse of first semiconductor device 501 and the pulse of sixth semiconductor device 302 are synchronized with each other, and the pulse of second semiconductor device 502 and the pulse of fifth semiconductor device 301 are synchronized with each other. Further, the timing when first semiconductor device 501 turns on, the timing when sixth semiconductor device 302 turns on, and the timing when fourth semiconductor device 602 turns on are synchronized with each other, and the timing when second semiconductor device 502 turns off, the timing when fifth semiconductor device 301 turns off, and the timing when third semiconductor device 601 turns off are synchronized with each other.
  • the pulse width for first semiconductor device 501, the pulse width for third semiconductor device 601, and the pulse width for sixth semiconductor device 302 are equal, and the pulse width for second semiconductor device 502, the pulse width for fourth semiconductor device 602, and the pulse width for fifth semiconductor device 301 are equal.
  • Control circuit 14 controls first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, fourth semiconductor device 602, fifth semiconductor device 301, and sixth semiconductor device 302 such that switching frequency fs common to first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, fourth semiconductor device 602, fifth semiconductor device 301, and sixth semiconductor device 302 changes while those conditions are satisfied.
  • FIG. 40 is a diagram illustrating another example of gate pulses for first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, fourth semiconductor device 602, fifth semiconductor device 301, and sixth semiconductor device 302 in the fourth control method.
  • the pulse of first semiconductor device 501 and the pulse of sixth semiconductor device 302 are synchronized with each other, and the pulse of second semiconductor device 502 and the pulse of fifth semiconductor device 301 are synchronized with each other.
  • the center phase of the gate pulse for first semiconductor device 501, the center phase of the gate pulse for fourth semiconductor device 602, and the center phase of the gate pulse for sixth semiconductor device 302 are synchronized with each other, and the center phase of the gate pulse for second semiconductor device 502, the center phase of the gate pulse for third semiconductor device 601, and the center phase of the gate pulse for fifth semiconductor device 301 are synchronized with each other.
  • the pulse width for first semiconductor device 501, the pulse width for third semiconductor device 601, and the pulse width for sixth semiconductor device 302 are equal, and the pulse width for second semiconductor device 502, the pulse width for fourth semiconductor device 602, and the pulse width for fifth semiconductor device 301 are equal.
  • Control circuit 14 controls first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, fourth semiconductor device 602, fifth semiconductor device 301, and sixth semiconductor device 302 such that switching frequency fs common to first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, fourth semiconductor device 602, fifth semiconductor device 301, and sixth semiconductor device 302 changes while those conditions are satisfied.
  • the duration in which the diagonally-positioned first semiconductor device 501 and fourth semiconductor device 602 turn on simultaneously can be identical to the duration in which the diagonally-positioned second semiconductor device 502 and third semiconductor device 601 turn on simultaneously, thereby enabling stable power supply.
  • FIG. 41 is a diagram illustrating another example of gate pulses for first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, fourth semiconductor device 602, fifth semiconductor device 301, and sixth semiconductor device 302 in the sixth control method.
  • the pulse of first semiconductor device 501 and the pulse of sixth semiconductor device 302 are synchronized with each other, and the pulse of second semiconductor device 502 and the pulse of fifth semiconductor device 301 are synchronized with each other.
  • the initial state of phase shift control is defined as a state in which the timing when first semiconductor device 501 turns on, the timing when fourth semiconductor device 602 turns on, and the timing when sixth semiconductor device 302 turns on are synchronized with each other, and the timing when second semiconductor device 502 turns off, the timing when third semiconductor device 601 turns off, and the timing when fifth semiconductor device 301 turns on are synchronized with each other. Starting from this initial state, the pulse phase for third semiconductor device 601 and the pulse phase for fourth semiconductor device 602 are shifted.
  • the pulse width for first semiconductor device 501, the pulse width for third semiconductor device 601, and the pulse width for sixth semiconductor device 302 are equal, and the pulse width for second semiconductor device 502, the pulse width for fourth semiconductor device 602, and the pulse width for fifth semiconductor device 301 are equal.
  • Control circuit 14 controls first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, fourth semiconductor device 602, fifth semiconductor device 301, and sixth semiconductor device 302 such that those conditions are satisfied.
  • FIG. 42 is a diagram illustrating another example of gate pulses for first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, fourth semiconductor device 602, fifth semiconductor device 301, and sixth semiconductor device 302 in the sixth control method.
  • the pulse of first semiconductor device 501 and the pulse of sixth semiconductor device 302 are synchronized with each other, and the pulse of second semiconductor device 502 and the pulse of fifth semiconductor device 301 are synchronized with each other.
  • the initial state of phase shift control is defined as a state in which the timing when first semiconductor device 501 turns on, the timing when third semiconductor device 601 turns on, and the timing when sixth semiconductor device 302 turns on are synchronized with each other, and the timing when second semiconductor device 502 turns on, the timing when fourth semiconductor device 602 turns on, and the timing when fifth semiconductor device 301 turns on are synchronized with each other.
  • the pulse phase for third semiconductor device 601 and the pulse phase for fourth semiconductor device 602 are shifted.
  • the pulse width for first semiconductor device 501, the pulse width for third semiconductor device 601, and the pulse width for sixth semiconductor device 302 are equal, and the pulse width for second semiconductor device 502, the pulse width for fourth semiconductor device 602, and the pulse width for fifth semiconductor device 301 are equal.
  • Control circuit 14 controls first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, fourth semiconductor device 602, fifth semiconductor device 301, and sixth semiconductor device 302 such that those conditions are satisfied.
  • the duration in which the diagonally-positioned first semiconductor device 501 and fourth semiconductor device 602 turn on simultaneously can be identical to the duration in which the diagonally-positioned second semiconductor device 502 and third semiconductor device 601 turn on simultaneously, thereby enabling stable power supply.
  • FIG. 43 is a diagram illustrating an example of gate pulses for first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, fourth semiconductor device 602, fifth semiconductor device 301, and sixth semiconductor device 302 in the fifth control method.
  • the pulse of first semiconductor device 501 and the pulse of sixth semiconductor device 302 are synchronized with each other, and the pulse of second semiconductor device 502 and the pulse of fifth semiconductor device 301 are synchronized with each other.
  • the initial state of phase shift control is defined as a state in which the timing when first semiconductor device 501 turns on, the timing when fourth semiconductor device 602 turns on, and the timing when sixth semiconductor device 302 turns on are synchronized with each other, and the timing when second semiconductor device 502 turns off, the timing when third semiconductor device 601 turns off, and the timing when fifth semiconductor device 301 turns on are synchronized with each other.
  • the pulse phase for third semiconductor device 601 and the pulse phase for fourth semiconductor device 602 are shifted.
  • the pulse width for first semiconductor device 501, the pulse width for third semiconductor device 601, and the pulse width for sixth semiconductor device 302 are equal, and the pulse width for second semiconductor device 502, the pulse width for fourth semiconductor device 602, and the pulse width for fifth semiconductor device 301 are equal.
  • Control circuit 14 controls first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, fourth semiconductor device 602, fifth semiconductor device 301, and sixth semiconductor device 302 such that switching frequency fs common to first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, fourth semiconductor device 602, fifth semiconductor device 301, and sixth semiconductor device 302 changes while those conditions are satisfied.
  • FIG. 44 is a diagram illustrating another example of gate pulses for first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, fourth semiconductor device 602, fifth semiconductor device 301, and sixth semiconductor device 302 in the fifth control method.
  • the pulse of first semiconductor device 501 and the pulse of sixth semiconductor device 302 are synchronized with each other, and the pulse of second semiconductor device 502 and the pulse of fifth semiconductor device 301 are synchronized with each other.
  • the initial state of phase shift control is defined as a state in which the timing when first semiconductor device 501 turns on, the timing when third semiconductor device 601 turns on, and the timing when sixth semiconductor device 302 turns on are synchronized with each other, and the timing when second semiconductor device 502 turns on, the timing when fourth semiconductor device 602 turns on, and the timing when fifth semiconductor device 301 turns on are synchronized with each other.
  • the pulse phase for third semiconductor device 601 and the pulse phase for fourth semiconductor device 602 are shifted.
  • the pulse width for first semiconductor device 501, the pulse width for third semiconductor device 601, and the pulse width for sixth semiconductor device 302 are equal, and the pulse width for second semiconductor device 502, the pulse width for fourth semiconductor device 602, and the pulse width for fifth semiconductor device 301 are equal.
  • Control circuit 14 controls first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, fourth semiconductor device 602, fifth semiconductor device 301, and sixth semiconductor device 302 such that switching frequency fs common to first semiconductor device 501, second semiconductor device 502, third semiconductor device 601, fourth semiconductor device 602, fifth semiconductor device 301, and sixth semiconductor device 302 changes while those conditions are satisfied.
  • the duration in which the diagonally-positioned first semiconductor device 501 and fourth semiconductor device 602 turn on simultaneously can be identical to the duration in which the diagonally-positioned second semiconductor device 502 and third semiconductor device 601 turn on simultaneously, thereby enabling stable power supply.
  • FIG. 45 is a diagram illustrating a plurality of control blocks serving to perform the fourth control method.
  • a plurality of control blocks in the fourth control method differ from a plurality of control blocks serving to perform the first control method in the first embodiment in that a plurality of control blocks in the fourth control method include control block 178 instead of control block 167.
  • control block 178 When voltage vac of AC power supply 1 has positive polarity, control block 178 outputs first gate signal g11 for the first leg as gate signal g1 of first semiconductor device 501 and gate signal g6 of sixth semiconductor device 302 and outputs second gate signal g12 for the first leg as gate signal g2 of second semiconductor device 502 and gate signal g5 of fifth semiconductor device 301.
  • control block 167 When voltage vac of AC power supply 1 has negative polarity, control block 167 outputs second gate signal g12 for the first leg as gate signal g1 of first semiconductor device 501 and gate signal g6 of sixth semiconductor device 302 and outputs first gate signal g11 for the first leg as gate signal g2 of second semiconductor device 502 and gate signal g5 of fifth semiconductor device 301.
  • FIG. 46 is a diagram illustrating a plurality of control blocks serving to perform the sixth control method.
  • a plurality of control blocks in the sixth control method differ from a plurality of control blocks serving to perform the third control method in the first embodiment in that a plurality of control blocks in the sixth control method include control block 178 instead of control block 167.
  • Control block 178 is similar to control block 178 in the fourth control method and will not be further elaborated.
  • FIG. 47 is a diagram illustrating a plurality of control blocks serving to perform the fifth control method.
  • a plurality of control blocks in the fifth control method differ from a plurality of control blocks serving to perform the second control method in the first embodiment in that a plurality of control blocks in the fifth control method include control block 178 instead of control block 167.
  • Control block 178 is similar to control block 178 in the fourth control method and will not be further elaborated.
  • FIG. 48 is a diagram illustrating control block 178 generating gate signal g1 of first semiconductor device 501, gate signal g2 of second semiconductor device 502, gate signal g5 of fifth semiconductor device 301, and gate signal g6 of sixth semiconductor device 302.
  • Control block 178 includes a comparator 58, a multiplexer 59, and a multiplexer 61.
  • Comparator 58 compares voltage vac of AC power supply 1 detected by third voltage detector 677 with the ground voltage and outputs a signal representing the comparison result.
  • Multiplexer (MUX) 59 receives first gate signal g11 for the first leg and second gate signal g12 for the first leg. Multiplexer (MUX) 59 outputs one of the input gate signals as gate signal g1 of first semiconductor device 501 and gate signal g6 of sixth semiconductor device 302, in accordance with an output signal of comparator 58.
  • Multiplexer (MUX) 61 receives first gate signal g11 for the first leg and second gate signal g12 for the first leg. Multiplexer (MUX) 61 outputs one of the input gate signals as gate signal g2 of second semiconductor device 502 and gate signal g5 of fifth semiconductor device 301, in accordance with an output signal of comparator 58.
  • control block 178 The operation of control block 178 is described.
  • Multiplexer (MUX) 59 outputs first gate signal g11 for the first leg as gate signal g1 of first semiconductor device 501 and gate signal g6 of sixth semiconductor device 302.
  • Multiplexer (MUX) 61 outputs second gate signal g12 for the first leg as gate signal g2 of second semiconductor device 502 and gate signal g5 of fifth semiconductor device 301.
  • Multiplexer (MUX) 59 outputs second gate signal g12 for the first leg as gate signal g1 of first semiconductor device 501 and gate signal g6 of sixth semiconductor device 302.
  • Multiplexer (MUX) 61 outputs first gate signal g11 for the first leg as gate signal g2 of second semiconductor device 502 and gate signal g5 of fifth semiconductor device 301.
  • power loss is shared among first semiconductor device 501, second semiconductor device 502, fifth semiconductor device 301, and sixth semiconductor device 302 whereby operation is performed such that power loss does not locally occur.
  • high power factor control and output control in a wide range can be performed at the same time with a one-stage full-bridge inverter circuit, in the same manner as in the power conversion apparatus illustrated in the first embodiment.
  • FIG. 49 is a diagram illustrating a control method in a first modification to the second embodiment.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on the sixth control method, in a region in which target value M* of voltage conversion ratio M is larger than threshold TH1.
  • Control circuit 14 controls first leg 500 by pulse width modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control and phase shift modulation control.
  • Control circuit 14 controls third leg 300 by pulse width modulation control.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on the fifth control method, in a region in which target value M* of voltage conversion ratio M is equal to or smaller than threshold TH1 and is larger than threshold TH2.
  • Control circuit 14 controls first leg 500 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control, pulse frequency modulation control, and phase shift modulation.
  • Control circuit 14 controls third leg 300 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on the fourth control method, in a region in which target value M* of voltage conversion ratio M is equal to or smaller than threshold TH2.
  • Control circuit 14 controls first leg 500 by pulse width modulation control and pulse frequency control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls third leg 300 by pulse width modulation control and pulse frequency control.
  • FIG. 50 is a diagram illustrating a control method in a second modification to the second embodiment.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on the fourth control method, in a region in which target value M* of voltage conversion ratio M is larger than threshold TH.
  • Control circuit 14 controls first leg 500 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls third leg 300 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on the fifth control method, in a region in which target value M* of voltage conversion ratio M is equal to or smaller than threshold TH.
  • Control circuit 14 controls first leg 500 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control, pulse frequency modulation control, and phase shift modulation.
  • Control circuit 14 controls third leg 300 by pulse width modulation control and pulse frequency modulation control.
  • FIG. 51 is a diagram illustrating a control method in a third modification to the second embodiment.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on the fifth control method, in a region in which target value M* of voltage conversion ratio M is larger than threshold TH.
  • Control circuit 14 controls first leg 500 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control, pulse frequency modulation control, and phase shift modulation.
  • Control circuit 14 controls third leg 300 by pulse width modulation control and pulse frequency modulation control.
  • Control circuit 14 controls first leg 500, second leg 600, and third leg 300 based on the sixth control method, in a region in which target value M* of voltage conversion ratio M is equal to or smaller than threshold TH.
  • Control circuit 14 controls first leg 500 by pulse width modulation control.
  • Control circuit 14 controls second leg 600 by pulse width modulation control and phase shift modulation.
  • Control circuit 14 controls third leg 300 by pulse width modulation control.
  • FIG. 52 is a diagram illustrating a configuration of a power conversion apparatus 6000 according to a modification.
  • fifth semiconductor device 301 and sixth semiconductor device 302 are configured with diodes which are passive semiconductor.
  • AC power supply 1 One end of AC power supply 1 is connected to first AC end ND1 at which first semiconductor device 501 and second semiconductor device 502 are connected, through power factor-improving reactor 2.
  • First AC end ND1 is connected to series resonance reactor 7.
  • control logic that generates command value fs_ref of switching frequency is not limited to control block 160 in FIG. 26 , and any other control logic may be used.
  • FIG. 53 is a diagram illustrating control block 161 generating command value fs_ref of switching frequency.
  • Multiplier 44 multiplies output voltage Vout obtained from second voltage detector 676 by output current iout obtained from second current detector 679 to output output power PW1.
  • Subtracter 47b calculates differential power SP1 between a predetermined output power target value Pout_ref and output power PW1.
  • the calculated differential power SP1 is input as the feedback amount to PI controller 48.
  • PI controller 48 performs proportional integral control of differential power SP1 and outputs command value fs_ref of switching frequency.
  • FIG. 54 is a diagram illustrating control block 162 generating command value fs_ref of switching frequency.
  • Multiplier 44 multiplies effective voltage Vac of AC power supply 1 obtained from third voltage detector 677 by effective current lac of AC power supply 1 obtained from first current detector 678 to calculate power of AC power supply 1, that is, input power PW2.
  • Subtracter 47c calculates differential power SP2 between a predetermined input power target value Pac_ref and input power PW2.
  • the calculated differential power SP2 is input as the feedback amount to PI controller 48.
  • PI controller 48 performs proportional integral control of differential power SP2 and outputs command value fs_ref of switching frequency. It is noted that input power PW2 is active power that reflects the input power factor.
  • FIG. 55 is a diagram illustrating control block 163 generating command value fs_ref of switching frequency.
  • Subtracter 47d calculates differential current SI1 between a predetermined target current effective value Iac_ref of AC power supply 1 and effective current lac of AC power supply 1 obtained from first current detector 678.
  • the calculated differential current SI1 is input as the feedback amount to PI controller 48.
  • PI controller 48 performs proportional integral control of differential current SI1 and outputs command value fs_ref of switching frequency. Effective current of AC power supply 1 indicates input current.
  • FIG. 56 is a diagram illustrating control block 164 generating command value fs_ref of switching frequency.
  • Subtracter 47e calculates differential current SI2 between a predetermined output current target value iout_ref and output current iout obtained from second current detector 679.
  • the calculated differential current SI2 is input as the feedback amount to PI controller 48.
  • PI controller 48 performs proportional integral control of differential current SI2 and outputs command value fs_ref of switching frequency.
  • control logic that generates command value Dpsc of phase shift amount Dps is not limited to control block 158 in FIG. 24 , and any other control logic may be used.
  • FIG. 57 is a diagram illustrating control block 170 generating command value Dpsc of phase shift amount Dps.
  • Control block 170 includes a multiplier 844, a multiplier 845, a divider 846, a subtracter 847a, and a PI controller 848.
  • Multiplier 844 multiplies output voltage Vout obtained from second voltage detector 676 by output current iout obtained from second current detector 679 to output output power PW1.
  • Multiplier 845 multiplies effective voltage Vac of AC power supply 1 obtained from third voltage detector 677 by effective current lac of AC power supply 1 obtained from first current detector 678 to output input power PW2.
  • Divider 846 divides output power PW1 by input power PW2 to output conversion efficiency ⁇ .
  • Subtracter 847a performs subtraction between a predetermined target efficiency ⁇ ref and conversion efficiency ⁇ output from divider 46 to calculate differential efficiency S ⁇ as the feedback amount.
  • PI controller 848 performs proportional integral control of differential efficiency S ⁇ and outputs command value Dpsc of phase shift amount Dps. It is noted that input power PW2 is active power that reflects the input power factor.
  • FIG. 58 is a diagram illustrating control block 171 generating command value Dpsc of phase shift amount Dps.
  • Control block 171 includes a multiplier 44, a subtracter 47b, and a PI controller 40.
  • Multiplier 44 multiplies output voltage Vout obtained from second voltage detector 676 by output current iout obtained from second current detector 679 to output output power PW1.
  • Subtracter 47b performs subtraction between a predetermined target output power pout ref and output power PW1 output from multiplier 44 to calculate differential power SPwp as the feedback amount.
  • PI controller 40 performs proportional integral control of differential power SP and outputs command value Dpsc of phase shift amount Dps.
  • FIG. 59 is a diagram illustrating control block 172 generating command value Dpsc of phase shift amount Dps.
  • Control block 172 includes a multiplier 45, a subtracter 47c, and a PI controller 40.
  • Multiplier 45 multiplies voltage vac of AC power supply 1 obtained from third voltage detector 677 by current iac of AC power supply 1 obtained from first current detector 678 to output AC power PW2. It is noted that input power PW2 is active power that reflects the input power factor.
  • Subtracter 47c performs subtraction between a predetermined target AC power pac_ref and AC power PW2 output from multiplier 45 to calculate differential power SP as the feedback amount.
  • PI controller 40 performs proportional integral control of differential power SP and outputs command value Dpsc of phase shift amount Dps.
  • FIG. 60 is a diagram illustrating control block 173 generating command value Dpsc of phase shift amount Dps.
  • Control block 173 includes a subtracter 47d and a PI controller 40.
  • Subtracter 47d performs subtraction between a predetermined AC current iac_ref and current iac of AC power supply 1 obtained from first current detector 678 to calculate differential current SI as the feedback amount.
  • PI controller 40 performs proportional integral control of differential current SI and outputs command value Dpsc of phase shift amount Dps.
  • FIG. 61 is a diagram illustrating control block 174 generating command value Dpsc of phase shift amount Dps.
  • Control block 174 includes a subtracter 47e and a PI controller 40.
  • Subtracter 47e performs subtraction between a predetermined output current iout_ref and output current iout obtained from second current detector 679 to calculate differential current SI as the feedback amount.
  • PI controller 40 performs proportional integral control of differential current SI and outputs command value Dpsc of phase shift amount Dps.
  • Control block 160 generates command value fs_ref of switching frequency such that the efficiency computed from the detected voltage and current follows target efficiency
  • control block 170 generates command value Dpsc of phase shift amount Dps such that the efficiency computed from the detected voltage and current follows target efficiency.
  • the control method based on the efficiency is not limited thereto.
  • FIG. 62 is a diagram for explaining a method of selecting switching frequency fs and phase shift amount Dps.
  • a plurality of patterns of combination of switching frequency fs and phase shift amount Dps that provides a desired voltage conversion ratio are stored, and the operation conditions may be converged to those of the combination that provides the largest conversion efficiency among them.
  • the combinations of switching frequency and phase shift amount Dps may be successively stored, or as shown in FIG. 62 , the combination may be stored for each variation range ⁇ fs of switching frequency.
  • the combination that provides the largest output power, rather than the conversion efficiency, may be stored, or the combination that provides the largest input power may be stored, or the combination that provides the largest input current may be stored, or the combination that provides the largest output current may be stored.
  • Secondary-side rectifying circuit 11 is not limited to the configuration shown in FIG. 1 .
  • FIG. 63 is a diagram illustrating a modification of secondary-side rectifying circuit 11.
  • a center-tap diode rectification system may be employed in which transformer 9 is of a center-tap type and a diode is used as a semiconductor device.
  • FIG. 64 is a diagram illustrating another modification of secondary-side rectifying circuit 11. As shown in FIG. 64 , a voltage doubler diode rectification system may be employed in which one of two legs is configured with two diodes and the other is configured with two capacitors.
  • FIG. 65 is a diagram illustrating another modification of secondary-side rectifying circuit 11. As shown in FIG. 65 , a full-bridge synchronous rectification system may be employed in which four active semiconductors constitute a full bridge.
  • FIG. 66 is a diagram illustrating another modification of secondary-side rectifying circuit 11.
  • a center-tap synchronous rectification system may be employed in which transformer 9 is of a center-tap type and an active semiconductor is used as a semiconductor device.
  • FIG. 67 is a diagram illustrating another modification of secondary-side rectifying circuit 11. As shown in FIG. 67 , a voltage doubler synchronous rectification system may be employed in which one of two legs is configured with two active semiconductors and the other is configured with two capacitors.
  • FIG. 68 is a diagram illustrating a modification of output smoothing circuit 1200.
  • a capacitor input system may be employed in which output smoothing circuit 1200 is configured to smooth only using a capacitor C.
  • FIG. 69 is a diagram illustrating another modification of output smoothing circuit 1200.
  • a smoothing system may be employed in which output smoothing circuit 1200 is configured such that a plurality of capacitors C1, C2, C3 and a plurality of inductors L1, L2 are alternately connected.
  • the number of capacitors and inductors is not limited thereto.
  • the second voltage detector detecting output voltage Vout is not limited to the method illustrated in FIG. 1 that detects the voltage of second output smoothing capacitor 1203, and may detect the voltage of first output smoothing capacitor 1201 or may detect the voltage of DC load 13.
  • output smoothing circuit 1200 has the configuration shown in FIG. 68 or FIG. 69 , one of a method of detecting any one capacitor voltage or a method of detecting the voltage of DC load 13 may be selected.
  • the second current detector detecting output current iout may be arranged at a section connected in series with output smoothing reactor 1202, rather than the section connected in series with DC load 13 as illustrated in FIG. 1 , and may detect current of output smoothing reactor 1202.
  • control circuit 14 may be configured with software using a memory 746 storing a program and a processor 745 processing the program.
  • Series resonance reactor 7 may be substituted with leakage inductance of transformer 9, and parallel resonance reactor 8 may be substituted with magnetizing inductance of transformer 9.
  • series resonance reactor 7, parallel resonance reactor 8, and series resonance capacitor 10 are disposed on the primary side of transformer 9. However, they may be disposed on the secondary side of transformer 9 or may be disposed so as to be distributed on the primary side and the secondary side of transformer 9.
  • series resonance reactor 7 and series resonance capacitor 10 are connected to one of the primary-side terminals of transformer 9. However, they may be disposed so as to be distributed between both terminals or may be disposed so as to be distributed between both terminals on the secondary side of transformer 9.
  • Control block 169 may be used instead of control block 160.
  • a fixed phase shift amount set for each operation condition may be uniquely output, rather than obtaining command value Dpsc of phase shift amount Dps by arithmetic operation. In this case, output control may be performed using the switching frequency as the feedback amount.
  • a fixed switching frequency set for each operation condition may be uniquely output, rather than obtaining command value fs_ref of switching frequency by arithmetic operation. In this case, output control may be performed using the phase shift amount as the feedback amount.
  • the control may be as follow in the CP control mode.
  • First leg 500 performs high power factor control by adjusting the ON period and the switching frequency so as to follow the target sinusoidal current in phase with the sinusoidal voltage obtained from third voltage detector 677, based on the value obtained from first current detector 678.
  • Second leg 600 performs output control by adjusting the ON period and the switching frequency so as to follow the target DC voltage, based on the value obtained from first voltage detector 675.
  • the control may be as follow.
  • First leg 500 performs high power factor control by adjusting the ON period and the switching frequency such that DC voltage of DC capacitor 4 follows the target DC voltage, based on the values obtained from first voltage detector 675, third voltage detector 677, and first current detector 678.
  • Second leg 600 performs output control by adjusting the ON period and the frequency so as to follow the target DC current, based on the value obtained from second current detector 679.
  • the control may be as follow in the CP control mode.
  • First leg 500 and the third leg perform high power factor control by adjusting the ON period and the switching frequency so as to follow the target sinusoidal current in phase with the sinusoidal voltage obtained from third voltage detector 677, based on the value obtained from first current detector 678.
  • Second leg 600 performs output control by adjusting the ON period and the switching frequency so as to follow the target DC voltage, based on the value obtained from first voltage detector 675.
  • the control may be as follow.
  • First leg 500 and the third leg perform high power factor control by adjusting the ON period and the switching frequency such that DC voltage of DC capacitor 4 follows the target DC voltage, based on the values obtained from first voltage detector 675, third voltage detector 677, and first current detector 678.
  • Second leg 600 performs output control by adjusting the ON period and the frequency so as to follow the target DC current, based on the value obtained from second current detector 679.
  • the control may be as follow in the CP control mode.
  • First leg 500 performs high power factor control by adjusting the ON period and the switching frequency so as to follow the target sinusoidal current in phase with the sinusoidal voltage obtained from third voltage detector 677, based on the value obtained from first current detector 678.
  • Second leg 600 performs output control by adjusting the ON period, the phase shift amount, and the switching frequency so as to follow the target DC voltage, based on the value obtained from first voltage detector 675.
  • the control may be as follow.
  • First leg 500 performs high power factor control by adjusting the ON period and the switching frequency such that DC voltage of DC capacitor 4 follows the target DC voltage, based on the values obtained from first voltage detector 675, third voltage detector 677, and first current detector 678.
  • Second leg 600 performs output control by adjusting the ON period, the frequency, and the phase shift amount so as to follow the target DC current, based on the value obtained from second current detector 679.
  • the control may be as follow in the CP control mode.
  • First leg 500 and the third leg perform high power factor control by adjusting the ON period and the switching frequency so as to follow the target sinusoidal current in phase with the sinusoidal voltage obtained from third voltage detector 677, based on the value obtained from first current detector 678.
  • Second leg 600 performs output control by adjusting the ON period, the phase shift amount, and the switching frequency so as to follow the target DC voltage, based on the value obtained from first voltage detector 675.
  • the control may be as follow.
  • First leg 500 and the third leg perform high power factor control by adjusting the ON period and the switching frequency such that DC voltage of DC capacitor 4 follows the target DC voltage, based on the values obtained from first voltage detector 675, third voltage detector 677, and first current detector 678.
  • Second leg 600 performs output control by adjusting the ON period, the frequency, and the phase shift amount so as to follow the target DC current, based on the value obtained from second current detector 679.
  • first leg 500 performs high power factor control by adjusting the ON period so as to follow the target sinusoidal current in phase with sinusoidal voltage obtained from third voltage detector 677, based on the value obtained from first current detector 678.
  • Second leg 600 performs output control by adjusting the ON period and the phase shift amount so as to follow the target DC voltage, based on the value obtained from first voltage detector 675.
  • first leg 500 performs high power factor control by adjusting the ON period such that DC voltage of DC capacitor 4 follows the target DC voltage, based on the values obtained from first voltage detector 675, third voltage detector 677, and first current detector 678.
  • Second leg 600 performs output control by adjusting the ON period and the phase shift amount so as to follow the target DC current, based on the value obtained from second current detector 679.
  • first leg 500 and the third leg perform high power factor control by adjusting the ON period so as to follow the target sinusoidal current in phase with the sinusoidal voltage obtained from third voltage detector 677, based on the value obtained from first current detector 678.
  • Second leg 600 performs output control by adjusting the ON period and the phase shift amount so as to follow the target DC voltage, based on the value obtained from first voltage detector 675.
  • first leg 500 and the third leg perform high power factor control by adjusting the ON period such that DC voltage of DC capacitor 4 follows the target DC voltage, based on the values obtained from first voltage detector 675, third voltage detector 677, and first current detector 678.
  • Second leg 600 performs output control by adjusting the ON period and the phase shift amount so as to follow the target DC current, based on the value obtained from second current detector 679.
EP17936427.8A 2017-12-25 2017-12-25 Dispositif de conversion de puissance Active EP3734828B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2017/046449 WO2019130395A1 (fr) 2017-12-25 2017-12-25 Dispositif de conversion de puissance

Publications (3)

Publication Number Publication Date
EP3734828A1 true EP3734828A1 (fr) 2020-11-04
EP3734828A4 EP3734828A4 (fr) 2020-12-30
EP3734828B1 EP3734828B1 (fr) 2023-06-28

Family

ID=63518822

Family Applications (1)

Application Number Title Priority Date Filing Date
EP17936427.8A Active EP3734828B1 (fr) 2017-12-25 2017-12-25 Dispositif de conversion de puissance

Country Status (5)

Country Link
US (1) US11056979B2 (fr)
EP (1) EP3734828B1 (fr)
JP (1) JP6388745B1 (fr)
CN (1) CN111542999B (fr)
WO (1) WO2019130395A1 (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111587526A (zh) * 2018-12-17 2020-08-25 富士电机株式会社 Ｄｃ－ｄｃ转换器装置
CN110323783B (zh) * 2019-07-24 2021-01-08 阳光电源股份有限公司 光伏并网逆变器及其控制方法
JP6747569B1 (ja) * 2019-11-21 2020-08-26 富士電機株式会社 電力変換装置、制御方法、および制御プログラム
JP2021197803A (ja) * 2020-06-12 2021-12-27 キヤノン株式会社 整流回路および無線電力伝送装置
CN113302828B (zh) * 2020-10-16 2023-11-17 深圳欣锐科技股份有限公司 电压转换电路与电子装置
KR102472398B1 (ko) * 2021-01-12 2022-11-29 인천대학교 산학협력단 역률 보상부와 컨버터를 통합한 구조를 갖는 배터리 충전 장치
JP2022108333A (ja) * 2021-01-13 2022-07-26 富士電機株式会社 電力変換装置、電力変換装置の制御装置、および、電力変換制御方法
US11799382B2 (en) * 2021-03-03 2023-10-24 Semiconductor Components Industries, Llc Resonant converter with dual-mode control
WO2023243321A1 (fr) * 2022-06-17 2023-12-21 パナソニックＩｐマネジメント株式会社 Dispositif convertisseur
FR3140491A1 (fr) * 2022-09-30 2024-04-05 Valeo Systemes De Controle Moteur Circuit d’alimentation électrique d’une unité de stockage d’énergie électrique de véhicule

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3431985B2 (ja) 1994-03-17 2003-07-28 株式会社日立メディコ インバータ式ｘ線高電圧装置
JP3407051B2 (ja) * 1997-04-16 2003-05-19 株式会社日立製作所 モータ制御装置
US7956592B2 (en) * 2008-06-13 2011-06-07 The Regents Of The University Of Colorado Monitoring and control of power converters
JP5359637B2 (ja) * 2009-07-17 2013-12-04 富士電機株式会社 電力変換装置
CN101867296B (zh) * 2010-06-01 2012-12-05 国电南瑞科技股份有限公司 串联谐振直流/直流变换器
CN102299649B (zh) * 2010-06-24 2015-11-25 盛飞 电源变换器
JP5678344B2 (ja) * 2010-07-13 2015-03-04 ミネベア株式会社 スイッチング電源装置の制御方法
US8705252B2 (en) * 2011-04-15 2014-04-22 Power Integrations, Inc. Off line resonant converter with merged line rectification and power factor correction
WO2012144249A1 (fr) * 2011-04-18 2012-10-26 三菱電機株式会社 Dispositif de conversion de puissance et dispositif d'alimentation électrique à bord de véhicule doté de celui-ci
JP2012249415A (ja) 2011-05-27 2012-12-13 Minebea Co Ltd スイッチング電源装置の制御方法
EP2568589B1 (fr) * 2011-09-08 2013-11-13 ABB Technology AG Convertisseur multiniveaux ayant un redresseur actif et un convertisseur résonant courant continu-courant et procédé de commande pour son fonctionnement
US8687388B2 (en) 2012-01-31 2014-04-01 Delta Electronics, Inc. Three-phase soft-switched PFC rectifiers
US9379617B2 (en) 2012-02-03 2016-06-28 Fuji Electric Co., Ltd. Resonant DC-DC converter control device
JP5909402B2 (ja) * 2012-04-11 2016-04-26 日立アプライアンス株式会社 電力変換装置およびそれを用いた誘導加熱装置
US20150103562A1 (en) * 2013-10-16 2015-04-16 Acbel Polytech Inc. Switching Power Supply with a Resonant Converter and Method Controlling the Same
FR3025949B1 (fr) * 2014-09-11 2016-08-26 Renault Sa Procede de commande d'un chargeur de batterie a convertisseur courant-continu - courant continu a resonance serie
CA2902428C (fr) * 2014-10-31 2024-01-09 Majid Pahlevaninezhad Optimiseur de puissance sans capteur de courant destine a des micro-onduleurs photovoltaiques
CN104734520A (zh) * 2015-03-23 2015-06-24 深圳市皓文电子有限公司 一种dc/dc转换器
CN106787760B (zh) * 2016-12-30 2018-05-08 珠海英搏尔电气股份有限公司 全桥谐振直流/直流变换器及其控制方法
CN109861356B (zh) * 2018-05-09 2023-03-24 台达电子工业股份有限公司 冲击电流抑制模块、车载双向充电机及控制方法

Also Published As

Publication number Publication date
JP6388745B1 (ja) 2018-09-12
WO2019130395A1 (fr) 2019-07-04
US11056979B2 (en) 2021-07-06
US20200287468A1 (en) 2020-09-10
CN111542999A (zh) 2020-08-14
CN111542999B (zh) 2023-07-11
EP3734828A4 (fr) 2020-12-30
JPWO2019130395A1 (ja) 2019-12-26
EP3734828B1 (fr) 2023-06-28

Similar Documents

Publication Publication Date Title
EP3734828B1 (fr) Dispositif de conversion de puissance
US10476397B2 (en) Interleaved resonant converter
US6310785B1 (en) Zero voltage switching DC-DC converter
US10044278B2 (en) Power conversion device
US11411502B2 (en) Single-stage isolated DC-DC converters
US10847999B2 (en) Wireless power receiver, wireless power transmission system using the same, and rectifier
US9401655B2 (en) Power conversion apparatus with inverter circuit and series converter circuit having power factor control
US10454364B2 (en) Power convertor
US11296607B2 (en) DC-DC converter
US10141851B2 (en) Resonant DC to DC power converter
EP3442089A1 (fr) Circuit de contrôle pour ponts duals actifs à utiliser avec des tensions de réseau déséquilibrées
US9929668B1 (en) Powder conditioner with reduced capacitor voltage ripples
CN109842182B (zh) 供电系统
Rehlaender et al. Dual interleaved 3.6 kW LLC converter operating in half-bridge, full-bridge and phase-shift mode as a single-stage architecture of an automotive on-board DC-DC converter
US10848072B2 (en) Power supply control device, power conversion system, and power supply control method
KR20180091543A (ko) 역률 개선 컨버터
JP6277087B2 (ja) 電力変換装置
JP6313236B2 (ja) 電源装置およびａｃアダプタ
Sharifuddin et al. Implementation of Three-Phase Bidirectional Isolated DC-DC Converter with Improved Light-Load Efficiency
Golbon et al. A novel ac-dc single-stage converter for low power applications
Jacoboski et al. Zero voltage switching dual neutral point clamped dc-dc converter
KR20220072173A (ko) 단일전력단 3 레벨 컨버터
CN117581469A (zh) 功率转换器装置

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20200618

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

A4 Supplementary search report drawn up and despatched

Effective date: 20201130

RIC1 Information provided on ipc code assigned before grant

Ipc: H02M 1/42 20070101ALI20201124BHEP

Ipc: H02M 3/335 20060101ALI20201124BHEP

Ipc: H02M 7/48 20070101AFI20201124BHEP

Ipc: H02M 1/00 20060101ALI20201124BHEP

Ipc: H02M 7/217 20060101ALI20201124BHEP

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)
REG Reference to a national code

Ref country code: DE

Ref legal event code: R079

Ref document number: 602017070839

Country of ref document: DE

Free format text: PREVIOUS MAIN CLASS: H02M0007480000

Ipc: H02M0003335000

Ref country code: DE

Ref legal event code: R079

Ipc: H02M0003335000

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

RIC1 Information provided on ipc code assigned before grant

Ipc: H02M 3/00 20060101ALI20221209BHEP

Ipc: H02M 7/217 20060101ALI20221209BHEP

Ipc: H02M 1/42 20070101ALI20221209BHEP

Ipc: H02M 3/335 20060101AFI20221209BHEP

INTG Intention to grant announced

Effective date: 20230112

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230601

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 1583628

Country of ref document: AT

Kind code of ref document: T

Effective date: 20230715

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602017070839

Country of ref document: DE

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG9D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230628

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230928

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20230628

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 1583628

Country of ref document: AT

Kind code of ref document: T

Effective date: 20230628

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230628

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230628

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230628

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230628

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230628

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230929

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230628

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230628

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230628

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231028

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230628

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230628

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230628

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231030

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231028

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230628

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230628

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230628

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230628

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20231108

Year of fee payment: 7

Ref country code: DE

Payment date: 20231031

Year of fee payment: 7

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230628