EP3403267A1 - Bauelementtraeger mit esd schutzfunktion und verfahren zur herstellung - Google Patents
Bauelementtraeger mit esd schutzfunktion und verfahren zur herstellungInfo
- Publication number
- EP3403267A1 EP3403267A1 EP17700228.4A EP17700228A EP3403267A1 EP 3403267 A1 EP3403267 A1 EP 3403267A1 EP 17700228 A EP17700228 A EP 17700228A EP 3403267 A1 EP3403267 A1 EP 3403267A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- pair
- electrodes
- electrode
- varistor
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
- H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
- H01C7/1006—Thick film varistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C1/00—Details
- H01C1/14—Terminals or tapping points specially adapted for resistors; Arrangements of terminals or tapping points on resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C1/00—Details
- H01C1/14—Terminals or tapping points specially adapted for resistors; Arrangements of terminals or tapping points on resistors
- H01C1/144—Terminals or tapping points specially adapted for resistors; Arrangements of terminals or tapping points on resistors the terminals or tapping points being welded or soldered
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
- H01C17/065—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thick film techniques, e.g. serigraphy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/28—Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals
- H01C17/281—Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals by thick film techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
- H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
- H01C7/102—Varistor boundary, e.g. surface layers
Definitions
- the application relates to a component carrier with built-in ESD protection function, with electrical components
- Varistors can be used to protect sensitive equipment, components and networks against ESD (Electro Static Discharge). These are non-linear components whose resistance exceeds one
- Varistors are therefore suitable for safely dissipating overvoltage pulses.
- Varistors made of a zinc oxide ceramic with grain structure are produced.
- Discrete devices with varistor function or generally with ESD protection function are soldered directly onto a ceramic substrate, a leadframe, a circuit board or a circuit board and electrically connected to the device to be protected. It is also possible to integrate such protective elements in a laminate during its production. Further, it is possible to place the protective element in a recess of the substrate, the carrier plate or the laminate so that it is adjacent to other electrically conductive structures which are provided for connection to further components. Although this leads to a low
- Object of the present invention is the integration of a protective function or a protective element in one
- Another sub-task is to specify a basic body with protective function and improved thermal conductivity. This object is achieved by a component carrier with the
- the component carrier has a ceramic base body which has electrical connection surfaces on a first surface and a first electrode pair on a second surface. Electrical connection surfaces and first
- Electrode pair are electrically connected via vias.
- a varistor layer is applied over the first pair of electrodes.
- a second electrode pair is applied over the varistor layer and electrically connected in parallel with the first electrode pair.
- First and second electrode pair together with the varistor layer arranged therebetween form a varistor and can thus, in the case of one at the connection surfaces
- Electrode pair electrically connected component is not damaged.
- the varistor layer lies flat on the base body, can use its first electrode pair as a varistor electrode and therefore requires only little additional volume.
- Component carrier therefore has a relatively small volume.
- the varistor layer is laterally dimensioned so that it is circumferentially spaced from the edges of the component carrier. This has the advantage that no side edge of
- Varistor layer terminates on a side surface of the component carrier. As a result, the varistor layer is protected against mechanical and other influences after assembly of the component.
- Such a lateral structuring of the varistor layer has in particular in the structuring of the base body, or in the singling of individual component carriers along
- Dividing lines have the advantage that the dividing lines come to rest outside the varistor layer, so that the latter does not have to be severed during separation and therefore can not be damaged.
- the second electrode pair preferably comprises a solderable material or is provided with a solderable surface layer Mistake. Then, an electrical component can be soldered directly onto the varistor layer or its second "upper" electrode pair
- the varistor between the component and body is mechanically protected.
- a protective layer or a passivation is therefore either not necessary for the varistor or can be produced in a simple and cost-effective design.
- the component carrier is suitable for components that generate waste heat during operation. This can be removed from the component via the component carrier.
- the base body comprises aluminum nitride. This is characterized by a particularly good thermal conductivity. This advantage can compensate for the disadvantage of higher material price in heat-generating components.
- other ceramic materials are also suitable for the basic body, for example aluminum oxide, silicon carbide, boron nitride or others.
- the component carrier may be provided with thermal vias, which improve the heat transfer through the body through.
- the thermal vias are preferably connected to a heat sink, which may for example be provided on a circuit board, to which the component carrier is bonded.
- At least the second comprises
- Electrode pair copper-containing and silver-containing electrode pastes can be printed with additional finish to give a solderable surface. But there are also other electrode pastes known, can be soldered on directly without additional finish.
- At least one inner electrode is arranged, which is embedded in the varistor layer in an electrically floating manner or is electrically connected to one electrode of the first pair of electrodes. This has in the production of the
- a passivation layer is above the varistor layer and the second electrode pair arranged that the varistor layer is enclosed on all sides and completely between the base body, second electrode pair and passivation layer and from the second
- connection contacts remain free and uncovered.
- the passivation layer can be applied and patterned after the application of the varistor layer.
- the second pair of electrodes can then be produced in surface regions which are free of the passivation layer. It is also possible, the passivation layer after the
- connection contacts for the assembly of the device can be generated.
- Component carrier comprises the steps:
- Pair of electrodes of a green sheet which can be converted into a varistor layer by sintering
- varistor h imprinting a second pair of electrodes on the
- Varistor layer and the exposed portion of the first pair of electrodes such that first and second
- Electrode pair are electrically connected and an overlap of an electrode of the first pair of electrodes with the opposite electrode of the second
- Electrode pair defined with an intermediate active varistor region The method steps a) to d) can be substantially similar to corresponding known methods without modification.
- step e) the varistor layer is then used as a green sheet. This can be done before or after the baking of the printed first pair of electrodes.
- Electrode paste can comprise glass components for better adhesion and at the same time serve as adhesion promoter for the varistor layer.
- the green sheet for the varistor layer can be laminated over the entire surface of the base body. It can the
- the body may be a ceramic wafer on which a large number of individual carriers can be generated in parallel and processed before the wafer is then separated into the individual carriers.
- the varistor is designed with an inner electrode, it can be applied to the green sheet before it is laminated. However, it is then necessary a mutual alignment between the varistor layer with the inner electrode and the base body with the first electrode pair. This eliminates the subsequent generation of the inner electrode after the lamination. It is possible but not necessary to apply single or more layers after lamination or
- the laminated green sheet is so
- the struc ⁇ turing can be quickly and structure accurately performed with a laser.
- the metallizations of the component carrier as ⁇ connection surfaces, first and second pair of electrodes may be prepared by
- Metal-containing paste can be provided with a refining coating, a so-called finish and thus with a solderable surface.
- a finish may include Ni, Au, Pt, Pd or Sn.
- the inner electrode can be printed as well as the other Metalli ⁇ stechniken. This can be done on an already laminated green foil with varistor material or on the separate not yet laminated green sheet done. A green foil provided with an inner electrode can also be printed over the whole area on a large-area base body and patterned later.
- the inner electrode is aligned at the first pair of electrodes. Alignment is less critical if the inner electrode is electrically floating. If the at least one inner electrode with a
- the alignment of the inner electrode on the first electrode pair must be done with a lower tolerance.
- the structuring of the green sheet is to be carried out in such a way that the inner electrodes to be interconnected with the same polarity are cut on one structural edge of the green sheet or green sheet stack and can later be connected to the second pair of electrodes.
- a passivation layer can be applied and patterned so that in the first case only the surface region provided for the second electrode pair remains free of the passivation layer.
- the printed second electrode pair remains free of the passivation layer only in such an area, in which subsequently solderable connection contacts are produced by amplifying the second electrode pair.
- the passivation layer may be a glass, ceramics, other dielectric oxides, nitrides, carbides, or a polymer, e.g. Polyimide include.
- a polymer may be selected to require further processing steps such as e.g. Electroplating, the burning of printed metallizations or
- the passivation layer is usually to remain on the component carrier
- solderable contacts are galvanic
- the singulation can be done in a simple manner e.g. done by sawing.
- FIG. 1 shows a simple embodiment of a
- FIGS. 2A to 2H show various embodiments
- FIGS. 3A to 3F show a second cross-section through different process stages
- FIGS. 4A to 4G show various process steps on the basis of schematic cross sections during the production of a component carrier with a multilayer varistor.
- Figures 5A and 5B show the manufacture of a film stack as may be used in the manufacture of a multilayer varistor.
- FIGS. 6A to 6E show various embodiments of a component carrier according to the invention after being fitted with a component.
- FIG. 1 shows, in a schematic cross section, a simple embodiment of a component carrier BT according to FIG.
- a ceramic base GK is provided on a first surface Ol with pads AF.
- a first electrode pair EP1 is applied on the opposite second surface 02.
- Each pad AF is associated with an electrode of the first pair of electrodes EP1 and with this through a via DK through the
- a varistor layer VS is applied over both electrodes of the first pair of electrodes EP1. Above the varistor layer VS, a second electrode pair EP2 is attached, and so on
- Electrode pair is in contact. Accordingly, the second is Electrode of the second pair of electrodes EP2 with the second electrode of the first pair of electrodes EP1 in contact.
- An electrode of the first electrode pair overlaps with an electrode of the second pair of electrodes EP2 so that with the intervening varistor VS in
- Zinc oxide grains ZK are arranged in dense packing in the varistor layer VS.
- Electrode pair EP1, EP2 applied voltage exceeds the breakdown voltage, forms between individual
- the varistor voltage is the voltage drop across the varistor at impressed current of 1 mA. she has no
- the main body GK is preferably formed of aluminum oxide or for better heat conduction of aluminum nitride. Other ceramic materials are theoretically suitable, but expensive. Connection surfaces and first
- Electrode pairs comprise a baked conductive paste, for example based on silver.
- the second electrode pair EP2 is preferably made of a conductive baked Paste formed and either already for themselves already solderable or provided with a solderable surface.
- a copper-containing paste can be used, which is already a solubilizing by itself additives
- FIGS. 2A to 2H show a simple production method for a component carrier according to FIG. 1.
- FIG. 2A shows a main body GK, which is used for
- FIG. 2B shows the main body after the manufacture of
- Pads AF on the first surface and of a first pair of electrodes EP1 on the second surface may be in the form of a conductive paste, but may also be baked already.
- a green film of a varistor layer VS is laminated onto the second surface above the first electrode pair EP1. This takes place over the entire surface over the entire surface of the main body GK.
- the whole-area varistor layer VS is patterned with the aid of a structuring tool ST.
- the varistor layer VS is in a circumferential
- the varistor foil VS is in the edge region of the first
- the electrodes of the first pair of electrodes are each strip-shaped, as is the exposed area.
- FIG. 2E shows the arrangement after the structuring of the varistor layer VS.
- a second pair of electrodes EP2 is then applied to the laminated green sheet of the varistor layer VS such that one electrode thereof in each case contacts an electrode of the first pair of electrodes EP1 in the exposed area.
- the second electrode pair EP2 is preferably printed, wherein a conductive paste based on silver or copper can be used. After printing, the second pair of electrodes EP2 can be baked, wherein
- Figure 2F shows the arrangement after the completion of the second pair of electrodes.
- solderable terminals AK is now over the entire surface of a passivation layer PS up ⁇ placed and structured to a mask for
- connection contacts AK forms.
- a passivation layer PS a glass-containing layer or another resist mask, for example a polymer, can be used.
- a glassy passivation layer can be used as a passivation layer PS.
- a polymer layer like a photoresist, can be laminated on as a film or spin-coated in liquid form and patterned photolithographically.
- Figure 2G shows the arrangement on this
- Electrode pair EP2 where it is exempt from the passivation layer PS and uncovered, with a good conductive
- Metal reinforced for example with copper.
- solderable surface can then be a
- connection surfaces AF on the first surface Ol can also be provided with a solderable coating.
- FIG. 2H shows the
- FIGS 3A to 3F show with reference to schematic
- the procedure starts with a
- Electrode provided basic body GK, for example, as shown in Figure 2B. On this body is now a
- Green film for the varistor layer VS laminated In principle, two variants are possible.
- a first partial layer of the varistor layer can be laminated on and then the inner electrode IE can be printed. Subsequently, over the entire surface, a second green sheet of the varistor layer VS is laminated so that the inner electrode is completely embedded between the two varistor layers.
- the inner electrode IE is printed on a first partial foil of the varistor layer VS and then a second partial foil of the varistor Layer laminated. The whole is done separately from the base ⁇ body GK, so that a prelaminate is formed, which is then laminated to the ceramic body GK.
- FIG. 3A shows the arrangement with the varistor layer, in which the inner electrode IE is embedded in such a way that they are both connected to the electrodes of the first and second electrode pair
- this varistor layer VS is also structured, and the edge region as well as that for connections
- the inner electrode remains
- a laser can be used for structuring.
- the varistor layer VS is sintered, wherein, as during firing, each ceramic begins to shrink in volume. Since the varistor layer is stretched by the base body, but this leads at most to a small, usually no lateral fading, but it leads to a reduction in the
- FIG. 3C shows the
- a passivation layer is then deposited and patterned, or structured or already vorstruk ⁇ tured applied, for example by printing.
- the connection areas provided for connecting the first pair of electrodes remain uncovered by the passivation layer PS and parts of the varistor layer VS, on which later the second electrode pair is generated in a structured manner.
- FIG. 3D shows the arrangement with the structured passivation layer PS.
- the second electrode pair EP2 is now applied, for example by printing. Subsequently, the second electrode pair is baked.
- Figure 3E shows the arrangement on this
- a solderable surface of a finishing layer may be applied to the second electrode pair EP2, for example, by electroplating a surface layer of OS, such as a gold, palladium or platinum ⁇ layer, or one of the above-mentioned other coatings.
- a surface layer of OS such as a gold, palladium or platinum ⁇ layer, or one of the above-mentioned other coatings.
- Figure 3F shows the arrangement on this
- the finished component carrier BT can now be equipped with an electrical component, which can be soldered onto the first electrode pair or on the surface layer OS. Alternatively, the component can also be mounted on the connection surfaces AF on the opposite first upper side Ol.
- FIGS. 4A to 4G show, with reference to schematic cross sections during various process stages, the production of a component carrier with a multilayer varistor structure.
- FIG. 4A shows a main body GK, which is coated on both sides with electrodes, namely with connection surfaces AF on the underside or first surface and a first electrode pair EP1 on the second surface 02nd On the second surface via the first electrode pair EP1 now a film stack FS is laminated.
- the method can be carried out as already described in the previous embodiment according to the figure 3.
- the film stack FS can be removed from the main body by
- Overlaminating green sheets printed with electrode material may be produced so that the inner electrodes IE overlap one another and differently polarized electrodes can be contacted at opposite edge regions. There, too, the individual layers of the inner electrodes do not overlap with another inner electrode of opposite polarity.
- the laminated film stack FS is then as a whole on the surface of the
- Figure 4B shows the arrangement on this
- FIG. 2D shows how, with the aid of a structuring tool ST, the film stack FS is structured such that a
- connection areas of the first pair of electrodes are exposed. At the same time, in each case a corresponding one in the two opposite edge regions
- FIG. 4D shows the arrangement after structuring and baking of the film stack, wherein a varistor layer VS having here two internal electrodes IE is obtained.
- the left edge of the lower inner electrode IE1 is for connection exposed with the left electrode of the first pair of electrodes.
- the upper inner electrode IE2 for connection to the right electrode of the first pair of electrodes is exposed.
- the second pair of electrodes EP2 is printed, each of the two electrodes contacting the ent ⁇ speaking lying beneath electrode of the first electrode ⁇ pair 1 and one or more associated internal electrodes IE.
- the preferred printing are
- Electrode pair EP1 shows the arrangement on this process stage.
- Figure 4F shows the arrangement after the application of a
- Passivation layer PS which serves to mask the varistor ⁇ layer before the production of the connection contacts.
- the passivation layer can be printed or through
- the passivation layer may comprise any desired dielectric material, in particular a glass-containing layer or a polymer. Uncovered remain the areas of the second pair of electrodes, which are provided for the production of the external contacts. The second electrode pair EP can now be reinforced into these exposed regions by means of electrodeposition
- FIGS. 5A and 5B show the production of a film stack FS, which can serve as a prelaminate for a subsequent varistor layer.
- the film stack FS can still handle as a green sheet and can be laminated in this form on a green body.
- FIGS. 6A to 6E show various embodiments of component carriers according to the invention after the mounting of a component component on the connection contacts AK of the second electrode pair EP2, or in the variant according to FIG. 6E, on the connection surfaces AF.
- Figure 6A shows the
- a single-layer varistor layer VS is likewise used, but uncovered regions of the varistor layer and large parts of the second electrode pair EP2 are covered with a passivation layer PS. Only the locations remain in which the connection contacts are generated, to which the component BE is subsequently mounted with the aid of connection means VM.
- connection means VM a bump or a conventional soldering point can be used.
- the varistor layer VS has a floating inner electrode which is not in electrical contact with the first or second electrode pair. Again, a passivation layer PS is provided, which leaves only the connection contacts. in the
- a surface layer OS is additionally applied via the connection contacts or the second electrode pair EP in the region of the connection contacts.
- FIG. 6D shows a multilayer varistor layer in which at least two internal electrodes are provided
- Electrode pairs EP are electrically connected.
- a passivation layer PS over the second electrode pair and the exposed region of the varistor layer leaves only the area for the connection contacts AK, which can be generated galvanically.
- On the connection contacts is a
- FIG. 6E shows the already explained embodiment of a
- Component carrier in which the component is applied to the connection surfaces ⁇ on the opposite surface of the body GK by means of connecting means VM.
- the varistor layer is preferably covered with a passivation layer except for the external contacts AK in order to facilitate the handling of the component carrier with the mounted component BE or to protect the varistor layer VS during the handling of the arrangement.
- the component BE can be any electrical component which is sensitive to overvoltages, such as may be caused by an ESD pulse, and is protected by the varistor function within the varistor layer against these current or voltage surges.
- a game at ⁇ exemplary application is a LED which can be applied as a component BE on the component carrier.
- the manufacturing ⁇ procedures were only for an isolated body, which is intended for equipping with a device represented.
- a large-area main body GK or a corresponding wafer which can be separated into a plurality of individual component carriers in the last method step.
- a component carrier is not limited to those with two electrodes or with two connection contacts per electrode.
- a plurality of terminal ⁇ surfaces or electrode pairs may be provided, but which may be connected in parallel with each other again.
- the varistor layer may be provided without an internal electrode, with a floating internal electrode or with electrically connected overlapping internal electrodes.
- the number of internal electrodes increases the overlap area of
- Electrodes of opposite polarity determines the capacitance of the varistor. More overlapping area of the electrodes leads to more
- Double ceramic height with inner electrode in between results in twice the protection level, since then twice the number of microvaristors is in series.
- Double the volume of the varistor gives approximately twice the energy absorption capacity, since then twice the number of energy absorbers in the form of zinc oxide grains is available.
- the embodiment according to FIG. 6E has the further advantage that the first surface which can be equipped with the component BE consists to a large extent of the main body GK, which has a good reflectivity. If an LED is applied as the component BE, then its light emission is largely due to the higher reflection at the top
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Thermistors And Varistors (AREA)
- Details Of Resistors (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102016100352.2A DE102016100352A1 (de) | 2016-01-11 | 2016-01-11 | Bauelementträger mit ESD Schutzfunktion und Verfahren zur Herstellung |
| PCT/EP2017/050409 WO2017121727A1 (de) | 2016-01-11 | 2017-01-10 | Bauelementtraeger mit esd schutzfunktion und verfahren zur herstellung |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP3403267A1 true EP3403267A1 (de) | 2018-11-21 |
Family
ID=57777646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP17700228.4A Withdrawn EP3403267A1 (de) | 2016-01-11 | 2017-01-10 | Bauelementtraeger mit esd schutzfunktion und verfahren zur herstellung |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US10490322B2 (de) |
| EP (1) | EP3403267A1 (de) |
| JP (1) | JP6687738B2 (de) |
| DE (1) | DE102016100352A1 (de) |
| WO (1) | WO2017121727A1 (de) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050195549A1 (en) * | 2004-01-14 | 2005-09-08 | Matsushita Electric Industrial Co., Ltd. | Electrostatic discharge protection component |
| JP2010153719A (ja) * | 2008-12-26 | 2010-07-08 | Panasonic Corp | 過電圧保護部品およびその製造方法 |
| JP2015156406A (ja) * | 2012-05-25 | 2015-08-27 | パナソニック株式会社 | バリスタおよびその製造方法 |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03142901A (ja) * | 1989-10-30 | 1991-06-18 | Tokin Corp | 測温抵抗体 |
| JP2556151B2 (ja) * | 1989-11-21 | 1996-11-20 | 株式会社村田製作所 | 積層型バリスタ |
| JPH0572567A (ja) | 1991-09-13 | 1993-03-26 | Toppan Printing Co Ltd | 液晶表示装置の製造方法 |
| US5699035A (en) | 1991-12-13 | 1997-12-16 | Symetrix Corporation | ZnO thin-film varistors and method of making the same |
| WO2000004577A1 (de) * | 1998-07-15 | 2000-01-27 | Siemens Aktiengesellschaft | Verfahren zur herstellung eines keramischen körpers mit einem integrierten passiven elektronischen bauelement, derartiger körper und verwendung des körpers |
| DE19931056B4 (de) * | 1999-07-06 | 2005-05-19 | Epcos Ag | Vielschichtvaristor niedriger Kapazität |
| DE19961683A1 (de) | 1999-12-21 | 2001-06-28 | Philips Corp Intellectual Pty | Bauteil mit Dünnschichtschaltkreis |
| US7279724B2 (en) | 2004-02-25 | 2007-10-09 | Philips Lumileds Lighting Company, Llc | Ceramic substrate for a light emitting diode where the substrate incorporates ESD protection |
| DE102004031878B3 (de) * | 2004-07-01 | 2005-10-06 | Epcos Ag | Elektrisches Mehrschichtbauelement mit zuverlässigem Lötkontakt |
| CN101427326B (zh) * | 2006-04-24 | 2013-03-27 | Abb研究有限公司 | 基于微变阻器的过电压保护的装置和方法 |
| US7932806B2 (en) * | 2007-03-30 | 2011-04-26 | Tdk Corporation | Varistor and light emitting device |
| JP5188861B2 (ja) * | 2008-04-04 | 2013-04-24 | パナソニック株式会社 | 静電気対策部品およびこの静電気対策部品を備えた発光ダイオードモジュール |
| DE102008024480A1 (de) * | 2008-05-21 | 2009-12-03 | Epcos Ag | Elektrische Bauelementanordnung |
| EP2381451B1 (de) | 2010-04-22 | 2018-08-01 | Epcos AG | Verfahren zur herstellung einer elektrischen mehrschichtkomponente und elektrische mehrschichtkomponente |
| JP5877317B2 (ja) * | 2010-08-26 | 2016-03-08 | パナソニックIpマネジメント株式会社 | 過電圧保護部品および過電圧保護部品用の過電圧保護材料 |
| WO2012147299A1 (ja) * | 2011-04-26 | 2012-11-01 | パナソニック株式会社 | 静電気対策部品およびその製造方法 |
-
2016
- 2016-01-11 DE DE102016100352.2A patent/DE102016100352A1/de not_active Withdrawn
-
2017
- 2017-01-10 US US16/064,809 patent/US10490322B2/en active Active
- 2017-01-10 JP JP2018536133A patent/JP6687738B2/ja not_active Expired - Fee Related
- 2017-01-10 EP EP17700228.4A patent/EP3403267A1/de not_active Withdrawn
- 2017-01-10 WO PCT/EP2017/050409 patent/WO2017121727A1/de not_active Ceased
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050195549A1 (en) * | 2004-01-14 | 2005-09-08 | Matsushita Electric Industrial Co., Ltd. | Electrostatic discharge protection component |
| JP2010153719A (ja) * | 2008-12-26 | 2010-07-08 | Panasonic Corp | 過電圧保護部品およびその製造方法 |
| JP2015156406A (ja) * | 2012-05-25 | 2015-08-27 | パナソニック株式会社 | バリスタおよびその製造方法 |
Non-Patent Citations (1)
| Title |
|---|
| See also references of WO2017121727A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| DE102016100352A1 (de) | 2017-07-13 |
| US10490322B2 (en) | 2019-11-26 |
| US20190019604A1 (en) | 2019-01-17 |
| JP6687738B2 (ja) | 2020-04-28 |
| JP2019506741A (ja) | 2019-03-07 |
| WO2017121727A1 (de) | 2017-07-20 |
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