EP3350841A1 - TRANSISTOR A ENRICHISSEMENT COMPORTANT UNE HETEROJONCTION AlGaN/GaN ET UNE GRILLE EN DIAMANT DOPE P - Google Patents
TRANSISTOR A ENRICHISSEMENT COMPORTANT UNE HETEROJONCTION AlGaN/GaN ET UNE GRILLE EN DIAMANT DOPE PInfo
- Publication number
- EP3350841A1 EP3350841A1 EP16763850.1A EP16763850A EP3350841A1 EP 3350841 A1 EP3350841 A1 EP 3350841A1 EP 16763850 A EP16763850 A EP 16763850A EP 3350841 A1 EP3350841 A1 EP 3350841A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- heterojunction
- transistor
- gate
- aigan
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 229910003460 diamond Inorganic materials 0.000 title claims abstract description 75
- 239000010432 diamond Substances 0.000 title claims abstract description 75
- 230000005669 field effect Effects 0.000 title abstract 2
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 35
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 33
- 238000002161 passivation Methods 0.000 claims description 49
- 238000000034 method Methods 0.000 claims description 17
- 230000006911 nucleation Effects 0.000 claims description 15
- 238000010899 nucleation Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 229910002704 AlGaN Inorganic materials 0.000 abstract description 3
- 239000004411 aluminium Substances 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 21
- 239000002184 metal Substances 0.000 description 21
- 238000004519 manufacturing process Methods 0.000 description 12
- 230000005533 two-dimensional electron gas Effects 0.000 description 11
- 238000002347 injection Methods 0.000 description 10
- 239000007924 injection Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 125000004433 nitrogen atom Chemical group N* 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical group [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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Definitions
- Such transistors correspond, for example, to EMT (High Electron Mobility Transistor) type power transistors (or high electron mobility transistors).
- EMT High Electron Mobility Transistor
- the invention also relates to the field of electronic integrated circuits comprising such transistors.
- AIGaN / GaN type heterojunction within a power transistor such as an EMT type H transistor is advantageous because of the high carrier density (electrons) and the high mobility of these carriers obtained in the bidimensional electron gas (2DEG, or "2 Dimensional Electron Gas”) of the transistor.
- 2DEG bidimensional electron gas
- a portion of AIGaN or p + doped GaN is used to form the gate of the transistor, as described for example in the document "Gating Injection Transistor”.
- GIT A Normally-Off AIGaN / GaN Power Transistor Using Conductivity Modulation "by Y. Uemoto et al., Electron Devices, I EEE Transactions on, Vol. 54, Issue 12, December 2007, pages 3393 - 3399.
- the AIGaN or p-doped GaN layer which is produced in situ by growth on the AIGaN layer of the heterojunction must be etched to form the grid.
- stopping this etching on the AIGaN layer of the heterojunction poses problems of selectivity and control, generally leading to degradation of the AIGaN layer of the heterojunction and poor control of the passivation at the level of the heterojunction. engraved areas. This will notably have an impact on the two-dimensional electron gas, which will result in an increase in the transistor's on-state resistance and a degradation in its uniformity, and also result in charge trapping at the etched areas. .
- the addition of the p-doped layer in AIGaN or GaN on the heterojunction also poses problems, particularly for AIGaN.
- Nanocrystalline Diamond-Gated AIGaN / GaN HEMT from TJ. Anderson et al., Electron Device Letters, IEEE, Vol. 34, Issue 11, November 2013, pages 1382 - 1384, describes the production of a depletion or depletion HEMT transistor (also called a “normally-on” transistor). or “n-on” or “depletion-mode”) in which a p-doped diamond grid is used to form a heat sink.
- the realization of such a diamond grid overcomes some of the problems related to the realization of an AIGaN grid or p-doped GaN.
- the realization of the diamond grid described in this document involves significant thermal budgets (greater than 750 ° C.) making it impossible to integrate such a gate in a process for producing a transistor compatible with CMOS technology.
- the nucleation phase is more complex and does not allow p + diamond growth closer to the AIGaN layer.
- the nucleation technique used does not make it possible to obtain sufficiently consistent growth of the diamond because it does not itself have the necessary conformity when it is carried out on a non-planar surface, having a strong topology.
- An object of the present invention is to provide an enhancement transistor comprising an AIGaN / GaN heterojunction not having the disadvantages of the transistors of the prior art described above.
- the present invention proposes an enrichment transistor comprising at least:
- a heterojunction formed by at least a first layer comprising GaN and at least a second layer comprising AIGaN;
- a gate comprising p-doped diamond and such that a first portion of the second layer of the heterojunction delimiting a channel of the transistor is disposed between the gate and the first layer of the heterojunction;
- first portion of the second layer of the heterojunction has a thickness of between about 5 nm and 12 nm and an aluminum content between about 15% and 20%.
- the combined use of the p-doped diamond grid and the particular AIGaN layer of the heterojunction makes it possible to produce an enrichment transistor that does not have the problems associated with an AIGaN or p-doped GaN gate, especially those linked to to the epitaxial production of such a grid.
- the problems of etch selectivity during etching of the grid are notably solved by virtue of the use of p or p + doped diamond.
- the transistor according to the invention judiciously combines a p or p + doped diamond grid with a particular heterojunction making it possible to obtain an enrichment transistor having good performances, and in particular to obtain a threshold voltage which may be between approximately 1 V and 2 V.
- a transistor which would comprise a p + doped diamond grid combined with a heterojunction formed of a layer of GaN and a layer of AIGaN whose thickness would be less than 5 nm and / or whose aluminum would be less than 15% would not achieve sufficient performance.
- first part of the second layer of the heterojunction has a thickness of between approximately 5 nm and 12 nm and an aluminum content of between approximately 15% and 20% may allow the formation of an electron gas.
- two-dimensional surface density of charges ns less than about 4.10 12 cm 2 which allows, combined with the p-doped diamond grid, to form an enrichment transistor.
- the use of a diamond grid makes it possible to doping the grid with boron, which facilitates the implementation of this method. doping and makes it possible to easily obtain a doping level greater than that obtainable in a grid made of AIGaN or magnesium-doped GaN.
- aluminum level is used herein to refer to the molar fraction of AIN present in AIGaN.
- the aluminum content is 20%, which corresponds to about 10% of aluminum atoms in the whole of AIGaN (taking into account the N atoms). It can also be seen as the percentage of aluminum in the set of aluminum and gallium atoms present in AIGaN, without taking into account the N atoms present in AIGaN.
- the second layer of the heterojunction may have a substantially constant thickness and between about 5 nm and 12 nm.
- the second layer of the heterojunction may have a thickness of less than about 35 nm, and second portions of the second layer of the heterojunction, adjacent to the first portion of the second layer of the heterojunction, may have thicknesses greater than that of the first part of the second layer of the heterojunction.
- the second layer of the heterojunction may comprise at least one stack of at least one lower layer comprising AIGaN, a thickness of between about 5 nm and 12 nm and an aluminum content between about 15% and 20%, and at least one upper layer comprising AIGaN, a thickness such that the sum of the thicknesses of the lower layer and the upper layer is less than about 35 nm and a rate of aluminum between about 15% and 25%, and the first part of the second layer of the heterojunction may correspond to part of the lower layer.
- the second and third cases have the particular advantage of making it possible to achieve access, or zones, of source and drain of the transistor from portions of AIGaN which are thicker and / or which comprise a higher level of aluminum than the AIGaN portion located at the channel, which allows to obtain a higher surface density of charges and a lower on-state resistance without impacting the value of the threshold voltage which remains positive.
- the doping of diamond of the grid can be between about 3.10 18 cm “3 and 3.10 21 cm” 3 and / or the thickness of the gate may be between about a few tens and a few hundred nm, for example between about 50 nm and 300 nm.
- the thickness of the gate may be greater than the sum of the areas depleted in the p-doped diamond associated with contact with the AIGaN of the second layer and in contact with a gate metal, or metal contact, disposed on the doped diamond.
- a metal contact can be arranged on the grid. This metal contact can in particular serve as an electrical contact for applying an electrical potential on the gate.
- the contact between this metal contact and the p-doped diamond layer may be either ohmic or Schottky type, in particular depending on the doping level of the diamond and the nature of the metal forming the metal contact.
- this contact may be ohmic when this doping level (acceptor concentration) is greater than about 10 19 cm 3 .
- High doping of the diamond makes it possible to obtain an ohmic contact and thus obtain a GIT type transistor ("Gate Injection Transistor") in which an injection of holes from the p-doped diamond to the transistor channel is sought in order to improve its performance. performance in the on state of the transistor.
- a lower doping makes it possible to obtain a Schottky-type contact and thus to obtain a transistor with a higher threshold voltage which also makes it possible to greatly limit the injection of holes.
- the first layer of the heterojunction may be directly in contact with the second layer of the heterojunction.
- the absence of AIN between the layers of the heterojunction makes it possible in particular to obtain a good value of the threshold voltage of the transistor.
- the enrichment transistor may furthermore comprise at least:
- the gate may pass through at least the first and second passivation dielectric layers.
- the first layer of the heterojunction may be disposed on a substrate comprising Si and / or SiC and / or ⁇ 2 ⁇ 3 and / or sapphire.
- One or more other layers for growth of the first layer of the heterojunction may be disposed between the first layer of the heterojunction and the silicon substrate.
- the invention also relates to an electronic circuit comprising at least one enhancement transistor as previously described.
- the invention also relates to a method for producing an enrichment tra nsistor, comprising at least the steps of:
- the method may furthermore comprise, between the step of producing the heterojunction and the step of producing the grid, the implementation of the following steps:
- diamond for producing the gate of the transistor makes it possible, for its implementation, to implement an etching, for example of the 0 2 / Ar plasma type, compatible with standard CMOS processes and which is selective with respect to the second dielectric passivation layer on which the diamond layer is deposited.
- the method may furthermore comprise, between the production of the second opening and the production of the grid, a step of etching a second part of the second layer of the heterojunction lying opposite the second opening and covering the first part of the second layer of the heterojunction.
- the second layer of the heterojunction may comprise a stack of at least one lower layer deposited on the first layer of the heterojunction and comprising AIGaN, a thickness of between about 5 nm and 12 nm and a of aluminum between about 15% and 20%, and at least one upper layer deposited on the lower layer and comprising AIGaN, a thickness such that the sum of the thicknesses of the lower layer and the upper layer is less than about 35 nm and an aluminum content between about 15% and 25%, and the first part of the second layer of the heterojunction may correspond to a portion of the lower layer and the second portion of the second layer of the heterojunction may correspond to a part of the upper layer.
- the p-doped diamond can be achieved by the implementation of the following steps:
- Such an embodiment of the p-doped diamond grid makes the realization of the transistor compatible and integrable with the standard CMOS technology.
- FIG. 1 schematically represents an enhancement transistor comprising an AIGaN / GaN heterojunction and a p-doped diamond grid, object of the present invention, according to a first embodiment
- FIGS. 2A to 2C show examples of band diagrams of an enhancement transistor comprising an AIGaN / GaN heterojunction and a p-doped diamond grid, object of the present invention
- FIGS. 3A to 3C show steps of a method for producing an enhancement transistor comprising an AIGaN / GaN heterojunction and a p-doped diamond grid, also a subject of the present invention, according to the first embodiment
- FIGS. 4A to 4C show steps of a method for producing an enhancement transistor comprising an AIGaN / GaN heterojunction and a p-doped diamond grid, also a subject of the present invention, according to a second embodiment.
- FIG. 1 corresponds to a diagrammatic sectional view of an enrichment transistor 100, here of the HEMT type, and comprising a heterojunction of the AIGaN / GaN type and a p-doped diamond grid according to a first embodiment.
- the transistor 100 is made from a semiconductor substrate 102, for example comprising silicon, on which the heterojunction of the transistor 100 is made.
- the substrate 102 may also include SiC or ⁇ 2 ⁇ 3 or sapphire.
- This heterojunction comprises a first layer 104 comprising GaN and formed on the substrate 102, and a second layer 106 comprising AIGaN and formed on the first layer 104.
- a first AlN layer serving as a nucleation layer can be formed first on the substrate 102.
- transition layers for example comprising AIGaN whose aluminum content varies from one layer to another (for example several layers of AIGaN with a molar fraction of AlN which decreases with distance from the substrate 102, or a superlattice comprising several bilayers AlxGai-xN / GaN), are arranged on the nucleation layer in order to achieve isolation and adaptation of the crystal lattice parameter and to manage the mechanical stresses between the substrate and the layers of the heterojunction.
- a thick buffer layer for example several microns thick, is placed on the transition layers in order to limit the lateral and vertical leakage currents in the transistor 100 and also better to confine the two-dimensional electron gas.
- This thick buffer layer comprises for example carbon-doped GaN-Si (SI designating semi-insulator), or a GaN-Si / AlxGai-b bilayer with X of between about 4% and 8%.
- the layer 104 comprising here GaN nest (unintentionally doped) is then formed on the buffer layer.
- Such intermediate layers for producing the heterojunction are described, for example, in US 2002/0074552 A1.
- GaN GaN
- in situ SiN passivation can be carried out, deposited in the building of GaN growth.
- the AlGaN aluminum level of the second layer 106 is between about 15% and 20%.
- the thickness of the layer 106 is between about 5 nm and 12 nm.
- the thickness of the layer 104 is chosen as a function of the desired breakdown voltage for the transistor 100, and is for example between about 1 ⁇ and 15 ⁇ .
- a two-dimensional electron gas 105 is formed in the first layer 104, under the interface of the first layer 104 with the second layer 106 (this two-dimensional electron gas is delimited symbolically in the first layer 104 by dashed lines in the figure 1), at the level of the channel and the source and drain of the transistor 100.
- a first passivation dielectric layer 108 comprising, for example, SiN, covers the second layer 106.
- Two source and drain electrical contacts are formed through the first passivation dielectric layer 108. and are in contact with regions of the second layer 106 forming accesses to the source and the drain of the transistor 100.
- a second passivation dielectric layer 114 comprising for example Si0 2 , covers the first passivation dielectric layer 108 as well as the electrical contacts 110 and 112.
- each of the electrical contacts 110 and 112 may be embodied in the form of a bilayer of the type Ti / Al or Ta / Al.
- each of the electrical contacts 110 and 112 may be embodied in the form of a Ta / Al or Ti / Al type bilayer or a stack of layers. Ti / Al / Ni / Au.
- the transistor 100 also comprises a gate 116 disposed in an opening formed through the passivation dielectric layers 108 and 112 and such that it is directly in contact with a portion 115 of the second layer 106 defining the channel of the transistor 100.
- the gate 116 comprises p-doped nanocrystalline diamond (here doped with boron), with a doping level of between approximately 3.10 18 and 3.10 21 cm 3 (which corresponds to a p + doping level).
- the thickness of the gate 116 is for example between about 50 nm and 500 nm.
- the thickness and composition of the second layer 106 of material are such that they allow to obtain, in the first layer 104, a two-dimensional electron gas 105 of surface charge density ns less than about 4.10 cm 2 and 12 whose mobility of electrons is of the order of 1900 cm 2 / (Vs), or between about 1300 and 2000 cm 2 / (Vs), thus enabling the transistor 100 to have a low resistance in the on state.
- the characteristics of the diamond gate 116 contribute to the fact that the transistor 100 is an enhancement transistor. For the threshold voltage to be positive and as large as possible, the p-doping of the diamond in contact with the second layer AIGaN 106 is high so that the diffusion voltage (Vbi or Vbuiit-in) is maximum (Na> 3.10 18 ).
- the p + diamond thickness may be greater than about 50 nm.
- FIGS. 2A and 2B show the band diagrams of the transistor 100 in the parts of the different layers located opposite the gate 116, for the case where a zero voltage is applied to the gate 116 (via the metal contact 118) so that the transistor 100 is in a locked state (FIG. 2A), and for the case where a positive voltage greater than the threshold voltage of the transistor 100 is applied to the gate 116 so that the transistor 100 is in an on state (FIG. 2B).
- These diagrams correspond to those of a transistor 100 comprising a layer 106 of composition Alo, 2Gao, 8N.
- FIG. 2C represents the band diagram of the transistor 100 in the parts of the different layers located opposite the gate 116 when the gate contact is of Schottky type (unlike the diagrams of FIGS. 2A and 2B for which the gate contact is ohmic type).
- the thickness of the diamond of the gate 116 is greater than in the case of an ohmic contact because it is necessary to add the thickness of the depletion zone generated by the Schottky contact between the metallic contact 118 and the diamond of the gate 116
- the diamond thickness of the gate 116 is, for example, greater than about 100 nm.
- the values of the thickness of the second layer 106 and the aluminum level of the AIGaN of the second layer 106 previously described make it possible to have a judicious compromise between the achievable value of the threshold voltage (which is for example chosen equal to about 2 V), and the performance and robustness of the two-dimensional electron gas at the gate-drain and gate-source access areas of the transistor which constitute the bulk of the on-state resistance of the transistor .
- the threshold voltage which is for example chosen equal to about 2 V
- the thickness of the second layer 106 is chosen to be less than or equal to approximately 12 nm and the material of this second layer 106 has an aluminum content of less than or equal to approximately 20%.
- the aluminum content of the AIGaN of the second layer 106 is chosen to be greater than or equal to approximately 15% in order to have a sufficient surface density of the particles in the parts the second layer 106 peripheral to the portion 115 located under the gate 116, that is to say in the access areas to the source and the drain of the transistor 100.
- This aluminum content greater than or equal to about 15% also makes it possible to avoid degrading the confinement of the bidimensional electron gas 105 in the first layer 104 and thus to degrade the mobility of the two-dimensional electron gas 105.
- such an aluminum content greater than or equal to about 15% of the AIGaN of the second layer 106 makes it possible to produce this second layer 106 via an epitaxy guaranteeing the formation of a heterojunction and the appearance of a two-dimensional electron gas.
- the thickness of the second layer 106 also has an impact on the performance and robustness of the bidimensional electron gas 105. This thickness is here chosen greater than or equal to about 5 nm so that the epitaxy of the second layer 106 is sufficiently robust.
- the threshold voltage of transistor 100 will be between approximately 1 V and 2 V because of other parameters affecting the value of the threshold voltage (diamond / AIGaN interface states, diamond nucleation layer and diamond doping profile).
- the second layer 106 is not etched, which makes it possible to avoid problems related to the realization of the gate 116 (contamination interface states of the AIGaN and precise control of the thickness of the 'AlGaN).
- the first layer 104 is produced by epitaxial growth of GaN on the substrate 102 (by forming on the substrate 102 the different layers used for the growth of the first layer 104 as previously described).
- the second layer AIGaN 106 is then also formed by epitaxy on the first layer 104.
- the first passivation dielectric layer 108 is then deposited on the second layer 106.
- the electrical contacts 110 and 112 are then made by depositing a metal layer on the first passivation dielectric layer 108 and in the first openings. This metal layer is then etched so that remaining portions of this metal layer form the electrical contacts 110 and 112. Parts of the electrical contacts 110 and 112 project over the first passivation dielectric layer 108 at the periphery of the first openings.
- the second passivation dielectric layer 114 is then deposited by covering the electrical contacts 110, 112 and the first passivation dielectric layer 108.
- a portion of the second passivation dielectric layer 114 is etched to form a second opening 117 in the layer 114 forming a location of a first portion of the "Field Plate” grid.
- a portion of the first passivation dielectric layer 108 is also etched to extend the second aperture 117 in the layer 108 (but with dimensions, in the plane of the layer 108, lower than those in the plane of the layer 114) so as to to form an access to the second layer 106 for a second part of the grid called gate foot.
- the etching of the first passivation dielectric layer 108 is performed with a stop on the AIGaN of the second layer 106.
- a p + doped diamond layer is then produced, for example by growth from a previously deposited nucleation layer, in the etched portions of the layers 108 and 114, i.e. in the second aperture 117 formed through the layers 108 and 114, and the layer 114.
- a metal layer is then deposited on the p + doped diamond layer.
- the metal layer is etched, then the p + doped diamond layer is etched for example via a plasma etching 0 2 / Ar with stop on the layer 114, so that the remaining portions of these layers form the gate 116 and the metal contact gate 118 (FIG. 3C).
- the p + doped diamond grid 116 is preferably made at a low temperature, for example by steps involving temperatures below about 700 ° C. or advantageously between about 500 ° C. and 600 ° C., which makes the production of the grid 116 perfectly compatible with the presence of other elements on the substrate 102 made in CMOS technology, without damaging the characteristics of these other elements.
- a nucleation layer is performed in a manner compatible with the techniques of microelectronics on silicon, and then a conformal and low temperature growth of the diamond is made from the nucleation layer.
- 83-87 particularly describes details of realization of a low temperature nucleation layer by an electrostatic nucleation technique.
- Such a technique makes it possible to achieve this nucleation layer with good compliance with the topology on which this layer is made.
- the growth of diamond for example by MPCVD Microwave Plasma Chemical Vapor Deposition
- MPCVD Microwave Plasma Chemical Vapor Deposition
- This growth is also implemented at low temperature and makes it possible to obtain a diamond layer. having a good conformity with the topology on which it is made.
- the diamond of the grid 116 can also be realized with the implementation of different techniques.
- Various diamond CVD growth techniques are described in the Nanocrystalline Diamond Growth and Device Applications document by Michohn Dipalo, Ulm University, October 2, 2008. Steps of a method for producing transistor 100 according to a second embodiment are shown in FIGS. 4A to 4C.
- FIG. 4A which is similar to that previously described with reference to FIG. 3A, is produced.
- Portions of the passivation dielectric layers 108 and 114 are then etched, as previously described in connection with FIG. 3B, thus forming the second aperture 117 through the passivation dielectric layers 108 and 114 (the second aperture 117 having larger dimensions in the second passivation dielectric layer 114 only in the first passivation dielectric layer 108).
- the etching is not stopped on the second layer 106 but is prolonged in a portion of the thickness of the AIGaN of the second layer 106 (FIG. 4B ).
- the remaining thickness of AIGaN under the etched portion of the second layer 106 corresponds to the portion 115 of AIGaN whose thickness is between about 5 nm and 12 nm and comprising an aluminum content of between about 15% and 20% and which is intended to delimit the channel of the transistor 100.
- the transistor 100 is then completed by depositing the p + doped diamond layer in the etched portion of the second layer 106, in the second aperture 117 formed in the passivation dielectric layers 108 and 114, and on the second passivation dielectric layer 114.
- the metal layer is then deposited on the p + doped diamond layer.
- the metal layer and the p + doped diamond layer are etched so that the remaining portions of these layers form the gate 116 and the gate metal contact 118 (FIG. 4C).
- the fact that the second layer 106 is partially etched at the gate 116 to form the portion 115 delimiting the channel of the transistor 100 allows a second thicker initial layer 106 to be used. that in the first embodiment, and in particular whose thickness may be greater than about 12 nm, advantageously between about 25 nm and 35 nm.
- This second embodiment therefore makes it possible to have, at the level of the gate 116, a thickness of AIGaN sufficiently fine to obtain a positive threshold voltage while keeping, at the level of the gate-source and gate-drain access regions. , a greater thickness of AIGaN, for example between about 25 nm and 35 nm, and therefore a higher charge density and a lower on-state resistance Ron than in the first embodiment.
- This second embodiment thus makes it possible to partially dissociate the constraints related to obtaining a positive threshold voltage and sufficiently large of those related to obtaining a resistance in the on state of the transistor which is sufficiently low.
- the second layer 106 corresponds to a stack of at least one lower layer comprising AIGaN, placed against the first layer 104 of GaN and comprising a aluminum between about 15% and 20% and a thickness between about 5 nm and 12 nm, and an upper layer of AIGaN may in particular have an aluminum level different from that of the AIGaN of the lower layer for example greater than about 20% (e.g. about 25%).
- the total thickness of this stack of the lower layer and the upper layer is for example less than about 35 nm or between about 25 nm and 35 nm.
- the gate-source and gate-drain gate are in this case formed by portions 119 of the lower and upper layers of AIGaN adjacent to the Part 115.
- the AIGaN of the upper layer of the stack allows these accesses to have a higher charge density and a lower on-state resistance Ron than in the first embodiment.
- the doped diamond layer must be etched selectively with respect to the AIGaN of the second layer 106 to form the gate 116, for example by 0 2 / Ar plasma etching.
- such a transistor 100 may advantageously be part of electronic circuits used in the field of power electronics, for example in power conversion circuits. energy used in electric cars or in photovoltaic devices, or for the control of industrial motors, or the microwave power domain, for example in microwave power amplifiers used for radars or telecommunications devices , or for the realization of logical functions using integrated GaN technologies and managing for example the operation of power microwave amplifiers.
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Abstract
Description
Claims
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Application Number | Priority Date | Filing Date | Title |
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FR1558536A FR3041150B1 (fr) | 2015-09-14 | 2015-09-14 | Transistor a enrichissement comportant une heterojonction algan/gan et une grille en diamant dope p |
PCT/EP2016/071538 WO2017046077A1 (fr) | 2015-09-14 | 2016-09-13 | TRANSISTOR A ENRICHISSEMENT COMPORTANT UNE HETEROJONCTION AlGaN/GaN ET UNE GRILLE EN DIAMANT DOPE P |
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EP16763850.1A Withdrawn EP3350841A1 (fr) | 2015-09-14 | 2016-09-13 | TRANSISTOR A ENRICHISSEMENT COMPORTANT UNE HETEROJONCTION AlGaN/GaN ET UNE GRILLE EN DIAMANT DOPE P |
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US (1) | US20180182878A1 (fr) |
EP (1) | EP3350841A1 (fr) |
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WO (1) | WO2017046077A1 (fr) |
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US11257811B2 (en) | 2017-07-14 | 2022-02-22 | Cambridge Enterprise Limited | Power semiconductor device with an auxiliary gate structure |
US11336279B2 (en) | 2017-07-14 | 2022-05-17 | Cambridge Enterprise Limited | Power semiconductor device with a series connection of two devices |
GB2564482B (en) | 2017-07-14 | 2021-02-10 | Cambridge Entpr Ltd | A power semiconductor device with a double gate structure |
EP3948955A4 (fr) * | 2019-04-04 | 2023-05-10 | HRL Laboratories, LLC | Grille-t de plaque de champ miniature et son procédé de fabrication |
US11955478B2 (en) * | 2019-05-07 | 2024-04-09 | Cambridge Gan Devices Limited | Power semiconductor device with an auxiliary gate structure |
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US6649287B2 (en) | 2000-12-14 | 2003-11-18 | Nitronex Corporation | Gallium nitride materials and methods |
JP2009200395A (ja) * | 2008-02-25 | 2009-09-03 | Sanken Electric Co Ltd | Hfetおよびその製造方法 |
CN101604704B (zh) * | 2008-06-13 | 2012-09-05 | 西安能讯微电子有限公司 | Hemt器件及其制造方法 |
JP2010206125A (ja) * | 2009-03-06 | 2010-09-16 | Oki Electric Ind Co Ltd | 窒化ガリウム系高電子移動度トランジスタ |
US20110210377A1 (en) * | 2010-02-26 | 2011-09-01 | Infineon Technologies Austria Ag | Nitride semiconductor device |
FR2958640B1 (fr) | 2010-04-07 | 2012-05-04 | Commissariat Energie Atomique | Procede de fabrication d'un materiau poreux en diamant de synthese |
KR102065115B1 (ko) * | 2010-11-05 | 2020-01-13 | 삼성전자주식회사 | E-모드를 갖는 고 전자 이동도 트랜지스터 및 그 제조방법 |
US9379191B2 (en) * | 2011-12-28 | 2016-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | High electron mobility transistor including an isolation region |
US9331163B2 (en) * | 2013-08-30 | 2016-05-03 | The United States Of America, As Represented By The Secretary Of The Navy | Transistor with diamond gate |
US9425301B2 (en) * | 2014-04-30 | 2016-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Sidewall passivation for HEMT devices |
-
2015
- 2015-09-14 FR FR1558536A patent/FR3041150B1/fr not_active Expired - Fee Related
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2016
- 2016-09-13 EP EP16763850.1A patent/EP3350841A1/fr not_active Withdrawn
- 2016-09-13 WO PCT/EP2016/071538 patent/WO2017046077A1/fr active Application Filing
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US20180182878A1 (en) | 2018-06-28 |
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WO2017046077A1 (fr) | 2017-03-23 |
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