EP3332523B1 - Vorrichtung zur verarbeitung eines seriellen datenstroms - Google Patents

Vorrichtung zur verarbeitung eines seriellen datenstroms Download PDF

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Publication number
EP3332523B1
EP3332523B1 EP16804641.5A EP16804641A EP3332523B1 EP 3332523 B1 EP3332523 B1 EP 3332523B1 EP 16804641 A EP16804641 A EP 16804641A EP 3332523 B1 EP3332523 B1 EP 3332523B1
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Prior art keywords
latch
clock
feedback
data
latches
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French (fr)
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EP3332523A4 (de
EP3332523A1 (de
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Tonmoy Shankar MUKHERJEE
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Texas Instruments Inc
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Texas Instruments Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0045—Correction by a latch cascade

Definitions

  • bandwidth networks are needed to interconnect the computing devices and facilitate use of the increasing computing power.
  • increasing network data rates can be problematic due to limited channel bandwidth.
  • the bandwidth of an electrical channel e.g., a transmission line
  • Limited channel bandwidth can cause a transmitted pulse to spread across more than one unit interval. As a result, the received signal may suffer from inter-symbol interference.
  • Equalization functions may be added the input and/or output circuitry of a network to compensate for signal distortions resulting from limited channel.
  • a decision feedback equalizer is a nonlinear equalizer that is well-suited to equalizing a high-loss channel. Unlike linear equalizers, the DFE is able to flatten channel response and reduce signal distortion without amplifying noise or crosstalk, which is an important advantage when equalizing a high loss channel.
  • a DFE having a half-rate architecture is disclosed.
  • the DFE comprises two equalization paths with different latches.
  • a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. Also, if X is based on Y , then X may be based on Y and any number of other factors.
  • Serializer/deserializer (SERDES) circuits are employed in a variety of applications that require conversion of data between serial and parallel formats.
  • SERDES circuits for processing of high-speed serial data streams may include equalization circuitry, such as a decision feedback equalizer (DFE) to mitigate the effects of inter-symbol interference.
  • DFE decision feedback equalizer
  • a unit interval is a symbol interval or symbol duration
  • Conventional half-rate DFE architectures may be subject to the same sample feedback delay requirements as full rate architectures. More complex half rate DFE architectures include sample and hold circuitry that relaxes the feedback delay requirements, but implementing suitable sample and hold circuitry can be difficult and expensive.
  • the DFE circuits disclosed herein employ a half-rate architecture and cross-coupled equalization paths.
  • Each equalization path includes a feedback shift register that provides feedback data for use in the equalization paths.
  • Some implementations include relaxed feedback timing requirements that allow equalization of higher rate data streams than would be possible with conventional DFE architectures.
  • the DFE architectures disclosed herein allow implementation of DFEs for equalizing high rate data streams using semiconductor processes that may be unsuitable for implementing conventional DFEs to equalize such data streams.
  • SERDES circuits also include a serializer to convert data from parallel form to a bitstream.
  • a serializer that requires less circuitry than conventional high-speed serializers is disclosed herein.
  • the serializer of this disclosure may be implemented with substantially less (e.g., 40% less) circuitry and energy consumption than conventional serializers with equivalent performance.
  • Embodiments of the serializer disclosed herein avoid the use of flip-flops in favor of latches controlled via quadrature phase clock signals. In addition to reduced circuit area and power consumption, the use of quadrature phase clock signals may allow for increased performance due to reduced clock loading relative to conventional serializers.
  • FIG. 1 shows a schematic diagram of a DFE circuit 100 in accordance with example embodiments.
  • the DFE circuit 100 allows the feedback time specifications to be relaxed relative to conventional DFE implementations.
  • the DFE circuit 100 is a half-rate implementation that allows for equalization of higher speed data streams than conventional full rate implementations on a given semiconductor process, while requiring less circuitry that conventional half-rate DFE implementations.
  • the DFE circuit 100 includes parallel equalization paths 110 and 150 with multiple feedback paths in each equalization path. Alternate symbols of the data stream received at the input of the DFE circuit 100 are processed in each of the equalization paths 110, 150.
  • a multiplexer 148 selects output data from the equalization paths 110 and 150 to form an output data stream of equalized data. The multiplexer 148 serializes the half-rate data stream generated by the equalization paths 110 and 150 to produce a full-rate data stream.
  • the equalization path 110 includes a summing node 112, synchronization latches 114 and 116, feedback latch 118, and feedback shift register 120.
  • the feedback shift register 120 includes shift latches 122, 124, 126, and 128.
  • the equalization path 150 includes a summing node 152, and synchronization latches 154 and 156, feedback latch 158, and feedback shift register 160.
  • the feedback shift register 160 includes shift latches 162, 164, 166, and 168.
  • Each of the summing nodes 112 and 152 receives data from the input of the DFE circuit 100, and includes circuitry for summing the input data with feedback data.
  • the synchronization latch 114 receives as input summed data from the summing node 112 and provides output data as input to the synchronization latch 116 and the feedback latch 118.
  • the feedback latch 118 provides output data as input to the feedback shift register 120.
  • the data received by the feedback shift register 120 from the feedback latch 118 is latched in the shift latch 122 and shifted through the successive shift latches 124, 126, and 128.
  • the output data of the feedback latch 118, shift latch 124, and shift latch 128 are weighted in respective gain stages 130, 132, and 134, and provided to the summing node 152 of the equalization path 150.
  • the output data of shift latches 122 and 126 are weighted in respective gain stages 136 and 138, and provided to the summing node 112 of the equalization path 110.
  • the synchronization latch 154 receives as input summed data from the summing node 152 and provides output data for input to the synchronization latch 156 and the feedback latch 158.
  • the feedback latch 158 provides output data as input to the feedback shift register 160.
  • the data received by the feedback shift register 160 from the feedback latch 158 is latched in the shift latch 162 and shifted through the successive shift latches 164, 166, and 168.
  • the output data of the feedback latch 158, shift latch 164, and shift latch 168 are weighted in respective gain stages 170, 172, and 174 and provided to the summing node 112 of the equalization path 110.
  • the output data of shift latches 162 and 166 are weighted in respective gain stages 176 and 178 and provided to the summing node 152 of the equalization path 150.
  • Outputs of the synchronization latches 116 and 156 are provided to the multiplexer 148, or equivalent selection circuitry, that selects/routes the outputs of the latches 116, 156 to the output of the DFE circuit 100.
  • the gain stages 130-138 and 170-178 scale the outputs of latches 118-128 and 158-168 for combination with the data input to the circuit 100.
  • the polarities of the feedback signals provided from each of the gain stages 130-138 and 170-178 can be changed in the gain stage, in the summing nodes 112 and 152, or elsewhere in the DFE circuit 100.
  • DFE circuit 100 has been illustrated as included a feedback shift register 120, 160 that includes four shift latches, some embodiments of the DFE feedback shift register may include more or fewer shift latches with associated gain stages. In some embodiments, the feedback registers 118 and 158 may be respectively included in the feedback shift registers 120 and 160.
  • FIG. 2 shows the control signals applied to the DFE circuit 100.
  • the clocks I and Q have a period that is twice the unit interval of the data input to the circuit 100.
  • the clock I is aligned to transition at, or approximately at, the center of each unit interval.
  • the clock Q is a quadrature phase (i.e., delayed by 90 degrees) version of clock I. Accordingly, the transitions of clock Q are aligned at, or approximately at, the edges of the unit interval of the data input to the circuit 100.
  • latches controlled by the clock Q pass data during even numbered unit intervals and latch data during odd numbered unit intervals
  • latches controlled by an inverted version of the clock Q pass data during odd numbered unit intervals and latch data during even numbered unit intervals.
  • the clock I causes the latch 114 to transparently pass the data received from the summing node 112 in the initial half of each even numbered unit interval, and to latch the data through the middle of the subsequent odd-numbered unit interval.
  • the clock Q causes the latch 118 to transparently pass the data received from the latch 114 throughout even numbered unit intervals and to latch the received data throughout odd numbered unit intervals.
  • the latch 118 captures the data latched by the latch 114 and aligns the feedback data over the next unit interval for combination with input data in summing node 152.
  • the latch 116 is clocked by an inverted version of clock I. Accordingly, latch 116 is transparent while latch 114 is latched and stores the output of latch 114 for an additional unit interval after latch 114 becomes transparent.
  • Latch 122 is clocked by in inverted version of clock Q to latch, hold, and align the data provided from latch 118 with the subsequent even numbered unit interval. Thus, the latch 122 aligns the feedback data for combination with input data in summing node 112.
  • equalization path 110 for equalization of data in a given unit interval (e.g., unit interval 2), feedback from the immediately preceding unit interval (e.g., unit interval 1) is provided from the other equalization path 150, while feedback from the unit interval two ahead (unit interval 0) of the given unit interval is provided from equalization path 110.
  • Shift latches 124 and 128 are also clocked by clock Q, and latch data for provision to the summing node 152.
  • Shift latch 126 is clocked by the inverted version of clock Q and latches data for provision to summing node 112.
  • the equalization path 150 operates similarly to equalization path 110 with respect to odd unit intervals.
  • the DFE circuit 100 provides reduced implementation complexity relative to full-rate DFEs and conventional half-rate DFEs.
  • the DFE circuit 100 advantageously increases the time available for feedback of previously received symbol data. For example, at a 25 giga-bit input rate, the DFE 100 allows 40 picoseconds for feedback, rather than 20 picoseconds as provided in conventional DFE implementations.
  • the DFE 100 provides equalization at rates equivalent to that provided by a full rate architecture, but allows implementation using a less complex and less expensive semiconductor process. Conversely, on a given semiconductor process, the DFE 100 is useful to equalize higher rates than allowed by a conventional full-rate DFE. Further, DFE circuit 100 uses simple 50% duty cycle clocks, which are easier to generate and propagate in high-speed circuitry than asymmetric clocks. Additionally, in contrast to conventional DFEs, with the DFE circuit 100, feedback data is not required to be provided exactly at the unit interval boundary (i.e., the symbol zero crossing); instead, feedback data may advantageously be provided at any time, within margin constraints, before the unit interval during which the feedback data is to combined with input data.
  • FIG. 3 shows a schematic diagram of a DFE circuit 300 that is similar to the DFE circuit 100.
  • the DFE circuit 200 includes parallel equalization paths 310 and 350.
  • an additional synchronization latch 140 is coupled to the output of the synchronization latch 116.
  • the synchronization latch 140 rather than the synchronization latch 116 as in DFE circuit 100, is connected to, and provides equalized output data to, the multiplexer 148.
  • the feedback shift register 120 is coupled to, and receives input data from, the synchronization latch 116, rather than the feedback latch 118 as in the DFE circuit 100.
  • an additional synchronization latch 180 is coupled to the output of the synchronization latch 156.
  • the synchronization latch 180 is coupled to, and provides equalized output data to, the multiplexer 148.
  • the feedback shift register 160 is coupled to, and receives input data from, the synchronization latch 156, rather than the feedback latch 158.
  • FIG. 4 shows a block diagram of a SERDES 400 in accordance with various implementations.
  • the SERDES 400 includes a serial-to-parallel conversion path 412 and a parallel-to-serial conversion path 414.
  • the serial-to-parallel conversion path 412 includes a DFE circuit 404, which may the DFE circuit 100 or the DFE circuit 300, a clock/data recovery (CDR) circuit 406, and a serial-to parallel-converter 408.
  • the DFE 404 equalizes the serial input data to mitigate inter-symbol interference.
  • the CDR circuit 406 extracts clock and data signals from the equalized serial data stream generated by the DFE 404.
  • the serial-to parallel-converter 408 groups data bits recovered by the CDR circuit 406 in parallel words.
  • the serial-to-parallel conversion path 412 may include various other components and subsystems that have been omitted for clarity.
  • the serial-to-parallel conversion path 412 may include additional equalization circuitry, receiver circuitry and/or clock generation circuitry.
  • the parallel-to-serial conversion path 414 includes a serializer 402 and a driver 410.
  • the serializer 402 receives parallel data words (each word including a number of simultaneously presented data bits) and converts the parallel data words into a serial bitstream.
  • the driver 410 conditions the serial bitstream generated by the serializer 410 for transmission to other circuitry.
  • the DFE circuit 404 and/or the serializer 402 may also be applied in other applications, circuits, or systems that receive and/or generate serial data streams.
  • FIG. 5 shows a schematic diagram of a serializer 500 in accordance with example embodiments.
  • the serializer 500 may applied in the SERDES 400 as the serializer 402.
  • the serializer 500 includes multiple serialization layers 502, 504, 506 arranged in a tree structure where the output serial bitstream is generated at the root of the tree.
  • the three serialization layers 502, 504, 506 are arranged for serialization of eight bits of parallel data presented at the inputs of the serialization layer 502.
  • Other embodiments of the serializer 500 may include a different number of layers to serialize a different number of parallel data bits.
  • Each of the serialization layers 502-506 includes one or more serialization cells 508.
  • Each serialization cell 508 serializes two simultaneously presented bits/bitstreams.
  • FIG. 6 shows a schematic diagram of layers 504 and 506 of serializer 500 and shows additional details of the serializer cells 508.
  • Each serializer cell 508 includes latch 602, latch 604, and multiplexer 606.
  • the latches 602 and 604 each receive as input a bit to be serialized.
  • the multiplexer 606 selects, in turn, the output of each latch 602 and 604 to serialize the latch outputs.
  • serialization cell 508 which generates the output serial bitstream for the serializer 500
  • the latch 604 is controlled by Iclk and the latch 602 is controlled by Qclk.
  • Qclk is a quadrature phase version of Iclk (i.e., Qclk is Iclk delayed by 90°).
  • the multiplexer 606 is controlled by the clock applied to latch 604, Iclk in serializer cell 508.
  • the clock applied to latches 602 and 604, and the multiplexer 606 in a given layer is twice the rate of that applied in the subsequent layer.
  • the versions of Iclk and Qclk applied in serialization layer 504 are half the frequency of the versions of Iclk and Qclk applied in serialization layer 506.
  • the versions of Iclk and Qclk applied in serialization layer 502 are half the frequency of the versions of Iclk and Qclk applied in serialization layer 504. Accordingly, viewing the layers of the serialier 500 from the output of the serializer 500, each more distant layer applies clocks that are half the frequency of the clocks applied in the adjacent layer that is closer to output of the serializer 500.
  • the clock phase applied to the latches 602 and 604, and multiplexer 606 is changed.
  • the quadrature phase clock is applied to latch 602
  • the in-phase clock is applied to latch 604 and the multiplexer 606.
  • the clocking is changed in layer 504, such that the in-phase phase clock is applied to latch 602, and the quadrature phase clock is applied to latch 604 and the multiplexer 606.
  • FIG. 7 shows a diagram of timing signals in a serializer cell 508 in accordance with example embodiments.
  • the timing of FIG. 7 is with respect to operation of a serializer cell 508 of layers 504 and 506 of the serializer 500.
  • the data bits are presented to the serializer cell 508 at the rate of the clock Iclk.
  • the clock Iclk (DIV 2 ICLK) transitions at approximately the transition times of the data bits.
  • the clock signal Qclk (DIV 2 QCLK) is offset from Iclk by 90°.
  • the multiplexer 606 is controlled by the Qclk. Accordingly, data output of the serializer 508, in layer 504, is synchronized with Qclk, and each output bit is presented for one-half the period of Qclk.
  • the data labeled INPUT EVEN STREAM is presented to latch 602, and the data labeled INPUT ODD STREAM is presented to latch 604.
  • Latch 602 is transparent when Iclk is low and latches the input data when Iclk is high.
  • the multiplexer 606 selects the output of latch 602 when Qclk is low. Accordingly, the multiplexer 606 selects the output of the latch 602 for output during the center portion of each unit interval, as shown in FIG. 7 .
  • the latch 604 is transparent when Qclk is low and latches the input data when Qclk is high.
  • the latch 604 delays the INPUT ODD STREAM by 1/4 of an Iclk cycle, and the multiplexer 606 selects the output of latch 604 during the high portion of Qclk.
  • the Qclk applied is phase aligned with, and twice the frequency of, the Qclk applied in the previous layer (i.e., layer 504).
  • the input data received in the layer 506 transitions at approximately the high to low transitions times of the Qclk.
  • the Iclk applied in the layer 506 is phase aligned with, and twice the frequency of the Iclk applied in the previous layer (i.e., layer 504).
  • the Iclk is also inverted relative to that applied in layer 504.
  • the timing relationship of Iclk and Qclk are the same as in the previous layer, but the Iclk is inverted such that Iclk is delayed by 90° relative to Qclk.
  • the Qclk is applied to the multiplexer 606 and the latch 602, while the inverted Iclk is applied to the latch 604.
  • the clocks applied to the latches 602 and 604 and multiplexer 606 are switched relative to layer 504, as explained above, and, in layer 506, the DELAYED ODD STREAM is delayed by 1/4 cycle via the inverted Iclk.
  • the output of layer 506 is synchronous with the inverted Iclk.
  • the clock applied to the multiplexer of the previous layer is applied at twice the frequency to the latch(es) 502 of the subsequent layer
  • the inverse of the clock applied to the latch(es) 502 of the previous layer is applied at twice the frequency to the latch(es) 504 and the multiplexer 506 of the subsequent layer.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Dc Digital Transmission (AREA)

Claims (10)

  1. Entscheidungsrückkopplungsentzerrerschaltung, DFE-Schaltung, (100), die Folgendes umfasst:
    einen ersten Entzerrungspfad (110) und einen zweiten Entzerrungspfad (150), wobei jeder des ersten Entzerrungspfads und des zweiten Entzerrungspfads Folgendes enthält: einen Summierknoten (112, 152); einen ersten Synchronisationsriegel (114, 154), der konfiguriert ist, Daten, die vom Summierknoten empfangen werden, zu verriegeln; einen zweiten Synchronisationsriegel (116, 156), der konfiguriert ist, Daten, die vom ersten Synchronisationsriegel empfangen werden, zu verriegeln; einen rückgekoppelten Riegel (118, 158), der an einen Ausgang des ersten Synchronisationsriegels gekoppelt ist und konfiguriert ist, Daten, die vom ersten Synchronisationsriegel empfangen werden, zu verriegeln; ein rückgekoppeltes Schieberegister (120, 160), das an einen Ausgang des zweiten Synchronisationsriegels oder des rückgekoppelten Riegels gekoppelt ist, wobei das rückgekoppelte Schieberegister mehrere sequenziell gekoppelte Schieberiegel enthält; und einen Multiplexer (148), der an den zweiten Synchronisationsriegel jedes Entzerrungspfads gekoppelt ist und konfiguriert ist, auf der Grundlage eines ersten Takts Daten, die vom zweiten Synchronisationsriegel jedes Entzerrungspfads empfangen werden, wahlweise zu einem Ausgang der DFE-Schaltung zu leiten; wobei
    ein erster Schieberiegel konfiguriert ist, Daten, die vom zweiten Synchronisationsriegel oder vom rückgekoppelten Riegel empfangen werden, zu verriegeln und Daten zum Summierknoten zu liefern; ein zweiter Schieberiegel konfiguriert ist, Daten, die vom ersten Schieberiegel empfangen werden, zu verriegeln; im ersten Entzerrungspfad der rückgekoppelte Riegel und der zweite Schieberiegel konfiguriert sind, Daten zum Summierknoten des zweiten Entzerrungspfads zu liefern; und im zweiten Entzerrungspfad der rückgekoppelte Riegel und der zweite Schieberiegel konfiguriert sind, Daten zum Summierknoten des ersten Entzerrungspfads zu liefern;
    der rückgekoppelte Riegel durch einen Takt getaktet ist, der um 90 Grad verschoben den ersten Synchronisationsriegel taktet;
    im ersten Entzerrungspfad der erste Synchronisationsriegel durch den ersten Takt getaktet ist, der eine Periode besitzt, die das Doppelte der Symbolintervallzeit der Daten, die am Eingang der DFE-Schaltung empfangen werden, ist; der zweite Synchronisationsriegel durch einen zweiten Takt getaktet ist, der eine Umkehrung des ersten Takts ist; und der erste Schieberiegel durch einen dritten Takt, der eine quadraturphasenverschobene Version des zweiten Takts ist, getaktet ist; und
    im zweiten Entzerrungspfad der erste Synchronisationsriegel durch den zweiten Takt getaktet ist; der zweite Synchronisationsriegel durch den ersten Takt getaktet ist und das rückgekoppelte Schieberegister durch einen vierten Takt, der ein Umkehrung des dritten Takts ist, getaktet ist.
  2. DFE-Schaltung nach Anspruch 1, wobei in jedem des ersten Entzerrungspfads und des zweiten Entzerrungspfads ein dritter Schieberiegel konfiguriert ist, Daten, die vom zweiten Schieberiegel empfangen wurden, zu verriegeln und Daten zum Summierknoten des Entzerrungspfads zu liefern.
  3. DFE-Schaltung nach Anspruch 2, wobei im ersten Entzerrungspfad einer vierter Schieberiegel konfiguriert ist, Daten zum Summierknoten des zweiten Entzerrungspfad zu liefern; und im zweiten Entzerrungspfad ein vierter Schieberiegel konfiguriert ist, Daten zum Summierknoten des ersten Entzerrungspfads zu liefern.
  4. DFE-Schaltung nach Anspruch 1, die ferner einen Multiplexer umfasst; wobei jeder des ersten Entzerrungspfads und des zweiten Entzerrungspfads einen dritten Synchronisationsriegel enthält, der konfiguriert ist, Daten, die vom zweiten Synchronisationsriegel des Entzerrungspfads empfangen werden, zu verriegeln und Daten zum Multiplexer zu liefern; wobei der Multiplexer konfiguriert ist, auf der Grundlage des ersten Takts Daten, die vom zweiten Synchronisationsriegel jedes Entzerrungspads empfangen wurden, wahlweise zu einem Ausgang der DFE-Schaltung zu leiten.
  5. DFE-Schaltung nach Anspruch 1, wobei in jedem des ersten Entzerrungspfads und des zweiten Entzerrungspfads jeder nachfolgende Schieberiegel durch ein Taktsignal getaktet ist, das eine Umkehrung eines Taktsignals ist, das an einen unmittelbar vorhergehenden Schieberigel angelegt wurde.
  6. DFE-Schaltung nach Anspruch 1, wobei:
    der erste Synchronisationsriegel mittels eines ersten Takts gesteuert wird;
    der zweite Synchronisationsriegel mittels eines zweiten Takts, der eine Umkehrung des ersten Takts ist, gesteuert wird;
    das erste rückgekoppelte Schieberegister mittels eines dritten Takts, der eine Quadraturphasenversion des zweiten Takts ist, gesteuert wird;
    der erste Schieberiegel mittels eines vierten Takts, der eine Umkehrung des dritten Takts ist, gesteuert wird und
    jeder nachfolgende Schieberiegel mittels eines Taktsignals gesteuert wird, das eine Umkehrung eines Taktsignals ist, das an einen unmittelbar vorhergehenden Schieberiegel angelegt wurde.
  7. DFE-Schaltung nach Anspruch 6, wobei der erste Takt eine Periode besitzt, die das Doppelte der Symbolintervallzeit der Daten ist, die am Dateneingang der Schaltung empfangen werden.
  8. DFE-Schaltung nach Anspruch 1, die ferner Folgendes umfasst:
    einen zweiten Summierknoten, der an den Dateneingang der Schaltung gekoppelt ist;
    einen dritten Synchronisationsriegel, der konfiguriert ist, Daten vom zweiten Summierknoten zu empfangen;
    einen vierten Synchronisationsriegel, der konfiguriert ist, Daten vom dritten Synchronisationsriegel zu empfangen;
    einen zweiten Rückkopplungsriegel, der konfiguriert ist, Daten vom dritten Synchronisationsriegel zu empfangen; und
    ein zweites rückgekoppeltes Schieberegister, das mehrere sequenziell gekoppelte Schieberiegel enthält; wobei
    ein erster Schieberiegel des zweiten rückgekoppelten Schieberegisters konfiguriert ist, Daten, die vom vierten Synchronisationsriegel oder dem zweiten rückgekoppelten Riegel empfangen wurden, zu verriegeln und Daten zum Summierknoten zu liefern; erste alternative Schieberiegel des zweiten rückgekoppelten Schieberegisters konfiguriert sind, rückgekoppelte Daten zum zweiten Summierknoten zu liefern; und der zweite Summierknoten konfiguriert ist, ein Symbol, das vom Dateneingang der Schaltung empfangen wurde, durch Kombinieren der Daten, die durch den zweiten rückgekoppelten Riegel, die zweiten alternativen der Schieberiegel des ersten rückgekoppelten Schieberegisters und die ersten alternativen der Schieberiegel des zweiten rückgekoppelten Schieberegisters geliefert wurden, mit dem Symbol zu entzerren.
  9. DFE-Schaltung nach Anspruch 8, wobei
    der dritte Synchronisationsriegel mittels des zweiten Takts gesteuert wird;
    der vierte Synchronisationsriegel mittels des ersten Takts gesteuert wird;
    das zweite rückgekoppelte Schieberegister mittels des vierten Takts gesteuert wird;
    der erste Schieberiegel des zweiten rückgekoppelten Schieberegisters mittels einer Umkehrung des vierten Takts gesteuert wird; und
    jeder nachfolgende Schieberiegel des zweiten rückgekoppelten Schieberegisters mittels eines Taktsignals, das eine Umkehrung eines Taktsignals, das an einen unmittelbar vorhergehenden Schieberiegel angelegt wurde, gesteuert wird.
  10. DFE-Schaltung nach Anspruch 8, wobei zweite alternative Schieberiegel des zweiten rückgekoppelten Schieberegisters rückgekoppelte Daten zum ersten Summierknoten liefern.
EP16804641.5A 2015-06-05 2016-06-06 Vorrichtung zur verarbeitung eines seriellen datenstroms Active EP3332523B1 (de)

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EP3332523A4 (de) 2018-10-10
JP2018520585A (ja) 2018-07-26
EP3332523A1 (de) 2018-06-13
US20160359645A1 (en) 2016-12-08
CN113395223A (zh) 2021-09-14
WO2016197107A1 (en) 2016-12-08
CN107615724A (zh) 2018-01-19
JP6826545B2 (ja) 2021-02-03
US9660843B2 (en) 2017-05-23
CN107615724B (zh) 2021-06-01

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