EP3183807B1 - Switched capacitor converter - Google Patents

Switched capacitor converter Download PDF

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Publication number
EP3183807B1
EP3183807B1 EP15748239.9A EP15748239A EP3183807B1 EP 3183807 B1 EP3183807 B1 EP 3183807B1 EP 15748239 A EP15748239 A EP 15748239A EP 3183807 B1 EP3183807 B1 EP 3183807B1
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Prior art keywords
voltage
voltage divider
clock signal
switches
stage
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EP15748239.9A
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German (de)
English (en)
French (fr)
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EP3183807A1 (en
Inventor
Junmin JIANG
Jie Fu
Shu Xu
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Signify Holding BV
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Philips Lighting Holding BV
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/37—Converter circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/007—Plural converter units in cascade
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Definitions

  • SSL solid state lighting
  • driver on board where the drivers and light source are combined together on one carrier board.
  • the power supply of such boards varies from regulated standard voltage to an unregulated wide range voltage, which presents difficulties for drivers to maintain high performance.
  • PoE Power over Ethernet
  • V O M * V IN ⁇ R O * I L
  • V O , V IN , R O , I L , M are input and output voltage, equivalent output resistance, load current and conversion ratio, respectively.
  • One conventional approach to get a regulated output voltage out of a switch capacitor converter is to add a feedback loop to adjust the equivalent output resistance of the circuit.
  • SCC successive-approximation converter
  • Each stage divides the prior voltage into two down-scaled voltage ranges. Accordingly, if two stages are cascaded, four configurable ratios are available. Thus, N stages provide 2 N possible ratios. Therefore, after cascaded multi-stage SAR SCC, high voltage resolution can be achieved.
  • JP2010074929 discloses a system with two stages according to the preamble of claim 1.
  • the inventors have recognised that although linear output voltage can be achieved through the method described above of adding a feedback loop to adjust the equivalent output resistance of the SCC circuit, when the regulated output voltage is far away from the expected voltage which is decided by the conversion ratio or the ideal voltage, the efficiency of the SCC decreases. The larger the difference between the regulated output voltage and the ideal voltage, the larger the efficiency drop. Thus, the drawback of this method is sacrificing the efficiency while regulating voltage.
  • the inventors have further recognised that since a linear multi-stage SAR SCC uses several stages to obtain high resolution, the large number of capacitors and switches used decreases the overall efficiency of the converter.
  • a system comprising: a switched capacitor circuit comprising a plurality of voltage divider circuit stages including a first voltage divider circuit stage coupled to a second voltage divider circuit stage; and a controller configured to supply a clock signal to the first voltage divider circuit stage to provide a first voltage on an output node of the first voltage divider circuit stage during a first half cycle of the clock signal, and a second voltage on said output node during a second half cycle of the clock signal; and at least one selection switch connected between said output node and an input node of the second voltage divider stage; wherein the second voltage divider circuit stage is configured to charge to an input voltage during a half cycle of the clock signal, and the controller is configured to synchronize charging of the second voltage divider circuit stage to a selected one of (i) the first half cycle of the clock signal, wherein the first voltage is supplied as said input voltage, and (ii) the second half cycle of the clock signal, wherein the second voltage
  • At least one selection switch is connected between said output node and an input node of the second voltage divider circuit stage
  • the controller may be configured to synchronize charging of the second voltage divider circuit to the first half cycle of the clock signal by turning on said at least one selection switch during the first half cycle of the clock signal, to supply the first voltage on said input node.
  • the controller may be configured to synchronize charging of the second voltage divider circuit to the second half cycle of the clock signal by turning on said at least one selection switch during the second half cycle of the clock signal, to supply the second voltage on said input node.
  • the controller is configured to detect an output parameter and based on the detected output parameter and a target output voltage, determine a conversion ratio of the switched capacitor circuit and make said selection to configure the switched capacitor circuit to provide said determined conversion ratio.
  • the output parameter may be an output voltage of the switched capacitor circuit.
  • the system may further comprise at least one light source (D) wherein the switched capacitor circuit provides an output voltage that drives said at least one light source, and the output parameter is a sense voltage across a sensing resistor indicative of current flowing through said at least one light source.
  • D at least one light source
  • the first voltage divider circuit stage may be based on a Dickson ladder topology and configured to operate as either a divide-by-5 voltage divider or a divide-by-4 voltage divider.
  • the first voltage divider circuit stage may comprise a plurality of switches, and the controller configured to control the first voltage divider circuit stage to operate as divide-by-5 voltage divider by supplying said clock signal to turn on a first set of said plurality of switches on during the first half cycle of the clock signal and a second set of said plurality of switches during the second half cycle of the clock signal.
  • the controller may be configured to control the first voltage divider circuit stage to operate as divide-by-4 voltage divider by supplying said clock signal to turn on a third set of said plurality of switches on during the first half cycle of the clock signal and a fourth set of said plurality of switches during the second half cycle of the clock signal
  • the first voltage divider circuit stage may be a divide-by-two voltage divider.
  • the second voltage divider circuit stage may be a divide-by-two voltage divider.
  • the second voltage divider circuit stage may be configured to operate as either (i) a divide-by-2 voltage divider (ii) a divide-by-3 voltage divider, or a (iii) divide-by-1.5 voltage divider.
  • the second voltage divider circuit stage may comprise a plurality of switches, and the controller may be configured to: control the second voltage divider circuit stage to operate as a divide-by-2 voltage divider by supplying said clock signal to turn on a first set of said plurality of switches on during the first half cycle of the clock signal and a second set of said plurality of switches during the second half cycle of the clock signal; control the second voltage divider circuit stage to operate as a divide-by-3 voltage divider by supplying said clock signal to turn on a third set of said plurality of switches on during the first half cycle of the clock signal and a fourth set of said plurality of switches during the second half cycle of the clock signal; and control the second voltage divider circuit stage to operate as a divide-by-1.5 voltage divider by supplying said clock signal to turn on a fifth set of said plurality of switches on during the first half cycle of the clock signal and a sixth set of said plurality of switches during the second half cycle of the clock signal.
  • FIGS 1a and 1b illustrates a system 100 in which the SAR SCC in accordance with embodiments described below is implemented as a general purpose DC-DC converter ( Figure 1a ) and a system 150 in which the SAR SCC in accordance with embodiments described below is implemented as a Light Emitting Diode (LED) driver.
  • a general purpose DC-DC converter Figure 1a
  • a system 150 in which the SAR SCC in accordance with embodiments described below is implemented as a Light Emitting Diode (LED) driver.
  • LED Light Emitting Diode
  • Both system 100 and 150 comprise a switched capacitor power chain 102 and a controller 104.
  • the switched capacitor power chain 102 is supplied by an input voltage V in output from a power supply 101.
  • the controller comprises an analogue-to-digital converter (ADC) 110, a voltage reference (Ref) 114, a finite state machine (FSM) 108 which is configured to provide digital codes 112, and a digital controlled oscillator (DCO) 106.
  • ADC analogue-to-digital converter
  • Ref voltage reference
  • FSM finite state machine
  • DCO digital controlled oscillator
  • the output voltage is sensed in the DC-DC converter.
  • the LED driver senses the current through sensing resistor Rs, keeping the LED current controllable.
  • Figure 1b shown the SAR SCC being used to drive a single LED (D), the LED could also be a set of LEDs, for example a string of LEDs.
  • any suitable light source may be driven by the SAR SCC e.g. a high/low pressure gas discharge source, a laser diode, an incandescent source, or a halogen source.
  • Figure 1b shows the SAR SCC being used to drive an LED (D) embodiments of the present disclosure are not limited to only addressing driving of lighting loads, but also other applications, wherein size constraints similarly apply (e.g. in devices such as smart phones, laptop PCs and other portable devices, which need slim and compact electronic design).
  • the ADC 110 is arranged to sense an output parameter (e.g. output voltage Vo in Figure 1a or a sense voltage Vs across the sensing resistor Rs in Figure 1b ) and convert the analogue input signal into the digital domain.
  • the voltage reference 114 is a bias voltage for the conversion process performed by the ADC 110, and plays an important role in the sensing process as will be apparent to persons skilled in the art.
  • the ADC 110 is configured to uniquely represent all analogue inputs within a certain range by a limited number of digital output codes. A forward feedback loop sensing input voltage can be added to improve line regulation.
  • the output of the ADC 110 is coupled to an input of the FSM 108.
  • the FSM 108 is configured to receive the codes from ADC 110, determine the current status of output parameter, and output the corresponding digital codes to control selection switches in the switched capacitor power chain 102 (as will be described in more detail later).
  • the FSM 108 may be preconfigured to control the switched capacitor power chain 102 to provide a target voltage (target output parameter).
  • the FSM 108 may be configured to receive a target voltage (target output parameter) from a user, whereby this target voltage may be changed by the user in dependence on the application of the switched capacitor power chain 102.
  • the FSM 108 is further configured to output a control signal to the DCO 106.
  • the functionality of the FSM 108 may be implemented in code (software) stored on a memory comprising one or more storage media, and arranged for execution on a processor comprising on or more processing units. The code is configured so as when fetched from the memory and executed on the processor to perform operations in line with embodiments discussed below. Alternatively it is not excluded that some or all of the functionality of the FSM 108 is implemented in dedicated hardware circuitry, or configurable hardware circuitry like a field-programmable gate array (FPGA). Since the SAR SCC is designed for on-chip application, the FSM 108 may preferably be implemented using a digital circuit according to a Very-large-scale integration (VLSI) approach.
  • VLSI Very-large-scale integration
  • the DCO 106 is used to generate a switching clock signal at a desired frequency based on the control signal received from the FSM 108.
  • the switching clock signal is used to control the switches of the switched capacitor power chain 102. In the circumstance of light load, the DCO 106 will diminish the operating frequency to improve the overall efficiency.
  • the switched capacitor power chain 102 comprises five stages.
  • the final fifth SCC stage 205 has three switchable conversion ratios, that is it may operate as 3:1 voltage divider, operate as 2:1 voltage divider, or operate as a 3:2 voltage divider.
  • the first SCC stage 202 is shown in Figure 3 and is implemented using a Dickson Ladder topology based on five capacitors C1 to C5 and nine switches S1 to S9 of the single pole, single throw type. More specifically, the first SCC stage 202 comprises two flying ladders, each flying ladder comprising two capacitors: one first flying ladder comprises a first capacitor C1 in series with a third capacitor C3, and a second flying ladder comprises a second capacitor C2 in series with a fourth capacitor C4.
  • the first SCC stage 202 further comprises six central nodes 3011 to 3016.
  • a first switch S1 selectively connects the first central node 3011 (node A) to the positive terminal of the power supply 20.
  • a second switch S2 selectively connects the first central node 3011 to the second central node 3012 (node B).
  • a third switch S3 selectively connects the second node 3012 to the third central node 3013 (node C).
  • a fourth switch S4 selectively connects the third central node 3013 to the fourth central node 3014 (node D).
  • a fifth switch S5 selectively connects the fourth central node 3014 to the fifth central node 3015.
  • a fifth loading capacitor C5 is placed between the fifth central node 3015 and a sixth central node 3016.
  • the sixth central node 3016 is connected to the negative terminal of the power supply 20.
  • the first flying ladder comprising the first and third capacitors C1, C3 is located between the first central node 3011 and a first secondary node 3021.
  • a sixth switch S6 selectively connects the first secondary node 3021 to the fifth central node 3015;
  • a seventh switch S7 selectively connects the first secondary node 3021 to the sixth central node 3016.
  • a node in-between first capacitor C1 and third capacitor C3 is connected to the third central node 3013.
  • the second flying ladder comprising the second and fourth capacitors C2, C4 is located between the second central node 3012 and a second secondary node 3022.
  • An eighth switch S8 selectively connects the second secondary node 3022 to the fifth central node 3015;
  • a ninth switch S9 selectively connects the second secondary node 3022 to the sixth central node 3016.
  • a node in-between second capacitor C2 and fourth capacitor C4 is connected to the fourth central node 3014.
  • the two flying ladders are oppositely phased, thanks to an adequate sequence of opening and closing the switches S1 to S9.
  • switching sequence is used herein to refer to a first set of switches of a SCC stage being turned on during a first time phase (whilst a remaining second set switches are turned off), and the second set of switches of the SCC stage being turned on during a second time phase (whilst the first set of switches of the SCC stage are turned off).
  • the switching clock signal with a duty cycle D that is output from the DCO 106 is supplied to switches S1, S3, S5, S6 and S8 to control these switches to be in a given state during a first time phase ⁇ 1, for instance turned on, and a clock signal with a duty cycle of 1-D is supplied to switches S2, S4, S7 and S9 to control these switches to be in the opposite state, for instance turned off.
  • switches S1, S3, S5, S6 and S8 to control these switches to be in a given state during a first time phase ⁇ 1, for instance turned on
  • a clock signal with a duty cycle of 1-D is supplied to switches S2, S4, S7 and S9 to control these switches to be in the opposite state, for instance turned off.
  • the switching clock signal with a duty cycle D that is output from the DCO 106 is supplied to switches S3, S5, S6 and S8 to control these switches to be in a given state during a first time phase ⁇ 1, for instance turned on, and a clock signal with a duty cycle of 1-D is supplied to switches S1, S2, S4, S7 and S9 to control these switches to be in the opposite state, for instance turned off.
  • a clock signal with a duty cycle of 1-D is supplied to switches S1, S2, S4, S7 and S9 to control these switches to be in the opposite state, for instance turned off.
  • the difference between the first SCC stage 202 operating as a 5:1 voltage divider or a 4:1 voltage divider is dependent on the time phase of the switching clock signal during which the switch S1 is turned on.
  • the first bit (bit 1) of the digital output code output from the FSM 108 is used to control whether the switch S1 is turned on (closed) during the first time phase ⁇ 1 or the second time phase ⁇ 2 of the switching clock signal, thus controlling whether the the first SCC stage 202 operates as a 5:1 voltage divider or a 4:1 voltage divider.
  • the duty cycle of the switching clock signal that is output from the DCO 106 may be set as 50%.
  • dead-time is added to prevent the current shoot-through during the switches transmit state from turn-on to turn-off.
  • the dead-time of a SCC stage refers to the time period during a switching transition when the first set of switches and the second set of switches are both are open. So, the actual duty cycle may be configured to be a little less than 50%, e.g. 49%.
  • the dead-time may be added by a dead-time generator which generates two phase complimentary non-overlapping clock signals.
  • the first SCC stage 202 By implementing the first SCC stage 202 as a 4:1/5:1 voltage divider the number of switches and capacitors are reduced compared to a 2-stage 2:1 voltage divider whilst obtaining the same resolution, thereby enhancing area efficiency.
  • Figure 4 illustrates the connections between the first SCC stage 202 and the second stabilizer SCC stage 204a.
  • a selection switch block 206a (also shown in Figure 2 ) is coupled between the first SCC stage 202 and the second stabilizer SCC stage 204a.
  • a first selection switch SS1 of the selection switch block 206a is coupled between node A of the first SCC stage 202 and a higher voltage input V+ of the second stabilizer SCC stage 204a.
  • a second selection switch SS2 of the selection switch block 206a is coupled between node C of the first SCC stage 202 and the higher voltage input V+ of the second stabilizer SCC stage 204a.
  • a lower voltage input V- of the second stabilizer SCC stage 204a is coupled to the fifth central node 3015 of the first SCC stage 202.
  • the second stabilizer SCC stage 204a operates in two phases.
  • a first time phase ⁇ 1 the top plate of the flying capacitor Cf is connected to the higher voltage input V+ terminal of the second stabilizer SCC stage 204a and the bottom plate of the flying capacitor Cf is connected to Vo (output voltage of the second stabilizer SCC stage 204a) due to switch S24 being turned on (whilst switches S22(b) and S23 are turned off).
  • a second time phase ⁇ 2 the top plate of the flying capacitor Cf is connected to Vo (due to switch S23 being turned on) and the bottom plate of the flying capacitor Cf is connected to the lower voltage input V- of the second stabilizer SCC stage 204a due to switch S22(b) being turned on (whilst switch S24 is turned off).
  • the top plate of a loading capacitor Cl is connected to Vo, whilst the bottom plate of the loading capacitor Cl is connected to the lower voltage input V- of the second stabilizer SCC stage 204a
  • the output voltage will therefore be at half the input voltage (the midpoint between the voltage on the higher voltage input V+ of the second stabilizer SCC stage 204a and the voltage on the lower voltage input V- of the second stabilizer SCC stage 204a) when the loading is zero.
  • the output voltage Vo of the second stabilizer SCC stage 204a drops because of finite output resistance. Fortunately after regulation by the feedback controller 104, the desired output voltage can be reached.
  • the first SCC stage 202 When operating as a 5:1 voltage divider the first SCC stage 202 provides the voltage 1/5Vin to the lower voltage input V- of the second stabilizer SCC stage 204a. When operating as a 4:1 voltage divider the first SCC stage 202 provides the voltage 1/4Vin to the lower voltage input V- of the second stabilizer SCC stage 204a.
  • Figure 5 shows the first SCC stage 202.
  • the voltage of node A could output two possible voltage levels.
  • One of these output voltage levels is V1: 4/5Vin when the switching clock signal that is output from the DCO 106 is in the first time phase ⁇ 1 and another is V2:Vin, when the switching clock signal that is output from the DCO 106 is in the second time phase ⁇ 2.
  • the following cascaded SCC (the second SCC stage 204a in this example) has two operating phases, a charging phase and an output phase.
  • the following cascaded SCC (the second SCC stage 204a in this example) needs to charge at the first half-cycle and discharge at the second half-cycle.
  • charging depends on the output of the previous SCC (the first SCC stage 202 in this example), while in the second half-cycle, discharge is irrelevant to the output of the previous SCC (the first SCC stage 202 in this example).
  • embodiments of the present disclosure relate to the use of selection switches that are time-controlled to selectively synchronize the charging half-cycle of the following SCC with a desired one of the two half-cycles of the previous SCC, wherein the two half-cycles of the previous SCC respectively provide a stable and different conversion ratio.
  • the voltage domain of the second stabilizer SCC stage 204a can be varied by varying the voltage on the higher voltage input V+ of the second stabilizer SCC stage 204a.
  • a control signal is supplied to the selection switch SS1 of the selection switch block 206a.
  • the control signal supplied to the selection switch SS1 which corresponds to the second bit (bit 2) of the digital output code output from the FSM 108 is synchronised to the switching clock signal output from the DCO 106.
  • the control signal supplied to the selection switch SS1 is able to control the selection switch SS1 to turn on during the first time phase ⁇ 1 or to turn on during the second time phase ⁇ 2.
  • the selection switch SS1 is turned on and the selection switch SS2 is turned off (the voltage 4/5Vin output from node A of the first SCC stage 202 is supplied to the higher voltage input V+ of the second stabilizer SCC stage 204a) and during the second time phase ⁇ 2 the selection switch SS1 and the selection switch SS2 are both turned off, the voltage domain of the second stabilizer SCC stage 204a will be between 1/5Vin and 4/5Vin, therefore the output voltage Vo of the second stabilizer SCC stage 204a will be 2.5/5Vin. This is illustrated in column "STB 2nd" of Figure 8(c) .
  • the selection switch SS1 and the selection switch SS2 are both turned off, and during the second time phase ⁇ 2 the selection switch SS1 is turned on and the selection switch SS2 is turned off (the voltage Vin output from node A of the first SCC stage 202 is supplied to the higher voltage input V+ of the second stabilizer SCC stage 204a), the voltage domain of the second stabilizer SCC stage 204a will be between 1/5Vin and Vin, therefore the output voltage Vo of the second stabilizer SCC stage 204a will be 3/5Vin. This is illustrated in column "STB 2nd" of Figure 8(d) .
  • a control signal is also supplied to the selection switch SS2 of the selection switch block 206a.
  • the control signal supplied to the selection switch SS2 which corresponds to the third bit (bit 3) of the digital output code output from the FSM 108 is synchronised to the switching clock signal output from the DCO 106.
  • the control signal supplied to the selection switch SS2 is able to control the selection switch SS2 to turn on during the first time phase ⁇ 1 or to turn on during the second time phase ⁇ 2.
  • the selection switch SS1 is turned off and the selection switch SS2 is turned on (the voltage 2/5Vin output from node C of the first SCC stage 202 is supplied to the higher voltage input V+ of the second stabilizer SCC stage 204a) and during the second time phase ⁇ 2 the selection switch SS1 and the selection switch SS2 are both turned off, the voltage domain of the second stabilizer SCC stage 204a will be between 1/5Vin and 2/5Vin, therefore the output voltage Vo of the second stabilizer SCC stage 204a will be 1.5/5Vin. This is illustrated in column "STB 2nd" of Figure 8(a) .
  • the selection switch SS1 and the selection switch SS2 are both turned off, and during the second time phase ⁇ 2 the selection switch SS2 is turned on and the selection switch SS1 is turned off (the voltage 3/5Vin output from node C of the first SCC stage 202 is supplied to the higher voltage input V+ of the second stabilizer SCC stage 204a), the voltage domain of the second stabilizer SCC stage 204a will be between 1/5Vin and 3/5Vin, therefore the output voltage Vo of the second stabilizer SCC stage 204a will be 2/5Vin. This is illustrated in column "STB 2nd" of Figure 8(b) .
  • This voltage synchronous technique described above advantageously reduces the number of required selection switches between the first SCC stage 202 and the second stabilizer SCC stage 204a by half, compared with conventional methods; this is illustrated in Figure 6 .
  • the conventional method to obtain voltages 4/5Vin, 3/5Vin, 2/5Vin and 1/5Vin from the first SCC stage 202 is to use four selection switches connected to output nodes A, B, C and D, respectively.
  • the voltage synchronous technique described above only node A and node C are necessary to connect to selection switches SS1 and SS2 respectively. This is because each of node A and node C can output two voltages, which are able to cover the desired voltage range. Thus the number of selection switches required decreases by half to two (selection switch SS1 connected to node A and selection switch SS2 connected to node C).
  • the voltage domain of the second stabilizer SCC stage 204a is varied by varying only the voltage on the higher voltage input V+ of the second stabilizer SCC stage 204a, for the later stages (third SCC stage 204b, fourth SCC stage 204c, and final fifth SCC stage 205) the voltage domain for these stages may be varied by varying both the voltage on the higher voltage input V+ and the voltage on the lower voltage input V- of the respective stage.
  • selections switches are used to control the voltage domain for these stages. These selection switches are controlled by control signals which correspond to the digital output code output from the FSM 108.
  • a selection switch block 206b is used to control the voltage that is supplied to the higher voltage input V+ of the third SCC stage 204b.
  • Selection switch SS3 of the selection switch block 206b is coupled between node C of the first SCC stage 202 and the higher voltage input V+ of the third SCC stage 204b.
  • Selection switch SS4 of the selection switch block 206b is coupled between the output of the second stabilizer SCC stage 204a and the higher voltage input V+ of the third SCC stage 204b.
  • a selection switch block 206c is used to control the voltage that is supplied to the lower voltage input V- of the third SCC stage 204b.
  • Selection switch SS5 of the selection switch block 206c is coupled between node C of the first SCC stage 202 and the lower voltage input V- of the third SCC stage 204b.
  • Selection switch SS6 of the selection switch block 206c is coupled between the output of the second stabilizer SCC stage 204a and the lower voltage input V- of the third SCC stage 204b.
  • Selection switch SS7 of the selection switch block 206c is coupled between node the fifth central node 3015 of the first SCC stage 202 and the lower voltage input V- of the third SCC stage 204b.
  • the following voltage domains for the third SCC stage 204b may be created.
  • a voltage domain between 1/5Vin (at the lower voltage input V- of the third SCC stage 204b) and the output voltage of the second stabilizer SCC stage 204a (at the higher voltage input V+ of the third SCC stage 204b) can be selected by turning on both selection switches SS4 and SS7.
  • a voltage domain between the output voltage of the second stabilizer SCC stage 204a (at the lower voltage input V- of the third SCC stage 204b) and 2/5Vin (at the higher voltage input V+ of the third SCC stage 204b) can be selected by turning on both selection switches SS6 and SS3 (during the first time phase ⁇ 1).
  • the possible voltages output from the third SCC stage 204b (at the lower voltage input V-, output voltage and at the higher voltage input V+ of the third SCC stage 204b) are illustrated in column "3rd" of Figure 8(a) .
  • a voltage domain between 2/5Vin (at the lower voltage input V- of the third SCC stage 204b) and the output voltage of the second stabilizer SCC stage 204a (at the higher voltage input V+ of the third SCC stage 204b) can be selected by turning on both selection switches SS5 (during the first time phase ⁇ 1 ) and SS4.
  • a voltage domain between the output voltage of the second stabilizer SCC stage 204a (at the lower voltage input V- of the third SCC stage 204b) and 3/5Vin (at the higher voltage input V+ of the third SCC stage 204b) can be selected by turning on both selection switches SS6 and SS3 (during the second time phase ⁇ 2).
  • the possible voltages output from the third SCC stage 204b (at the lower voltage input V-, output voltage and at the higher voltage input V+ of the third SCC stage 204b) are illustrated in column "3rd" of Figure 8(c) .
  • a fourth and fifth bit (bits 4 and 5) of the digital output code output from the FSM 108 are used to control the selection switches of the selection switch block 206b and the selection switch block 206c.
  • Selection switch blocks 206d and 206e control the voltage domain for the fourth SCC stage 204c.
  • Selection switch block 206d comprises selection switches SS8 and SS9.
  • Selection switch block 206e comprises selection switches SS10 and SS11.
  • Selection switches SS8 and SS11 work in pair (both are turned on/off are turned on/off at the same time) and so do SS9 and SS10. If selection switches SS8 and SS11 are turned on, the voltage domain for the fourth SCC stage 204c is between the high voltage input V+ of the third SCC stage 204b and the output voltage of the third SCC stage 204b. If selection switches SS9 and SS10 are turned on, the voltage domain for the fourth SCC stage 204c is between the output voltage of the third SCC stage 204b and the low voltage input V- of the third SCC stage 204b.
  • a sixth bit (bit 6) of the digital output code output from the FSM 108 is used to control the selection switches of the selection switch block 206d and the selection switch block 206e.
  • a single bit of the digital output code output from the FSM 108 is sufficient to control the selection switches of the selection switch block 206d and the selection switch block 206e because when the selection switches SS8 and SS11 are turned on, selection switches SS9 and SS10 must be turned off and vice versa.
  • An inverter (not shown in Figure 2 ) is the simplest way to implement this at the circuit level.
  • Selection switch blocks 206f and 206g control the voltage domain for the final fifth SCC stage 205.
  • Selection switch block 206f comprises selection switches SS12 and SS13.
  • Selection switch block 206g comprises selection switches SS14 and SS15.
  • Selection switches SS12 and SS15 work in pair (both are turned on/off are turned on/off at the same time) and so do SS13 and SS14. If selection switches SS12 and SS15 are turned on, the voltage domain for the final fifth SCC stage 205 is between the high voltage input V+ of the fourth SCC stage 204c and the output voltage of the fourth SCC stage 204c. If selection switches SS13 and SS14 are turned on, the voltage domain for the final fifth SCC stage 205 is between the output voltage of the fourth SCC stage 204c and the low voltage input V- of the fourth SCC stage 204c.
  • a seventh bit (bit 7) of the digital output code output from the FSM 108 is used to control the selection switches of the selection switch block 206f and the selection switch block 206g.
  • a single bit of the digital output code output from the FSM 108 is sufficient to control the selection switches of the selection switch block 206f and the selection switch block 206g because when the selection switches SS12 and SS15 are turned on, selection switches SS13 and SS14 must be turned off and vice versa.
  • An inverter (not shown in Figure 2 ) is the simplest way to implement this at the circuit level.
  • Figure 5 illustrates the final fifth SCC stage 205 which comprises nine switches S1-S9 and two flying capacitors CF1 and CF2.
  • this stage is able to operate at three modes, i.e. operating as a 3:1 voltage divider, a 2:1 voltage divider, or a 3:2 voltage divider.
  • this triple conversion ratio stage has higher voltage choices, thereby holds higher voltage resolution.
  • switches S1, S9 and S8 will turn on in the first time phase ⁇ 1 (capacitor Cf1 and Cf2 are in series connection between V+ and Vo), and switches S2, S5, S4 and S7 will turn on in the second time phase ⁇ 2 (capacitor Cf1 and Cf2 are in parallel between V- and Vo).
  • switches S1, S6, S3 and S8 will turn on in the first time phase ⁇ 1 (capacitors Cf1 and Cf2 are in parallel between V+ and Vo), and switches S2, S5, S4 and S7 will turn on in the second time phase ⁇ 2 (capacitors Cf1 and Cf2 are in parallel between V- and Vo).
  • switches S1, S6, S2 and S8 will turn on in the first time phase ⁇ 1 (capacitors Cf1 and Cf2 are in parallel between V+ and Vo), and switches S4, S9 and S5 will turn on in the second time phase ⁇ 2 (capacitors Cf1 and Cf2 are in series between V- and Vo).
  • Selection switch block 206h comprises selection switches SS16 and.
  • Selection switch SS16 is coupled between the high voltage input V+ of the final fifth SCC stage 205 and the output of the switched capacitor power chain 102.
  • Selection switch SS17 is coupled between the output voltage of the final fifth SCC stage 205 and the output of the switched capacitor power chain 102.
  • An eighth bit (bit 8) of the digital output code output from the FSM 108 is used to control the selection switches of the selection switch block 206h.
  • a single bit is sufficient to control the selection switches of the selection switch block 206d as explained below.
  • Supposing two voltage domain VD1 and VD2 are provided by the final fifth SCC stage 205 and these voltage domain are continuous (meaning that the lowest voltage of VD1 is equal to the highest voltage of VD2). If the lowest voltage of VD1 is desired the voltage domain of the final fifth SCC stage 205 can be adjusted to VD2 and selection switch SS16 used to select the highest voltage of VD2 (this voltage is the same as the lowest voltage of VD1). Thus only two selection switches in the selection switch block 206h are used to select the output voltage.
  • selection switch SS16 When selection switch SS16 is turned on, SS17 is turned off and vice versa.
  • An inverter (not shown in Figure 2 ) is the simplest way to implement this at the circuit level. Should the lowest voltage of VD1 be required to be selectable, then an additional selection switch coupled between the low voltage input V- of the final fifth SCC stage 205 and the output of the switched capacitor power chain 102 is required (and an additional bit of the digital output code output from the FSM 108 will be required to control the selection switch block 206h).
  • each stage of the switched capacitor power chain 102 several configurable switches are used to adjust the connection of voltage nodes in the respective stage.
  • Each individual setting of switches in the switched capacitor power chain 102 corresponds to one conversion ratio. Therefore, by setting the stages of switches one by one, or adjacent stage, the continuous output voltage can be achieved. Although, output voltage is controlled not smoothly continuous, or is pseudo continuous, however, the steps can be accurately constrained in a small range.
  • the operating mechanism is illustrated with reference to the first SCC stage 202 operating as a 5:1 voltage divider.
  • One concept should be noted in that to achieve a stable output voltage, a stable reference node is necessary. Therefore, the second SCC stage 204a is involved to be used as a stabilizer, providing a scaled down voltage.
  • Figure 8 illustrates the possible voltages output from each stage (at the lower voltage input V-, output voltage and at the higher voltage input V+ of each stage).
  • a solid line represents a stable voltage
  • dotted line represents an unstable voltage
  • the shaded region represents the region which is able to be regulated.
  • the operation mechanism can be divided into four operating modes which are shown in Figures 8(a), (b), (c) and (d) , respectively.
  • the first SCC stage 202 (5:1 voltage divider and 4:1 voltage divider) divides the input voltage into 5 regions, e.g. 5Vin to 4Vin, 4Vin to 3Vin, 3Vin to 2Vin, 2Vin to 1Vin and 1Vin to ground.
  • the second stabilizer SCC stage 204a is connected between 2Vin and 1Vin, providing a stable voltage 1.5Vin for the following stages. Consequently, the output voltage can be from Vin to 2Vin in small steps.
  • the second stabilizer SCC stage 204a is connected between 2Vin to 3Vin, which is shown in Figure 8(c) , the region of output voltage is from 2Vin to 3Vin. It can be noticed that in the aforementioned conditions, the voltage 2Vin and 3Vin are unstable (drawn in dotted line).
  • the stage can provide Vin, 4/5Vin, 3/5Vin, 2/5Vin and 1/5Vin voltages. If operating as a 4:1 voltage divider, the possible voltages are 5/4Vin, VDD, 3/4Vin, 2/4Vin, and 1/4Vin. For each case, referring to Figure 8 , there are eight possible voltage domains before the final fifth SCC stage 205 shown in the "4 th " column in figure 8(a) ) and eight possible voltage domains before the final fifth SCC stage 205 shown in the "4 th " column in figure 8(c) , therefore sixteen in total.
  • the switched capacitor converter power chain 102 provides good line regulation, as well as high efficiency.
  • the switched capacitor converter power chain 102 can provide numerous conversion ratios to adapt to the input voltage. So, with multiple pseudo-continuous steps, good line regulation and output accuracy are achieved. Meanwhile, as the real voltage is closely near ideal voltage, efficiency drop by regulation is largely reduced.
  • the topology of the switched capacitor converter power chain 102 is completely capacitive, it is high possible to be fully integrated on a single chip, which means it is flexible and will be low cost. Those features extend it into diverse applications, for instance, driver-on-board LED driver, SoC power supply, remote sensor network, energy harvesting, etc.
  • All the switches used in the stages of the switched capacitor converter power chain 102 can be bi-directional and implemented in a suitable technology that is compatible with the switching frequency of the circuit.
  • the switches can be formed by Metal Oxide Semiconductor Field Effect Transistors (MOSFET) on a silicon substrate or High Electron Mobility Transistors (HEMT) on a Gallium-Nitride substrate.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistors
  • HEMT High Electron Mobility Transistors
  • a computer program may be stored/distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems. Any reference signs in the claims should not be construed as limiting the scope.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
EP15748239.9A 2014-08-18 2015-08-10 Switched capacitor converter Active EP3183807B1 (en)

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PCT/EP2015/068324 WO2016026724A1 (en) 2014-08-18 2015-08-10 Switched capacitor converter

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CN106575919A (zh) 2017-04-19
US20170264192A1 (en) 2017-09-14
US10103621B2 (en) 2018-10-16
JP2017523764A (ja) 2017-08-17
EP3183807A1 (en) 2017-06-28
WO2016026724A1 (en) 2016-02-25
CN106575919B (zh) 2019-08-02

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