EP3110007B1 - Générateur de tension de rampe et procédé de test d'un convertisseur analogique-numérique - Google Patents
Générateur de tension de rampe et procédé de test d'un convertisseur analogique-numérique Download PDFInfo
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- EP3110007B1 EP3110007B1 EP16175440.3A EP16175440A EP3110007B1 EP 3110007 B1 EP3110007 B1 EP 3110007B1 EP 16175440 A EP16175440 A EP 16175440A EP 3110007 B1 EP3110007 B1 EP 3110007B1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K4/00—Generating pulses having essentially a finite slope or stepped portions
- H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
- H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
- H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
- H03K4/50—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor
- H03K4/501—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator
- H03K4/502—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator the capacitor being charged from a constant-current source
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
- H03M1/109—Measuring or testing for dc performance, i.e. static testing
Definitions
- This disclosure relates generally to analog-to-digital converters, and more specifically, to a ramp voltage generator configured to test an analog-to-digital converter (ADC), and a corresponding method.
- ADC analog-to-digital converter
- a major portion of the cost of manufacturing integrated circuits involves testing.
- ADC analog-to-digital converter
- ADC analog-to-digital converter
- a frequency control loop is known from Viswanathan, T.R., et al. 'Switched-Capacitor Frequency Control Loop', IEEE J. Solid State (Wcuits Comput. Sci. California Institute of Technology Department of Computer Science, California Institute of Technology), 1 January 1981, pages 269-278, XP055243239, Retrieved from the Internet: URL http://ieeexplore.ieee.org/ielx5/4/22584/01051811.pdf
- the control loop uses an integrator to provide an oscillating output.
- the output has a period T.
- the period T is equal to the product of a capacitance C and a resistance R.
- the capacitance C and resistance R are connected in parallel between a voltage source and an input to an operational amplifier.
- a current source charges a first capacitor.
- charge transfers from the first capacitor to a second capacitor that is located in parallel to an op-amp.
- the charge transfer is a variable, and is responsible for setting a period of oscillations of the op-amp.
- the first capacitor is charged up by the current source for a variable period.
- the variable period is one factor that determines a final, steady oscillation period, to which the system converges.
- US4754226 A (Lusignan et al. ) provides a function generator for providing a variety of functions for analog signal processing applications. Capacitors and resistors are provided with an operational amplifier. The capacitors are switched by the output of a modulator. Many different functions can be created by varying two time constants, each of which depends on a combination of a resistor and a capacitor. Output voltages can be polynomial, logarithmic or exponential.
- US2009/0174442 A1 (Kim et al. ) provides a ramp signal. A ramp signal generation unit provides the ramp signal. A ramp signal correction unit feeds back and compares the ramp signal with a reference signal. The correction unit can correct a driving voltage that is used by the ramp signal generation unit.
- a further system is known from John Hogan et al.: 'Voltage to frequency converter for DAC test', Enhanced and synthetic vision 2003: [Conference Enhanced and Synthetic Vision 2002]; 21 April 2003, Orlando, Florida, USA, vol. 5837, 30 June 2005 (2005-06-30), pages 522-533, XP055738523, US; DOI 10.1117/12.608479; ISBN 978-1-5106-3673-6 .
- the system provides a modified relaxation oscillator.
- the modified oscillator is to convert the high-resolution analog output signal of a DAC to a stream of digital pulses.
- a charge accumulates on a first capacitor, and a voltage on a second integrating capacitor is held.
- a second, subsequent configuration of switches allows the charge from the first capacitor to move to the integrating capacitor.
- the output of the integrator feeds a comparator.
- a switch is connected across the integrating capacitor, and can short the capacitor under control of an output from the comparator.
- a ramp voltage generator comprising the features of appended claim 1 is provided.
- a method for generating a ramped voltage is provided, the method comprising the steps of appended claim 8.
- a ramp voltage generator configured to generate an analog input voltage to test an analog-to-digital converter.
- the ramp voltage generator is configured to ramp the analog input voltage from one voltage level to another voltage level.
- the ramp voltage generator uses a switched current source on each input of the differential inputs of a fully differential switched capacitor amplifier.
- a constant offset circuit is used to provide a fixed reference for generating the input voltage. The use of a known constant offset allows a non-linear ramped input voltage to be used for generating the ramped output voltage.
- the ramped input voltage may be a ramp down, ramp up, or some other ramp scheme.
- test voltage generator may be implemented on the same integrated circuit as the ADC, enabling the ability to test the ADC using only on-chip resources.
- a ramp voltage generator configured to provide an analogue input voltage to test an analog-to-digital converter, the ramp voltage generator configured to ramp the analogue input voltage between successive voltage levels, the ramp voltage generator comprising: a switched-capacitor amplifier having a differential amplifier, a first input terminal, a first output terminal, a first sampling capacitor having a first terminal coupled to the first input terminal, and a first gain capacitor having a first terminal coupled via a first switch to the first output terminal; a first current source having a first terminal coupled to a first supply terminal, and a second terminal coupled to the first input terminal; a second switch having a first terminal coupled to a second supply terminal, and a second terminal coupled to a second terminal of the first sampling capacitor; a third switch having a first terminal coupled to the second supply terminal, and a second terminal coupled to the first terminal of the first sampling capacitor; and a fourth switch having a first terminal coupled to the second supply terminal, and a second terminal coupled to the first terminal of the first gain capacitor.
- the ramp voltage generator further comprises a first offset generation circuit coupled to a second terminal of the first gain capacitor.
- the first constant offset generation circuit includes a first offset capacitor coupled by a fifth switch to the first supply terminal and coupled by a sixth switch to the second supply terminal.
- the first constant offset generation circuit is configured to provide a fixed reference voltage.
- the first constant offset generation circuit is configured to transfer charge selectively from the first offset generation circuit to the first gain capacitor.
- the ramp voltage generator is configured such that, during a first amplification phase: (i) the first switch, the third switch and the fifth switch are closed; (ii) the second switch and the sixth switch are open; and (iii) the first gain capacitor causes a first predetermined voltage change at the first output terminal, the ramp voltage generator thereby providing a first voltage, without a voltage offset, at the first output terminal.
- the ramp voltage generator is then further configured such that, during a second amplification phase: (i) the first switch, the third switch and the sixth switch are closed; (ii) the second switch and the fifth switch are open; and (iii) the first constant offset generation circuit transfers charge to the first gain capacitor, such that a change in charge at the first gain capacitor causes a second predetermined voltage change at the first output terminal, the ramp voltage generator thereby providing a second voltage, with a voltage offset, at the first output terminal.
- the ramp voltage generator thereby provides a non-linear ramped analogue input voltage to test the analog-to-digital converter.
- the ramp voltage generator may comprise a positive power supply voltage supplied to the first terminal, and a common mode voltage supplied to the second supply terminal, the common mode voltage being half-way between the positive power supply voltage and ground.
- the ramp voltage generator may further comprise a test control unit coupled to provide control signals to the switched-capacitor amplifier and to the first, second, third, fourth, fifth and sixth switches.
- the switched-capacitor amplifier may further comprise a second input terminal and a second output terminal, a second sampling capacitor having a first terminal coupled to the second input terminal, and a second gain capacitor having a first terminal coupled via a seventh switch to the second output terminal, and wherein the ramp voltage generator may further comprise: a second current source having a first terminal coupled to a third supply terminal, and a second terminal coupled to the second input terminal; an eighth switch having a first terminal coupled to the second supply terminal, and a second terminal coupled to the first terminal of the second sampling capacitor; a ninth switch having a first terminal coupled to the second supply terminal, and a second terminal coupled to a second terminal of the second sampling capacitor; and a tenth switch having a first terminal coupled to the second supply terminal, and a second terminal coupled to the first terminal of the second gain capacitor.
- the ramp voltage generator may further comprise a second constant offset generation circuit coupled to a second terminal of the second gain capacitor.
- the second constant offset generation circuit may include a second offset capacitor coupled via an eleventh switch to the second supply terminal and coupled via a twelfth switch to the third supply terminal.
- the second constant offset generation circuit is configured to provide a fixed reference voltage and to transfer charge selectively from the second constant offset generation circuit to the second gain capacitor.
- the ramp voltage generator may be configured such that, during the first amplification phase: (i) the seventh switch, the ninth switch and the twelfth switch are closed; (ii) the eighth switch and the eleventh switch are open; and (iii) the second gain capacitor contributes to the first predetermined voltage change at the first output terminal, the ramp voltage generator thereby providing the first voltage, without a voltage offset, at the first output terminal.
- the ramp voltage generator is then also configured such that, during the second amplification phase: (i) the seventh switch, the ninth switch and the eleventh switch are closed; (ii) the eighth switch and the twelfth switch are open; and (iii) the second constant offset generation circuit transfers charge to the second gain capacitor, such that a change in charge at the second gain capacitor contributes to the predetermined voltage change at the first output terminal, the ramp voltage generator thereby providing the second voltage, with a voltage offset, at the first output terminal.
- the ramp voltage generator may further comprise a test control unit coupled to provide control signals to the differential switched-capacitor amplifier and to the first to twelfth switches.
- a system may comprise an analog-to-digital converter having differential input terminals coupled to the first and second output terminals of the differential switched-capacitor amplifier of the ramp voltage generator, in the embodiment having the first and second offset circuits, wherein the analog-to-digital converter and the ramp voltage generator are integrated on the same integrated circuit.
- a method of generating a ramped voltage, to provide an analogue input voltage to test an analog-to-digital converter, by ramping the analogue input voltage between successive voltage levels the method performed in a ramp voltage generator circuit including an output terminal, a current source, a first capacitor, a second capacitor, and an amplifier having a first input and a first output, the method comprising: during a first phase having a first configuration of a plurality of switches, charging the first capacitor using the current source; and during a second phase having a second configuration of the plurality of switches, transferring charge from the first capacitor to the second capacitor such that a change in charge at the second capacitor causes a first predetermined voltage change at the output terminal.
- the ramp voltage generator circuit further includes a first constant offset generation circuit, and the method further comprises: during a third phase having a third configuration of the plurality of switches, transferring charge from the offset generation circuit to the second capacitor such that a change in charge at the second capacitor causes a second predetermined voltage change with a voltage offset at the output terminal.
- the method may further comprise coupling signals from a test control unit to the plurality of switches to configure the plurality of switches. system 10.
- clock signal CLK does not have to be provided via bus 18, but may be generated in test control 24.
- Differential amplifier 26 has differential positive and negative inputs and outputs and is characterized as having a relatively high open loop gain. The negative input of amplifier 26 is connected to one terminal of capacitor 32 and the positive input is connected to a terminal of capacitor 34.
- the second terminal of capacitor 32 is connected to a first terminal of switch 41 and the second terminal of capacitor 34 is connected to a first terminal of switch 43.
- the second terminals of switches 41 and 43 are connected together for receiving common mode VCM.
- Control terminals of switches 41 and 43 are connected to receive clock signals CLK 1.
- VCM is set to be about half way between a logic high and a logic low of the output voltages VOUT+ and VOUT-.
- Current source 28 has a first terminal connected to a reference voltage terminal for receiving reference voltage VREF, and a second terminal connected to the first terminal of switch 44.
- a second terminal of switch 44 is connected to the second terminal of capacitor 32, and a control terminal of switch 44 is connected to receive clock signal CLK 2.
- Reference voltage VREF is a regulated voltage and may be equal to about a supply voltage.
- Current source 30 has a first terminal connected to ground, and a second terminal connected to a first terminal of switch 46.
- Switch 46 has a second terminal connected to the second terminal of capacitor 34, and a control terminal connected to receive clock signal CLK 2.
- Switch 48 has a first terminal connected to receive VREF, a control terminal connected to receive CLK 4, and a second terminal.
- Switch 50 has a first terminal connected to receive VCM, a control terminal connected to receive clock signal CLK 5, and a second terminal connected to the second terminal of switch 48.
- Capacitor 40 has a first terminal connected to the second terminals of switches 48 and 50, and a second terminal connected to the negative input terminal of amplifier 26.
- Switch 52 has a first terminal connected to VCM, a second terminal, and a control terminal for receiving clock signal CLK 5.
- Switch 54 has a first terminal connected to ground, a second terminal connected to the second terminal of switch 52, and a control terminal for receiving clock signal CLK 4.
- Capacitor 42 has a first terminal connected to the second terminals of switches 52 and 54, and a second terminal connected to the positive input of amplifier 26.
- Switch 56 has a first terminal connected to VCM, a control terminal connected to receive clock signal CLK 3, and a second terminal connected to the negative input terminal of amplifier 26.
- Switch 58 has a first terminal connected to the positive input of amplifier 26, a control terminal for receiving clock signal CLK 3, and a second terminal connected to receive VCM.
- Capacitor 36 has a first terminal connected to the negative input of amplifier 26, and a second terminal.
- Capacitor 38 has a first terminal connected to the positive input of amplifier 26, and a second terminal.
- Switch 60 has a first terminal connected to the negative input of amplifier 26, a control terminal for receiving clock signal CLK 6, and a second terminal connected to the positive output terminal of amplifier 26.
- Switch 62 has a first terminal connected to the positive input of amplifier 26, a control terminal for receiving clock signal CLK 6, and a second terminal connected to the negative output terminal of amplifier 26.
- Switch 64 has a first terminal connected to the second terminal of capacitor 36, a control terminal connected to receive clock signal CLK 7, and a second terminal connected to the positive output terminal of amplifier 26.
- Switch 66 has a first terminal connected to the second terminal of capacitor 38, a control terminal connected to receive clock signal CLK 7, and a second terminal connected to the negative output terminal of amplifier 26.
- Switch 68 has a first terminal connected to the second terminal of capacitor 36, a control terminal connected to receive clock signal CLK 6, and a second terminal connected to receive VCM.
- Switch 70 has a first terminal connected to the second terminal of capacitor 38, a control terminal connected to receive clock signal CLK 6, and a second terminal connected to receive VCM.
- FIG. 3 through FIG. 9 illustrates the phases of an operating cycle for generating a test voltage using ramp voltage generator 20 in accordance with an embodiment.
- FIG. 10 illustrates the output voltage of the test voltage generator for each of the phases during one the operating cycle.
- the illustrated embodiment includes, in order, an initialization phase, a first sampling phase, a first amplification phase without offset, a first amplification phase with offset, a second sampling phase, a second amplification phase with offset, and finally a second amplification phase without offset.
- Other embodiments may change or re-order the illustrated phases.
- the phases are illustrated in FIG. 10 as time periods between tick marks.
- the differential output voltage VOUT+/VOUT- ramps up in the illustrated embodiment, but may ramp, or transition, differently in another embodiment.
- current sources/sinks 28 and 30 are used to charge/discharge capacitors 32 and 34 to provide a small step of voltage change on differential output voltage VOUT+/VOUT-.
- Gain capacitors 36 and 38 are used as charge pumping capacitors and the voltage on capacitors 32 and 34 is relatively constant at about the level of VCM. Therefore, a drain/source voltage shift of the current sources does not cause a non-linearity problem.
- the size of capacitors 36 and 38 determines a resolution of the ramp rate of the analog input voltage. Because capacitors 32 and 34 do not affect the ramp rate, they can have a relatively small capacitance value.
- Capacitors 40 and 42 are used to provide the constant offset voltage. The amplification phases are arranged alternately without offset/with offset to remove the impact of temperature changes.
- FIG. 3 illustrates ramp voltage generator 20 during an initialization phase (PH 0).
- Test control 24 provides clock signals CLK 1 through CLK 7 to configure the switches of ramp voltage generator 20 so that switches 41, 43, 48, 54, 56, 58, 60, 62, 68, and 70 are closed, or conductive, and switches 44, 46, 50, 52, 64, and 66 are open, or non-conductive for the entire phase.
- capacitors 32, 34, 36, 38, 40 and 42 are charged to common mode voltage VCM and the differential inputs and differential outputs of amplifier 26 are all charged to common mode voltage VCM.
- common mode voltage VCM is about half-way between positive power supply voltage VREF and ground GND.
- FIG. 10 illustrates output voltage VOUT+/VOUT- at an initial voltage V1 during initialization phase PH 0. Note that FIG. 10 is representing the differential output voltage VOUT+/VOUT- as a single-ended voltage for simplicity of illustration.
- FIG. 4 illustrates the switch configuration of ramp voltage generator 20 during first sampling phase PH 1.
- test control 24 provides clock signals CLK 1 through CLK 7 to configure the switches of ramp voltage generator 20 so that switches 44, 46, 48, 54, 56, and 58 are closed while all of the other switches are open.
- current source 28 provides voltage VREF to the first terminal of capacitor 32 through switch 44 while switch 56 connects common mode voltage VCM to the second terminal of capacitor 32 and the first terminal of capacitor 36. Voltage VREF is applied to the first terminal of capacitor 40 through switch 48.
- current source 30 connects ground terminal GND to the first terminal of capacitor 34 through switch 46 while switch 58 connects common mode voltage VCM to the second terminal of capacitor 34 and the first terminal of capacitor 48.
- Switch 54 connects ground terminal GND to the first terminal of capacitor 42.
- a charge stored on capacitors 40 and 42 is added to the charge on capacitors 36 and 38.
- Capacitors 32 and 34 function as sampling capacitors.
- Capacitors 36 and 38 function to provide gain.
- a step size of the voltage increase at the output terminals of amplifier 26 is determined by a relative size of capacitor 40 and capacitor 36. In one embodiment capacitor 40 is one-tenth the size of capacitor 36.
- Amplifier 26 is characterized as having a high open loop gain.
- FIG. 5 illustrates the switch configuration of ramp voltage generator 20 during amplification phase PH 2 without applying an offset voltage.
- test control 24 provides clock signals CLK 1 through CLK 7 to configure the switches of ramp voltage generator 20 to close switches 41, 43, 48, 54, 64, and 66. The other switches are open.
- a differential voltage at the output of amplifier 26 is amplified voltage V2 without a voltage offset as illustrated in FIG. 10 at phase PH 2.
- FIG. 6 illustrates the switch configuration of ramp voltage generator 20 during amplification phase PH 3 while applying the offset.
- test control 24 causes switches 41, 43, 50, 52, 64, and 66 to be closed. The other switches are open.
- Differential signals VOUT+/VOUT- are amplified with a voltage offset.
- Charge is transferred from the offset generation circuit, that includes switches 48 and 50 and capacitor 40, to capacitor 36 such that a change in charge at capacitor 36 causes a predetermined voltage change at the output terminal of amplifier 26. The same charge transfer will occur at the bottom half of ramp voltage generator 20 with gain capacitor 38.
- Capacitors 40 and 42 when switches 50 and 52 are closed, provide the voltage offset to gain capacitors 36 and 38.
- the voltage is illustrated in FIG. 10 as voltage V3 at phase PH 3.
- FIG. 7 illustrates the switch configuration of ramp voltage generator 20 during second sampling phase PH 4.
- switches 44, 46, 50, 52, 56, and 58 are closed and the rest of the switches are open.
- the output voltage VOUT+/VOUT- does not change and is still at voltage V3 during phase PH 4 in FIG. 10 .
- FIG. 8 illustrates the switch configuration of ramp voltage generator 20 during an amplification phase PH 5 with offset voltage.
- switches 41, 43, 50, 52, 64, and 66 are closed causing amplification of the differential output voltage VOUT+/VOUT-with a voltage offset.
- the differential output voltage is at level V4 at phase PH 5 in FIG. 10 .
- FIG. 9 illustrates the switch configuration of ramp voltage generator 20 during amplification phase PH 6 without offset voltage.
- switches 41, 43, 48, 54, 64, and 66 are closed. The other switches are open.
- the differential output voltage VOUT+/VOUT- is amplified without a voltage offset.
- the differential output voltage is at level V5 at phase PH 6 in FIG. 10 .
- Coupled is not intended to be limited to a direct coupling or a mechanical coupling.
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Claims (9)
- Générateur de tension en rampe (20) configuré pour délivrer une tension d'entrée analogique afin de tester un convertisseur analogique vers numérique (22), le générateur de tension en rampe (20) étant configuré pour faire évoluer progressivement la tension d'entrée analogique entre des niveaux de tension successifs, le générateur de tension en rampe (20) comprenant :un amplificateur à condensateurs commutés comportant : un amplificateur différentiel (26), une première borne d'entrée, une première borne de sortie, un premier condensateur d'échantillonnage (32) dont une première borne est couplée à la première borne d'entrée, ainsi qu'un premier condensateur de gain (36) dont une première borne est couplée par l'intermédiaire d'un premier interrupteur (64) à la première borne de sortie,une première source de courant (28) dont une première borne est couplée à une première borne d'alimentation et une seconde borne est couplée à la première borne d'entrée,un deuxième interrupteur (56) dont une première borne est couplée à une deuxième borne d'alimentation et une seconde borne est couplée à une seconde borne du premier condensateur d'échantillonnage (32),un troisième interrupteur (41) dont une première borne est couplée à la deuxième borne d'alimentation et une seconde borne est couplée à la première borne du premier condensateur d'échantillonnage (32),un quatrième interrupteur (68) dont une première borne est couplée à la deuxième borne d'alimentation et une seconde borne est couplée à la première borne du premier condensateur de gain (36),un premier circuit de génération de décalage constant (40, 48, 50), le premier circuit de génération de décalage constant (40, 48, 50) incluant un premier condensateur de décalage (40) couplé par un cinquième interrupteur (48) à la première borne d'alimentation et couplé par un sixième interrupteur (50) à la deuxième borne d'alimentation, le premier circuit de génération de décalage constant (40, 48, 50) étant configuré pour délivrer un premier décalage de tension fixe,le premier circuit de génération de décalage constant (40, 48, 50) étant couplé à une seconde borne du premier condensateur de gain (36), le premier circuit de génération de décalage constant (40, 48, 50) étant configuré pour transférer sélectivement une charge du premier circuit de génération de décalage constant (40, 48, 50) au premier condensateur de gain (36),le générateur de tension en rampe (20) étant configuré de sorte que pendant une première phase d'amplification, PH2 :(i) le premier interrupteur (64), le troisième interrupteur (41) et le cinquième interrupteur (48) sont fermés,(ii) le deuxième interrupteur (56) et le sixième interrupteur (50) sont ouverts, et(iii) le premier condensateur de gain (36) provoque une première modification prédéterminée de tension sur la première borne de sortie, le générateur de tension en rampe (20) délivrant ainsi une première tension (V2) sans le premier décalage de tension sur la première borne de sortie, etle générateur de tension en rampe (20) étant configuré de sorte que pendant une seconde phase d'amplification, PH3 :(i) le premier interrupteur (64), le troisième interrupteur (41) et le sixième interrupteur (50) sont fermés,(ii) le deuxième interrupteur (56) et le cinquième interrupteur (48) sont ouverts, et(iii) le premier circuit de génération de décalage constant (40, 48, 50) transfère une charge vers le premier condensateur de gain (36) de sorte à ce qu'une modification de la charge au niveau du premier condensateur de gain (36) provoque une seconde modification prédéterminée de tension sur la première borne de sortie,le générateur de tension en rampe (20) fournissant ainsi une seconde tension (V3) avec le premier décalage de tension sur la première borne de sortie, etgrâce à quoi le générateur de tension en rampe (20) délivre une tension d'entrée analogique en rampe non linéaire pour tester le convertisseur analogique vers numérique (22).
- Générateur de tension en rampe (20) selon la revendication 1, dans lequel :une tension d'alimentation positive, VREF, est fournie à la première borne, etune tension de mode commun, VCM, est fournie à la deuxième borne d'alimentation, la tension de mode commun étant située au milieu de la tension d'alimentation positive et de la masse.
- Générateur de tension en rampe (20) selon la revendication 1, comprenant en outre une unité de commande de test (24) couplée pour délivrer des signaux de commande à l'amplificateur à condensateurs commutés (26) et au premier interrupteur (64), au deuxième interrupteur (56), au troisième interrupteur (41), au quatrième interrupteur (68), au cinquième interrupteur (48) et au sixième interrupteur (50).
- Générateur de tension en rampe (20) selon la revendication 1,dans lequel l'amplificateur à condensateurs commutés comprend en outre une seconde borne d'entrée et une seconde borne de sortie, un second condensateur d'échantillonnage (34) dont une première borne est couplée à la seconde borne d'entrée, ainsi qu'un second condensateur de gain (38) dont une première borne est couplée par un septième interrupteur (66) à la seconde borne de sortie, etdans lequel le générateur de tension en rampe (20) comprend en outre :une seconde source de courant (30) dont une première borne est couplée à une troisième borne d'alimentation et une seconde borne est couplée à la seconde borne d'entrée,un huitième interrupteur (58) dont une première borne est couplée à la deuxième borne d'alimentation et une seconde borne est couplée à la première borne du second condensateur d'échantillonnage (34),un neuvième interrupteur (43) dont une première borne est couplée à la deuxième borne d'alimentation et une seconde borne est couplée à une seconde borne du second condensateur d'échantillonnage (34), etun dixième interrupteur (70) dont une première borne est couplée à la deuxième borne d'alimentation et une seconde borne est couplée à la première borne du second condensateur de gain (38),le générateur de tension en rampe (20) comprenant en outre un second circuit de génération de décalage constant (42, 52, 54), le second circuit de génération de décalage constant (42, 52, 54) incluant un second condensateur de décalage (42) couplé par un onzième interrupteur (52) à la deuxième borne d'alimentation et couplé par un douzième interrupteur (54) à la troisième borne d'alimentation,le second circuit de génération de décalage constant (42, 52, 54) étant configuré pour délivrer un second décalage de tension fixe, le second circuit de génération de décalage constant (42, 52, 54) étant couplé à une seconde borne du second condensateur de gain (38) le second circuit de génération de décalage constant (42, 52, 54) étant configuré pour transférer sélectivement une charge du second circuit de génération de décalage constant (42, 52, 54) au second condensateur de gain (38),le générateur de tension en rampe (20) étant configuré de sorte que, pendant la première phase d'amplification PH2 :(i) le septième interrupteur (66), le neuvième interrupteur (43) et le douzième interrupteur (54) sont fermés,(ii) le huitième interrupteur (58) et le onzième interrupteur (52) sont ouverts, et(iii) le second condensateur de gain (38) provoque la première modification prédéterminée de tension à la première borne de sortie, le générateur de tension en rampe (20) délivrant ainsi la première tension (V2) sans le second décalage de tension sur la première borne de sortie, etle générateur de tension en rampe (20) étant configuré de sorte que, pendant la seconde phase d'amplification PH3 :(i) le septième interrupteur (66), le neuvième interrupteur (43) et le onzième interrupteur (52) sont fermés,(ii) le huitième interrupteur (58) et le douzième interrupteur (54) sont ouverts, et(iii) le second circuit de génération de décalage constant (42, 52, 54) transfère une charge vers le second condensateur de gain (38) de sorte à ce qu'une modification de charge au niveau du second condensateur de gain (38) provoque la modification prédéterminée de tension à la première borne de sortie, le générateur de tension en rampe (20) délivrant ainsi la seconde tension (V3) avec le second décalage de tension sur la première borne de sortie, etgrâce à quoi le générateur de tension en rampe (20) délivre une tension d'entrée analogique en rampe non linéaire pour tester le convertisseur analogique vers numérique (22).
- Générateur de tension en rampe (20) selon l'une quelconque des revendications précédentes, dans lequel la taille du premier condensateur de décalage (40) vaut un dixième de la taille du premier condensateur de gain (36) .
- Générateur de tension en rampe (20) selon la revendication 4, comprenant en outre une unité de commande de test (24) couplée pour délivrer des signaux de commande à l'amplificateur différentiel à condensateurs commutés (26) et au premier interrupteur (64), au deuxième interrupteur (56), au troisième interrupteur (41), au quatrième interrupteur (68), au cinquième interrupteur (48), au sixième interrupteur (50), au septième interrupteur (66), au huitième interrupteur (58), au neuvième interrupteur (43), au dixième interrupteur (70), au onzième interrupteur (52) et au douzième interrupteur (54).
- Système (10) comprenant un convertisseur analogique vers numérique (22) comportant des bornes d'entrée différentielle couplées aux première et seconde bornes de sortie de l'amplificateur différentiel à condensateurs commutés (26) du générateur de tension en rampe (20) de la revendication 6, le convertisseur analogique vers numérique et le générateur de tension en rampe (20) étant intégrés sur le même circuit intégré.
- Procédé de génération d'une tension en rampe, afin de délivrer une tension d'entrée analogique permettant de tester un convertisseur analogique vers numérique (22) en faisant évoluer progressivement la tension d'entrée analogique entre des niveaux successifs de tension, le procédé étant effectué dans un générateur de tension en rampe (20) incluant une borne de sortie, une source de courant, un premier condensateur (32), un second condensateur (36) un amplificateur différentiel (26) comportant une première entrée et une première sortie, ainsi qu'un premier circuit de génération de décalage constant (40, 48, 50), le premier circuit de génération de décalage constant (40, 48, 50) incluant un premier condensateur de décalage (40) configuré pour délivrer un premier décalage en tension fixe, le procédé comprenant :pendant une première phase (PH1 ; PH4) présentant une première configuration d'une pluralité d'interrupteurs, la charge du premier condensateur (32) en utilisant la source de courant (28), etpendant une deuxième phase (PH2 ; PH5) présentant une deuxième configuration de la pluralité d'interrupteurs, le transfert de la charge depuis le premier condensateur (32) jusqu'au second condensateur (36) de sorte à ce qu'une modification de charge au niveau du second condensateur (36) provoque une première modification prédéterminée de tension au niveau de la borne de sortie, ce qui délivre ainsi une première tension (V2) sans le premier décalage de tension sur la première borne de sortie,et où le procédé comprend en outre :
pendant une troisième phase (PH3 ; PH6) présentant une troisième configuration de la pluralité d'interrupteurs, le transfert d'une charge depuis le premier circuit de génération de décalage constant (40, 48, 50) jusqu'au second condensateur (36) de sorte à ce qu'une modification de charge au niveau du second condensateur (36) provoque une seconde modification prédéterminée de tension au niveau de la borne de sortie, ce qui délivre ainsi une seconde tension (V3) avec le premier décalage de tension sur la première borne de sortie. - Procédé selon la revendication 8, comprenant en outre des signaux de couplage provenant d'une unité de commande de test (24) vers la pluralité d'interrupteurs dans le but de configurer la pluralité d'interrupteurs.
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