EP3055866A1 - Verfahren zur zeitlichen kalibrierung eines geschalteten kondensatorarrays - Google Patents
Verfahren zur zeitlichen kalibrierung eines geschalteten kondensatorarraysInfo
- Publication number
- EP3055866A1 EP3055866A1 EP13774408.2A EP13774408A EP3055866A1 EP 3055866 A1 EP3055866 A1 EP 3055866A1 EP 13774408 A EP13774408 A EP 13774408A EP 3055866 A1 EP3055866 A1 EP 3055866A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- memory cell
- memory cells
- signal
- time interval
- stored
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
- G11C27/024—Sample-and-hold arrangements using a capacitive memory element
Definitions
- the present invention relates to a method for calibrating an analog memory array (AMA) with a number (n) of selectively connectable to a signal input memory cells and a control circuit which successively and preferably cyclically controls the memory cells so that each memory cell with a local time interval to the immediately preceding memory cell stores a voltage value of a signal input to the signal input, wherein the voltage values stored in the memory cells are digitized successively in time.
- AMA analog memory array
- Such analog memory arrays in English: Analog Memory Array: AMA, which are often referred to as SCA (Switched Capacitor Arrays), are already used in many areas of scientific and industrial application, in which repetitive and especially transient signals must be digitized at high scanning speed. For example, but not exhaustive includes the detection and digitization of output signals from Photomultipliern, gas detectors and semiconductor detectors in particle physics, gamma detectors in positron emission tomography (PET), detectors (also semiconductor detectors) in length measuring systems, cost and technical superior oscilloscopes (by replacing the fast but expensive and inaccurate ADCs).
- PTT positron emission tomography
- ADCs are used in oscilloscopes, which typically have only four separate channels for signal acquisition and digitization.
- the basic principle of an AMA-based ADC is to sample an analog signal with a very fast frequency and to store the analog samples corresponding to the sampling points serially on individual memory cells, usually capacitors.
- the stored voltages are overwritten again and again until sampling is stopped by a trigger signal.
- the stored voltages then represent a snapshot of the transient signal, that is, a small period of time of the analog signal that is frozen, so to speak.
- the analog stored voltages representing signal points can be read by a much slower ADC or first transcribed into a buffer and then digitized.
- the time intervals at which the stored voltages follow one another in the original analog signal are determined by the sampling frequency at which voltages are stored in successive memory cells.
- the time length of the stored time segment corresponds to the number of memory cells reduced by one multiplied by the mean value of the time intervals between the memory cells. In other words, the length of the stored time period corresponds to the sum of the time intervals between the memory cells 1 to n.
- the stored signal portion would correspond to a section of the original analog signal of 999 times 1 ns, ie 0.999 ⁇ .
- sampling rate is used instead of “sampling frequency”.
- the sample signal is then not specified in GHz but as GSPS (Giga Sample Per Second) or MSPS (Mega Sample Per Second).
- the time axis of a signal stored in an AMA is neither sufficiently linear nor known with sufficient accuracy. Therefore, the AMA-based ADCs must be calibrated not only with respect to the digitization of the voltage values but also with respect to the time axis and the sampling frequency.
- the present invention is concerned with the calibration of the time axis and the sampling frequency.
- the voltage calibration has already taken place so that over the used voltage range the stored voltage values can be determined sufficiently accurately and linearly.
- the voltage used for the calibration can oscillate about lying at an arbitrary voltage zero axis.
- oscillating voltages are considered around a 0-axis zero axis for the sake of simplicity.
- the usual measures with which such signals are possibly raised in the voltage level, so as not to have to digitize voltage values in the range of 0 volts, are ignored.
- a signal oscillating between +1 volt and -1 volt is shifted, for example, in the voltage by +2 volts, so that it oscillates between +3 and +1 volts and thus can be precisely digitized in each time period.
- the digitized voltage values are then corrected by - 2 volts.
- the DRS4 chip contains 9 channels in which signal sections of an analog signal can be stored at a sampling frequency of up to 5 GHz.
- each channel 1024 capacitors with a capacitance of 150 fF are arranged in the ring as memory cells.
- the memory cells are cyclically rewritten cyclically over a control circuit, so the previously stored voltage values are permanently overwritten.
- the time intervals between two consecutive memory cells are typically in the range between about 2 and about 0.17 ns, because the sampling frequency f ab for the signal is between 500 MHz and up to 6 GHz.
- n memory cells are thus permanently the last (n-1) x 1 / f stored from seconds of the sampled signal, this signal section is permanently updated every 1 / f from seconds and moves as it were in the ring of memory cells.
- the current value to be stored thus migrates in a circle through the memory array, thereby overwriting each case the oldest stored voltage value.
- the writing is stopped and the contents of the memory cells are loaded into a buffer, preferably a shift register, the signal portion stored at this time is thereby frozen. From this shift register, the voltage values of the signal section are then sequentially read out with a 33 MHz ADC and digitized.
- the sampling frequency is determined by an annular inverter chain, in which an inverter block with two inverters is provided for each memory cell, wherein the each first inverter is designed as an AND gate.
- the first input of the AND gate is connected to the output of the second inverter in the previous inverter block.
- the speed at which the signal wave travels through the inverter chain depends on the switching time that the individual inverters require to pass a signal change at its input as a signal change at its output.
- an NMOS transistor is arranged, which operates as a voltage-controlled resistor.
- This resistor forms, with the parasitic input capacitance of the following inverter, an RC element which serves as a variable delay element for the signal wave traveling through the inverter chain.
- the output signal of the respective second inverter is used as a write signal for the associated memory cell and opens a corresponding switch which connects the memory cell to the signal input to which the analog signal to be stored and digitized is applied.
- a domino wave write signal By appropriate adjustment of the control voltage for the NMOS transistors so called a domino wave write signal is generated, which moves at a sampling frequency between several 100 MHz and 6 GHz through the inverter chain, with certain AMA sampling frequencies up to 10 GHz to reach.
- the local time intervals between the successive write signals for each two adjacent inverter bell are fixed but not equidistant. This means that a signal applied to the signal input is not sampled equidistantly, but that the signal portion stored in the memory cells is not more linear in the time axis.
- the DRS4 chip must be calibrated prior to measurement to obtain the correct time positions for all sampled signal values.
- the DRS4 chips are shipped uncalibrated, but PSI offers an evaluation board for the DRS4 chip and appropriate calibration software to calibrate a DRS4 channel.
- the board provides a sine wave signal of 240 MHz, which can be stored in one of the channels. From the deviation between the known period of the sinusoidal signal and the period of time determined from the stored waveforms, a calibration table is then calculated which contains for each memory cell an entry which contains the point of the actual time axis of each memory cell.
- the deviations between the ideal time axis (0 ns, 1 ns, 2ns, 3ns, ...) and the calibrated time axis should be up to 1 ns according to PSI.
- the memory cells should ideally store a voltage value every 0.5 ns.
- the time resolution of the DRS4 has in such a calibration depending on the sampling rate on a half-width (FWHM) of the Gaussian distribution of about 50 to 100 ps, as the inventors of the present application could prove in various experiments.
- the known calibration does not provide a consistent error. If a signal calibrated according to the calibration method proposed by PSI is used to multiply measure two signals which have a certain interval from each other, then the error in determining the time interval depends on the time interval. Different memory cell areas on the DRS4 chip thus provide different errors. These are unfavorable conditions for an experiment, because normally for all measurements for each memory cell area the same error is assumed in order to be able to compare different measurements.
- the measurement error in the time resolution can be reduced by a correspondingly high number of measurements, but only if always the same (high) error occurs.
- this object is achieved according to the invention by a method comprising the following steps: a) for each memory cell, a local time interval T
- dendauer T2 and at least partially has a linear slope
- there is a recalibration in which at least once between a first memory cell S x and a not immediately adjacent second memory cell S y, a global time interval T xy is determined, c) at least some of the in the previous step determined local time intervals T
- 0C are corrected using the global time interval T g i ob , and d) steps b) and c) are repeated until at least 50% of the local time intervals have been corrected at least once.
- the invention thus provides a one- or two-stage calibration method, which requires in a preferred embodiment, only a single ideal periodic signal, such as a sine wave signal whose period must be known very accurately.
- a separate calibration table must be created for each channel of the DRS4 chip, which contains an entry for each memory cell, which contains the actual time interval to the respective previous memory cell.
- This time interval will be referred to generally as T
- the errors are below 10 ps FWHM, which corresponds to a standard deviation RMS (root mean square) of less than 4.26 ps.
- the new calibration is more than a factor of 10 more accurate than the known calibration.
- the error is no longer dependent on the memory cell area in which a signal section is stored.
- the time interval between two time-shifted signals can be determined for different time intervals with a comparable Gaussian distribution of the time interval thus measured.
- the new method also leads to a more than 10 times lower error, so that the number of measurements with a calibrated according to DRS4 chip according to the invention is lower to achieve a certain standard deviation or half-width, as in a DRS4 chip with known Calibration.
- first of all a signal for the first (local) calibration is used in order to determine the time difference T toc for every two memory cells S xi and S x which immediately follow one another in the time sequence.
- any signal may be used which must have constant and at least approximately linear slopes.
- This signal is stored in the memory cells and then digitized.
- the digitized voltage values of the memory cells in which signal portions corresponding to the rising or falling edges have been stored are used for the determination of T
- fa b the sampling frequency, which can be considered as a first approximation to be constant on average.
- this method is repeated until a ⁇ ⁇ has been determined once for each memory cell S x .
- 0C refined by means of the second periodic signal, which must have a constant period T2 and at least partially also a linear slope.
- signal sections are stored and digitized in the AMA several times in succession for the same signal.
- the digitized voltage values of a signal section can be evaluated immediately and / or temporarily stored for later processing.
- the method according to the invention therefore provides, in one exemplary embodiment, for firstly digitizing and storing many signal sections before the stored digitized voltage values are used for the calibration.
- the digitized voltage values are used equally for the calibration and possibly only the correction values for the relevant memory cells are stored.
- a global time interval T g i ob between two non-adjacent memory cells S x and S y is then determined several times and used to iteratively improve the local time intervals.
- Step c) is understood to mean that a correction can also lead to a local time interval T
- determined in the preceding step 0C is not changed because the correction takes place with a correction factor K 1.
- This process is carried out iteratively.
- step c) the local time intervals of the memory cells are corrected, which are assigned to the global time interval T g i ob .
- Memory cells which are assigned to a global time interval T g i ob , according to the invention means the memory cells between the first memory cell S x and the last (second) memory cell S y including the last (second) memory cell S y .
- the global time interval T g i ob for the memory cells S 10 to S 2 o are therefore assigned 10 memory cells, namely Sn up to and including S 2 o, and thus the local time intervals ATn up to and including AT 2 o.
- Step d) is then to be understood so that either first several global time intervals T g i ob determined in step b) and then in step c) the local time intervals T
- the first signal is selected from the group consisting of sawtooth signals, trapezoidal signals, triangular signals and sinusoidal signals.
- a sine wave signal is used, because it is not only very stable and accurate to produce, but also has constant and sufficiently linear edges at the two zero crossings.
- the period T2 of the second signal is smaller than the sum of all local time intervals T
- At least one full period of the second signal lies between S x and S y , so that the voltages stored in S x and S y lie on different edges, which, however, have the same slope direction.
- the value of the global time interval T g i ob is determined exactly, it corresponds to T2 or a multiple (m) of T2.
- the local time intervals T toc from the estimation, the local calibration or from the global calibration preceding in the iteration are used to obtain a linear interpolation on one or more both "ends" of the global time interval T g i ob perform.
- interpolation only at S y or S x it is also advantageous that only the error of an interpolation is included in the calculation of T g i ob .
- the global time interval for first and second memory cells S x and S y is determined, the digitized voltage values U x and U y within a predetermined voltage interval differ from each other or immediately above a predetermined reference value.
- the global time interval T g i ob using the voltage difference between the stored in the first memory cell S x and in the immediately preceding memory cell S x- i voltage value U x or U x- i and / or by using the voltage difference between the voltage value U y or U y -i stored in the second memory cell S y and in the immediately preceding memory cell S y- i.
- step c) the associated local time intervals T
- the first and / or the second signal has at least one positive and at least one negative slope with linear slope within a period of time, and preferably in step a), the local time intervals T
- Memory cell S x is calculated. Because the determination of T
- the object underlying the invention in the method mentioned above is achieved by the steps: e) with the aid of at least one fed into the signal input and stored in all memory cells S x periodic signal, the known period T2 and at least partially a has linear slope, at least one global time interval AT xy is determined between a first memory cell S x and a not immediately adjacent second memory cell S y , f) step e) is repeated until k global time intervals AT xy for different combinations of S x and S y and g) from the k determined global time intervals AT xy , n local time intervals T toc are calculated, making use of the fact that each global time interval AT xy corresponds to the sum of the local time intervals T toc of the memory cells S x + i to S y , which are assigned to the respective global time interval AT xy , preferably e k »n is.
- step e) is carried out for at least two signals with different period T2, then in each case the global time interval AT xy determined and from the different measured global time intervals AT xy a weighted average value is calculated, which is used in step g).
- the invention thus also provides a method in which a modification of the global calibration is used.
- a large number of global time intervals Tgo b are respectively determined without interpolation at the ends of T g i ob . Rather, it will an average is formed by calculating each global time interval T g i ob for S x and S y from many local time intervals AT xy for different signals with different period lengths T2 sig .
- the global time intervals AT x , y may be different, so that averaging takes place.
- 40 sine signals with different T2 are each stored and digitized 1000 times, and then the weighted average values are formed for given S x and S y .
- the weighted average is calculated according to:
- the first memory cell S x is preferably used in such memory cells in which a voltage value U x is stored, which is immediately before or after a zero crossing, ie before or after a sign change in the stored and digitized signal section, and preferably within one predetermined error distance to the voltage value of the zero crossing.
- such memory cells are used as second memory cells, in which a voltage value U y is stored, which lies within a predetermined error distance to U x and on a signal section with the same slope direction.
- this number m of the signal periods T2 sig is determined based on the sign changes that occur between S x and S y .
- Two sign changes each correspond to a signal period T2.
- the global time interval AT xy is then equal to m ⁇ T2 sig and equal to the sum of the associated local time intervals AT
- This linear equation system is set up for at least as many different global time intervals T g i ob , so that the individual local time intervals T
- a sampling frequency f ab is determined for the control circuit .
- the sampling frequency f ab can be determined more accurately than can be taken from the manufacturer's instructions:
- n the number of memory cells in the AMA.
- n and not (n-1) enter into the calculation of f ab .
- the local time intervals T toc are calibrated with the aid of a measuring and evaluation unit, which stores at least one in which many hundreds of sinusoidal signals are applied to the signal input in the memory cells and then digitized and evaluated according to the method described above the local time intervals T
- the present invention also relates to a computer program for carrying out the new method and to a data carrier with an executable version of the computer program.
- the new method is not performed by hand.
- the program only has to enter the error distances and possibly the first value for the sampling frequency f ab .
- the channels of the memory array for a given sampling frequency f were from calibrated, either the values of the so corrected local time intervals T
- the present invention also relates to an analog memory array having a number (n) of selectively connectable to a signal input memory cells and a control circuit which successively and preferably cyclically the memory cells so that each memory cell with a local time interval T
- Fig. 1 is a schematic representation of an analog memory array (AMA);
- FIG. 2 shows a schematic representation of two inverter blocks from the control circuit for the memory array from FIG. 1;
- FIG. FIG. 3 shows a schematic representation of a sine signal stored in the memory array, and
- FIG. 2 shows a schematic representation of two inverter blocks from the control circuit for the memory array from FIG. 1;
- FIG. 3 shows a schematic representation of a sine signal stored in the memory array, and
- Fig. 4 is an enlarged view of the sine signal of Fig. 3, partially in the region of the rising edges.
- FIG. 1 schematically shows an analog memory array 10 with, by way of example, nine memory cells 11.
- memory arrays have many hundreds of memory cells 1 1, eg 1024.
- Each memory cell 1 1 is also referred to below as S x , where x denotes the number of the memory cell 1 1 in the sequence, ie runs from 1 to 1024.
- Each memory cell 1 1 is connected in parallel with a signal input 12 and a signal output 14. Furthermore, each memory cell 1 1 is connected to a shift register 15, in which the stored in the memory cells 1 1 voltages are reloaded in parallel.
- the voltages are then read out with a clock signal 16 serially with an analog-to-digital converter 17 and digitized there.
- the memory array 10 further comprises a control circuit 18 which cyclically and temporally one after the memory cells 1 1 drives so that it stores a voltage of a signal input to the signal input 12 with a local time interval T toc to the immediately preceding memory cell 1 1.
- the memory cells 1 1 are thus cyclically rewritten over the control circuit 18 cyclically with a sampling frequency f ab , the previously stored voltage values are thus permanently overwritten.
- the sampling frequency f ab is significantly greater than the frequency of the clock signal 16.
- the sampling frequency f ab is determined by an annular chain of inverters 19, in which an inverter block 21 with two inverters 19 is provided for each memory cell 1 1, as shown in FIG. 2.
- the respective first inverter 19 is designed as an AND gate 22.
- the first input 23 of the AND gate 22 is connected to the output of the second inverter 19 in the preceding inverter block 22. Through this self-contained inverter chain wanders a signal wave when applied to the second input 24 of each AND gate 22, an enable signal.
- the speed at which the signal wave travels through the inverter chain depends on the switching time required by the individual inverters 19 to pass a signal change at their input as a signal change at their output.
- an N MOS transistor 25 is arranged, which operates as a voltage-controlled resistor.
- This resistor forms, with the parasitic input capacitance of the following inverter, an RC element which serves as a variable delay element for the signal wave traveling through the inverter chain.
- each second inverter 19 in an inverter block 21 so a write signal 27 is generated for the associated memory cell 1 1, which connects the memory cell 1 1 with the signal input 12 to which the analog signal to be stored and digitizing is applied.
- a write signal 27, also referred to as a domino wave is generated, which travels at a sampling frequency f ab between a few 100 MHz and several GHz through the inverter chain.
- the memory array 10 may comprise a plurality of channels, in each of which a number of memory cells 1 1 is arranged, wherein all channels are controlled by the control circuit 18.
- 0C are calibrated, which takes place with the aid of a measuring and evaluation unit, which applies a sinusoidal signal 30 to the signal input 12, stored in the memory cells 1 1 and then digitized and evaluated.
- 3 shows a representation of the digitized voltage values U over the time axis t. 31 denotes the first memory cell 1 1 in the analog memory array 10 and 32 denotes the last memory cell 1 1.
- the two memory cells 31 and 32 correspond to the voltage values
- Two further memory cells are denoted by 33 and 34, which have respectively stored exactly the rising edge 35 and 36 of the signal 30 in the zero crossing. Between the memory cells 33 and 34, the signal 30 thus has a global time interval T g i ob , which corresponds to the period T2 of the signal 30.
- the signal 30 would be divided into hundreds of voltage values, which in the ideal case would each have an identical local time interval T toc to the previous voltage value, which would be 1 / 100 of T g i ob would amount.
- the local ones are
- Time intervals T 0C though firm but not equidistant. This means that the memory cells 33 and 34 are not both exactly in the zero crossing of the edges 35 and 36, respectively. In fact, it is even the case that neither the memory cell 33 nor the memory cell 34 will lie exactly at the zero crossing.
- FIG. 4 This situation is shown in FIG. 4, where on a greatly enlarged scale two positive edges 35 and 36 of the signal 30 are shown, which at zero crossing to one another have a time interval of T2 or m ⁇ T2. Neither the memory cell S x nor the memory cell S y are exactly in the zero crossing, but at the positive voltage values U x and U y .
- the measurement and evaluation unit now searches the storage cell with the voltage value is on the rising edge closest to the zero crossing, this is the memory cell S x, because the memory cell S x i corresponds to a voltage value U x i, the is absolutely larger than U x .
- the measuring and evaluation unit searches on one of the subsequent rising edge 36, the memory cell with the voltage value that comes closest to the voltage value U x , that is the memory cell S y .
- edge 36 is spaced from the edge 35 by a period T2.
- S y could also lie m period lengths T 2 away from S x , which is automatically determined on the basis of the zero crossings of the signal 30 between S x and S y .
- an error range is also specified as a function of the total voltage swing of the signal 30, which is, for example, 120 mV at a voltage swing of 1 volt.
- the inventors were able to calibrate a DRS4 chip with a standard deviation for each T toc of less than 4.26 ps.
- 0C are thereby ⁇ 100 fs exactly determined.
- the time resolution is ⁇ 4.26 ps for any desired time interval between two ideal signals.
- the global time interval between the memory cells S x and S y can also be determined more accurately.
- the voltage value U x for the memory cell S x lies between the voltage values U y- i and U y for the memory cells S y- i and S y .
- the correction factor K is then determined with which the individual local time intervals T toc for the memory cells S x to S y are corrected by multiplication.
- 0C values are set. For this, you can choose from the sampling frequency f ab specified by the manufacturer of the AMA or from the sampling frequency f ab according to the relation T
- 0C 1 / f ab or can be determined by means of the equations (1) and (2) described above.
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- Measurement Of Current Or Voltage (AREA)
Abstract
Description
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Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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PCT/EP2013/070892 WO2015051824A1 (de) | 2013-10-08 | 2013-10-08 | Verfahren zur zeitlichen kalibrierung eines geschalteten kondensatorarrays |
Publications (1)
Publication Number | Publication Date |
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EP3055866A1 true EP3055866A1 (de) | 2016-08-17 |
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Family Applications (1)
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EP13774408.2A Withdrawn EP3055866A1 (de) | 2013-10-08 | 2013-10-08 | Verfahren zur zeitlichen kalibrierung eines geschalteten kondensatorarrays |
Country Status (2)
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WO (1) | WO2015051824A1 (de) |
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CN108333912B (zh) * | 2018-02-09 | 2020-03-31 | 中国科学技术大学 | 一种用于开关电容阵列芯片的时间修正方法 |
CN114265300B (zh) * | 2021-12-30 | 2022-12-30 | 中国科学技术大学 | 一种用于开关电容阵列芯片的时间修正方法 |
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KR100252647B1 (ko) | 1997-06-17 | 2000-04-15 | 윤종용 | 스위치/커패시터어레이를구비한아날로그/디지털변환기 |
EP2045816A1 (de) | 2007-10-01 | 2009-04-08 | Paul Scherrer Institut | Schnelles Auslesungsverfahren und Schaltkondensator-Arrayschaltung zur Wellenform-Digitalisierung |
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2013
- 2013-10-08 WO PCT/EP2013/070892 patent/WO2015051824A1/de active Application Filing
- 2013-10-08 EP EP13774408.2A patent/EP3055866A1/de not_active Withdrawn
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