EP3055866A1

EP3055866A1 - Method for the temporal calibration of a switched capacitor array

Info

Publication number: EP3055866A1
Application number: EP13774408.2A
Authority: EP
Inventors: Bernd Pichler; Daniel STRICKER-SHAVER; Armin KOLB; Christoph Parl; Stefan Ritt
Original assignee: Eberhard Karls Universitaet Tuebingen
Current assignee: Eberhard Karls Universitaet Tuebingen
Priority date: 2013-10-08
Filing date: 2013-10-08
Publication date: 2016-08-17
Also published as: WO2015051824A1

Abstract

The invention relates to a method for calibrating an analog memory array, which analog memory array has a number (n) of memory cells, which can be selectively connected to a signal input, and a control circuit, which activates the memory cells in succession and preferably cyclically in such a way that each memory cell stores a voltage value of a signal fed into the signal input with a local time difference T_loc in relation to the immediately preceding memory cell, wherein the voltage values stored in the memory cells are digitalized in succession. In the method according to the invention a local time difference T_loc is determined for each memory cell. By means of a second periodic signal fed into the signal input and stored in all memory cells, which second periodic signal has a known period T2 and and has a linear slope at least in some segments, a recalibration is performed, in which a global time difference T_x,y is determined at least once between a first memory cell S_x and a second memory cell S_y that is not directly adjacent, by means of which global time difference the local time differences T_loc are then iteratively corrected.

Description

METHOD FOR TIMELY CALIBRATING A SWITCHED CONDENSER ARRAY

The present invention relates to a method for calibrating an analog memory array (AMA) with a number (n) of selectively connectable to a signal input memory cells and a control circuit which successively and preferably cyclically controls the memory cells so that each memory cell with a local time interval to the immediately preceding memory cell stores a voltage value of a signal input to the signal input, wherein the voltage values stored in the memory cells are digitized successively in time.

Such analog memory arrays (in English: Analog Memory Array: AMA), which are often referred to as SCA (Switched Capacitor Arrays), are already used in many areas of scientific and industrial application, in which repetitive and especially transient signals must be digitized at high scanning speed. For example, but not exhaustive includes the detection and digitization of output signals from Photomultipliern, gas detectors and semiconductor detectors in particle physics, gamma detectors in positron emission tomography (PET), detectors (also semiconductor detectors) in length measuring systems, cost and technical superior oscilloscopes (by replacing the fast but expensive and inaccurate ADCs).

Classically, such systems use analog to digital converters (in English: Analog-to-Digital Converter: ADCs) with a sampling rate of up to several GHz. However, at such high sampling rates, ADC technology has high power consumption, often insufficient accuracy, and limited channel density. In addition, such ADCs are very expensive.

For example, very costly ADCs are used in oscilloscopes, which typically have only four separate channels for signal acquisition and digitization.

Cheaper, faster and more accurate are AMA based solutions as described in EP 2 045 816 A1, US 5,952,952 A, and by Varner et al., "Large Analog Bandwidth Recorders and Digitizers with Ordered Readout (LABRADOR)" ASIC ", Nuclear Instruments and Methods in Physics, Volume 583, 21 December 2007, pages 447-460.

The basic principle of an AMA-based ADC is to sample an analog signal with a very fast frequency and to store the analog samples corresponding to the sampling points serially on individual memory cells, usually capacitors. The stored voltages are overwritten again and again until sampling is stopped by a trigger signal. The stored voltages then represent a snapshot of the transient signal, that is, a small period of time of the analog signal that is frozen, so to speak. Now, the analog stored voltages representing signal points can be read by a much slower ADC or first transcribed into a buffer and then digitized.

The time intervals at which the stored voltages follow one another in the original analog signal are determined by the sampling frequency at which voltages are stored in successive memory cells. The time length of the stored time segment corresponds to the number of memory cells reduced by one multiplied by the mean value of the time intervals between the memory cells. In other words, the length of the stored time period corresponds to the sum of the time intervals between the memory cells 1 to n.

At a sampling frequency of 1 GHz and 1000 memory cells, the stored signal portion would correspond to a section of the original analog signal of 999 times 1 ns, ie 0.999 μβ.

Frequently, the term "sampling rate" is used instead of "sampling frequency". The sample signal is then not specified in GHz but as GSPS (Giga Sample Per Second) or MSPS (Mega Sample Per Second).

Technologically, neither the time intervals between two successive memory cells nor the sampling frequency are sufficiently constant and accurately known that the time course of the stored signal portion can be determined with an accuracy, as required in particular for the further analysis of very fast transient signals ,

In other words, the time axis of a signal stored in an AMA is neither sufficiently linear nor known with sufficient accuracy. Therefore, the AMA-based ADCs must be calibrated not only with respect to the digitization of the voltage values but also with respect to the time axis and the sampling frequency.

The present invention is concerned with the calibration of the time axis and the sampling frequency. In the following, it is assumed that the voltage calibration has already taken place so that over the used voltage range the stored voltage values can be determined sufficiently accurately and linearly.

The voltage used for the calibration can oscillate about lying at an arbitrary voltage zero axis. Hereinafter, oscillating voltages are considered around a 0-axis zero axis for the sake of simplicity. The usual measures with which such signals are possibly raised in the voltage level, so as not to have to digitize voltage values in the range of 0 volts, are ignored.

A signal oscillating between +1 volt and -1 volt is shifted, for example, in the voltage by +2 volts, so that it oscillates between +3 and +1 volts and thus can be precisely digitized in each time period. The digitized voltage values are then corrected by - 2 volts.

For reasons of clarity, these measures are not mentioned again every time but provided.

An example of the use of an AMA is the DRS4 chip of the Paul Scherrer Institute (PSI), Villigen, Switzerland, which is described in the manual "DRS4 Evaluation Board User's Manual", November 22, 2012, and in the corresponding Datasheet of the PSI, available on the Internet, http://www.psi.ch/drs/documentation DRS is the abbreviation for Domino Ring Sampler.

The DRS4 chip contains 9 channels in which signal sections of an analog signal can be stored at a sampling frequency of up to 5 GHz. In each channel 1024 capacitors with a capacitance of 150 fF are arranged in the ring as memory cells. The memory cells are cyclically rewritten cyclically over a control circuit, so the previously stored voltage values are permanently overwritten. The time intervals between two consecutive memory cells are typically in the range between about 2 and about 0.17 ns, because the sampling frequency f _ab for the signal is between 500 MHz and up to 6 GHz.

In n memory cells are thus permanently the last (n-1) x 1 / f stored _from seconds of the sampled signal, this signal section is permanently updated every 1 / f _from seconds and moves as it were in the ring of memory cells.

The current value to be stored thus migrates in a circle through the memory array, thereby overwriting each case the oldest stored voltage value.

For f _ab = 5 GHz and n = 1024, this means that permanently the last 0.2 [sec of the signal are stored.

In order to digitize the voltage values, the writing is stopped and the contents of the memory cells are loaded into a buffer, preferably a shift register, the signal portion stored at this time is thereby frozen. From this shift register, the voltage values of the signal section are then sequentially read out with a 33 MHz ADC and digitized.

After the stored signal portion has been copied into the shift register, the cyclic writing is resumed.

The sampling frequency is determined by an annular inverter chain, in which an inverter block with two inverters is provided for each memory cell, wherein the each first inverter is designed as an AND gate. The first input of the AND gate is connected to the output of the second inverter in the previous inverter block. Through this self-contained inverter chain wanders a signal wave when applied to the second input of each AND gate, an enable signal.

The speed at which the signal wave travels through the inverter chain depends on the switching time that the individual inverters require to pass a signal change at its input as a signal change at its output.

Between the two inverters in each inverter block, an NMOS transistor is arranged, which operates as a voltage-controlled resistor. This resistor forms, with the parasitic input capacitance of the following inverter, an RC element which serves as a variable delay element for the signal wave traveling through the inverter chain. The output signal of the respective second inverter is used as a write signal for the associated memory cell and opens a corresponding switch which connects the memory cell to the signal input to which the analog signal to be stored and digitized is applied.

By appropriate adjustment of the control voltage for the NMOS transistors so called a domino wave write signal is generated, which moves at a sampling frequency between several 100 MHz and 6 GHz through the inverter chain, with certain AMA sampling frequencies up to 10 GHz to reach.

Due to the component scattering in the inverters and N MOS transistors, the local time intervals between the successive write signals for each two adjacent inverter bell are fixed but not equidistant. This means that a signal applied to the signal input is not sampled equidistantly, but that the signal portion stored in the memory cells is not more linear in the time axis.

Therefore, like any other AMA chip, the DRS4 chip must be calibrated prior to measurement to obtain the correct time positions for all sampled signal values. The DRS4 chips are shipped uncalibrated, but PSI offers an evaluation board for the DRS4 chip and appropriate calibration software to calibrate a DRS4 channel. The board provides a sine wave signal of 240 MHz, which can be stored in one of the channels. From the deviation between the known period of the sinusoidal signal and the period of time determined from the stored waveforms, a calibration table is then calculated which contains for each memory cell an entry which contains the point of the actual time axis of each memory cell. The deviations between the ideal time axis (0 ns, 1 ns, 2ns, 3ns, ...) and the calibrated time axis should be up to 1 ns according to PSI.

At a sampling rate of 2 GSPS, the memory cells should ideally store a voltage value every 0.5 ns. The non-calibrated time axis starting with 0 ns at x = 1 thus contains the time t _x = 50 ns for the memory cell x = 100, while the calibrated time axis for x = 100 has the time t _x = 49 ns, for example.

The time resolution of the DRS4 has in such a calibration depending on the sampling rate on a half-width (FWHM) of the Gaussian distribution of about 50 to 100 ps, as the inventors of the present application could prove in various experiments. The PSI reported in EP 2 045 816 A1 that for a particular experiment a time resolution of less than 100 ps could be achieved.

As the inventors of the present application further noted, the known calibration does not provide a consistent error. If a signal calibrated according to the calibration method proposed by PSI is used to multiply measure two signals which have a certain interval from each other, then the error in determining the time interval depends on the time interval. Different memory cell areas on the DRS4 chip thus provide different errors. These are unfavorable conditions for an experiment, because normally for all measurements for each memory cell area the same error is assumed in order to be able to compare different measurements.

Although the measurement error in the time resolution can be reduced by a correspondingly high number of measurements, but only if always the same (high) error occurs.

In the known calibration method is thus not only the large error in the time resolution, but in particular the not constant over the memory cells error of disadvantage.

The advantages described in connection with the DRS4 chip, possible uses and disadvantages with regard to time resolution, apply analogously to other AMA or SCA-based applications. The invention will be described below by way of example with reference to the DRS4 chip. which in no way should be considered restrictive.

There is therefore a general need for a simple method of the type mentioned, which leads to a higher time resolution.

In the method mentioned in the introduction, this object is achieved according to the invention by a method comprising the following steps: a) for each memory cell, a local time interval T | _0C , wherein a first calibration is preferably carried out with the aid of a first signal which is fed into the signal input and stored in all memory cells and which has a constant gradient at least in sections, in which a local time interval T | _{0C is} detected, b) by means of a second periodic signal fed into the signal input and stored in all memory cells, which has a known periodicity. dendauer T2 and at least partially has a linear slope, there is a recalibration in which at least once between a first memory cell S _x and a not immediately adjacent second memory cell S _y, a global time interval T _{xy is} determined, c) at least some of the in the previous step determined local time intervals T | _0C are corrected using the global time interval T _g i _ob , and d) steps b) and c) are repeated until at least 50% of the local time intervals have been corrected at least once.

The invention thus provides a one- or two-stage calibration method, which requires in a preferred embodiment, only a single ideal periodic signal, such as a sine wave signal whose period must be known very accurately.

According to the inventors, a separate calibration table must be created for each channel of the DRS4 chip, which contains an entry for each memory cell, which contains the actual time interval to the respective previous memory cell.

This time interval will be referred to generally as T | _0C and specifically designated as ΔΤ _Χ , where x denotes the number of the memory cell and ΔΤ _Χ thus the local time interval between the memory cells S _x- i and S _x reproduces.

Using the new method, the errors are below 10 ps FWHM, which corresponds to a standard deviation RMS (root mean square) of less than 4.26 ps. The new calibration is more than a factor of 10 more accurate than the known calibration. Furthermore, the error is no longer dependent on the memory cell area in which a signal section is stored. The time interval between two time-shifted signals can be determined for different time intervals with a comparable Gaussian distribution of the time interval thus measured.

The new method also leads to a more than 10 times lower error, so that the number of measurements with a calibrated according to DRS4 chip according to the invention is lower to achieve a certain standard deviation or half-width, as in a DRS4 chip with known Calibration.

The problem underlying the invention is completely solved in this way.

In the two-stage method, first of all a signal for the first (local) calibration is used in order to determine the time difference T _toc for every two memory cells S _xi and S _x which immediately follow one another in the time sequence.

Local time interval ΔΤ _Χ for a memory cell S _x according to the invention means the time interval to the respective previous memory cell S _x- i. If at the time t _x, the memory cell S _x and the time t _{x + 1,} the memory cell S _{x +} i each of a voltage value stores, then the local time distance for the memory cell x + l calculated according _ΔΤ Χ _{+ 1} = t _{x + 1} - t _x .

For the first local calibration, any signal may be used which must have constant and at least approximately linear slopes. This signal is stored in the memory cells and then digitized. The digitized voltage values of the memory cells in which signal portions corresponding to the rising or falling edges have been stored are used for the determination of T | _0C uses: For each such memory cell S _x , the voltage difference ΔΙΙ _{Χ is} calculated to the immediately preceding memory cell S _x- i. If the number of these memory cells S _{x is} equal to n, that is, x runs from 1 to n, then the correspondence applies:

Σ ΔΙΙ _Χ (x = 1 to n) ^Λ = Σ ΔΤ _Χ (1)

From this, the individual local time intervals T _{x are} calculated as follows:

ΔΤ _Χ · ΣΔΙΙ _Χ = ΔΙΙ _Χ · n / f _ab , (2) where fa _{b is} the sampling frequency, which can be considered as a first approximation to be constant on average.

If necessary, this method is repeated until a ΔΤ _{Χ has been} determined once for each memory cell S _x .

In contrast, in the single-stage method, a T | _0C , from the sampling frequency f _ab given by the manufacturer of the AMA or estimated from the component data according to the relation T | _0C = 1 / fa _b, an identical estimate can be calculated for each memory cell.

For both methods, the estimated or determined in the first stage T | _{0C refined} by means of the second periodic signal, which must have a constant period T2 and at least partially also a linear slope.

In this case, signal sections are stored and digitized in the AMA several times in succession for the same signal.

The digitized voltage values of a signal section can be evaluated immediately and / or temporarily stored for later processing. The method according to the invention therefore provides, in one exemplary embodiment, for firstly digitizing and storing many signal sections before the stored digitized voltage values are used for the calibration.

In another embodiment, the digitized voltage values are used equally for the calibration and possibly only the correction values for the relevant memory cells are stored.

From the digitized voltage values for the relevant signal sections, a global time interval T _g i _ob between two non-adjacent memory cells S _x and S _y is then determined several times and used to iteratively improve the local time intervals.

Step c) is understood to mean that a correction can also lead to a local time interval T | determined in the preceding step _{0C is} not changed because the correction takes place with a correction factor K = 1.

This process is carried out iteratively.

It is preferred if in step c) the local time intervals of the memory cells are corrected, which are assigned to the global time interval T _g i _ob .

Memory cells, which are assigned to a global time interval T _g i _ob , according to the invention means the memory cells between the first memory cell S _x and the last (second) memory cell S _y including the last (second) memory cell S _y . The global time interval T _g i _ob for the memory cells S ₁₀ to S ₂ o are therefore assigned 10 memory cells, namely Sn up to and including S ₂ o, and thus the local time intervals ATn up to and including AT ₂ o.

The local time intervals T _toc for the respective global time interval Tgi _ob associated memory cells are then corrected. Step d) is then to be understood so that either first several global time intervals T _g i _{ob determined} in step b) and then in step c) the local time intervals T | _{0C are} corrected, which are assigned to the multiple global time interval T _g i _ob , or alternately a global time interval T _g i _{ob determined} in step b) and then with the one global time interval T _g i _ob in step c) the local time intervals T | _0C , which are assigned to the one global time interval T _g i _ob .

In this case, it is preferred if the first signal is selected from the group consisting of sawtooth signals, trapezoidal signals, triangular signals and sinusoidal signals.

These signals all have a constant slope, that is, they are used for the rough determination of T | _0C in step a) suitable. The inventors have found that even a clock signal corresponding to a very steep slope keystone signal can be used for step a).

Particularly preferred as the first and second signal, however, a sine wave signal is used, because it is not only very stable and accurate to produce, but also has constant and sufficiently linear edges at the two zero crossings.

In general, it is preferred if the period T2 of the second signal is smaller than the sum of all local time intervals T | _0C , preferably at least 10 times smaller.

Here, it is advantageous that not all memory cells lie within a period of the second signal, so that the same signal sections of the second signal are stored by different memory cells in different measurements.

The shorter the period T2 is, the more zero crossings can be stored in a measurement in the AMA and analyzed, and the faster the calibration can be completed. Further, it is preferred if the global time interval T _g i _whether the period T2 or a multiple (m) corresponds to the period T2 of the second signal.

It is advantageous here that at least one full period of the second signal lies between S _x and S _y , so that the voltages stored in S _x and S _y lie on different edges, which, however, have the same slope direction.

This has the advantage that measurements on flanks of the same slope are evaluated because the inventors have found that rising and falling flanks differ with respect to the time intervals. Between the zero crossing of a rising and a falling edge of a sine signal is not exactly half of T2, while between the zero crossings of slopes of the same slope exactly T2 or a multiple thereof is to be measured. This is due to the waveform.

Furthermore, it is advantageous that the value of the global time interval T _g i _ob is determined exactly, it corresponds to T2 or a multiple (m) of T2.

Generally, it is preferred if the global time interval T _g i _ob using the in the second memory cell S _y and in the first memory cell S _x stored and then digitized voltage value U _x or U _y , the period T2, the local time interval AT _x for the first memory cell S _x and / or the local time interval AT _y for the second memory cell S _y takes place.

In this determination of the global time interval T _g i _{ob, it} is advantageous that the local time intervals T _toc from the estimation, the local calibration or from the global calibration preceding in the iteration are used to obtain a linear interpolation on one or more both "ends" of the global time interval T _g i _ob perform. In the case of interpolation only at S _y or S _{x, it} is also advantageous that only the error of an interpolation is included in the calculation of T _g i _ob .

After T _g i _{ob has} been determined, the associated T | _{0C be} corrected.

A solution of extensive linear systems of equations is therefore not required.

It is preferred if the global time interval for first and second memory cells S _x and S _{y is} determined, the digitized voltage values U _x and U _y within a predetermined voltage interval differ from each other or immediately above a predetermined reference value.

This measure ensures that for the determination of the global time interval T _g i _ob at the two ends at S _x and S _y have stored voltage values which lie approximately on the same area of the different edges of the same slope direction, so that the temporal Distance between S _y and S _{x is} very close to T2 or an integer multiple (m) of T2.

If interpolation takes place only at one end of the global time interval T _g i _ob , preferably at least one of the two voltage values should be close to zero.

It is preferred if the global time interval T _g i _ob using the voltage difference between the stored in the first memory cell S _x and in the immediately preceding memory cell S _x- i voltage value U _x or U _x- i and / or by using the voltage difference between the voltage value U _y or U _{y -i} stored in the second memory cell S _y and in the immediately preceding memory cell S _y- i.

If U _x = U _y , the time interval between S _x and S _{y is} exactly equal to T2 or a multiple (m) of T2. If U _{x is} not equal to U _y , the temporal diverges Distance between S _x and S _y by an At of T2 or a multiple (m) of T2, wherein At is determined by interpolation on the basis of the voltage difference at S _x and / or S _y as follows:

At. (U _y - U _y, i) = _x U _"y AT (3) AT _{x, y} = m · T2 + At, (4) where m = 1, 2, 3, ... is.

It is preferred if in step c) the associated local time intervals T | _{0C are multiplied} by a correction factor K which is the ratio between the respective global time interval AT _xy and the sum of the previously determined local time intervals T | _0C for the global time interval AT _xy associated memory cells S _x to S _y .

K = AT _xy / Σ AT _n (n = x + 1 to y) (5)

AT _xcorr = K * AT _X (6)

In this way, the T | _0C iteratively corrected time and again until they converge towards a final value, which can be recognized by a narrowing Gaussian distribution.

In general, it is preferred if the first and / or the second signal has at least one positive and at least one negative slope with linear slope within a period of time, and preferably in step a), the local time intervals T | _{0C are determined} at least once for the positive edge and at least once for the negative edge, and from the thus determined local time intervals T | _0C for each memory cell S _x an averaged local time interval T | _0C for the respective

Memory cell S _{x is} calculated. Because the determination of T | _0C also depends on the sign of the slope, so a good average is determined, which can be used for both slope directions.

Alternatively, the object underlying the invention in the method mentioned above is achieved by the steps: e) with the aid of at least one fed into the signal input and stored in all memory cells S _x periodic signal, the known period T2 and at least partially a has linear slope, at least one global time interval AT _{xy is determined} between a first memory cell S _x and a not immediately adjacent second memory cell S _y , f) step e) is repeated until k global time intervals AT _xy for different combinations of S _x and S _y and g) from the k determined global time intervals AT _xy , n local time intervals T _{toc are} calculated, making use of the fact that each global time interval AT _xy corresponds to the sum of the local time intervals T _{toc of} the memory cells S _{x +} i to S _y , which are assigned to the respective global time interval AT _xy , preferably e k »n is.

Preferably, step e) is carried out for at least two signals with different period T2, then in each case the global time interval AT _xy determined and from the different measured global time intervals AT _xy a weighted average value is calculated, which is used in step g).

The invention thus also provides a method in which a modification of the global calibration is used. For many signals with different but exactly known period lengths T2 _sig, a large number of global time intervals Tgo _{b are} respectively determined without interpolation at the ends of T _g i _ob . Rather, it will an average is formed by calculating each global time interval T _g i _ob for S _x and S _y from many local time intervals AT _xy for different signals with different period lengths T2 _sig .

For the different signals, the global time intervals AT _x , y may be different, so that averaging takes place.

Here, for example, 40 sine signals with different T2 are each stored and digitized 1000 times, and then the weighted average values are formed for given S _x and S _y .

If, for example, a global time interval ΔΤ _25, 95 of Ta and 10 times a global time interval of Tb were measured for the memory cells S ₂ 5 and S ₉₄ 90 times, then the weighted average is calculated according to:

ΔΤ _{25, 95} = (90 × Ta + 10 × Tb) / 100 (7)

The first memory cell S _x is preferably used in such memory cells in which a voltage value U _{x is} stored, which is immediately before or after a zero crossing, ie before or after a sign change in the stored and digitized signal section, and preferably within one predetermined error distance to the voltage value of the zero crossing.

Preferably, such memory cells are used as second memory cells, in which a voltage value U _{y is} stored, which lies within a predetermined error distance to U _x and on a signal section with the same slope direction.

Between S _x and S _y is then an integer number m of signal periods T2 _sig , this number m of the signal periods T2 _{sig is} determined based on the sign changes that occur between S _x and S _y . Two sign changes each correspond to a signal period T2. The global time interval AT _xy is then equal to m · T2 _sig and equal to the sum of the associated local time intervals AT | _0C .

In this way, many (k) global time intervals T _g i _{ob are determined} for different combinations of two spaced memory cells S _x and S _y . This then solves the following linear equation system with k equations in order to calculate all n local time intervals T | _0C to determine.

AT _{x, y} = AT _X + AT _{X + 1} + AT _{x + 2} +. , , AT _y-2 + AT _y-1 + AT _y = m _{x, y} · T2 _sig

(8th)

ATp _{, q} = AT _P + AT _{P + 1} + AT _{p + 2} +. , , AT _q-2 + AT _q-1 + AT _q = m _pq · T2 _sig

This linear equation system is set up for at least as many different global time intervals T _g i _ob , so that the individual local time intervals T | _0C can be determined.

Since global time intervals must be present for the application of the formula (8), the formulas (5) and (6) could alternatively be applied here if for all T | _{0C is} assumed to correspond to 1 / f _a , or when calculated from previously calculated T | _{0C is} assumed.

The voltage values U _x and U _y used for the determination of T _g i _ob are very close to the calibrated zero line, which is why the determination of T _g i _{ob is} very exact, although not interpolated at the ends of T _g i _ob becomes.

In general, it is preferable if from the sum of the local time intervals T | _0C, a sampling frequency f _{ab is determined} for the control _circuit .

Here is exploited that, although initially worked with the sampling frequency f _from , resulting from the specified by the manufacturer of the AMA or from the the component data estimated sampling frequency f _from yields, but that this sampling is no longer required in the immediately after this determination of all local time intervals T _toc, so that the determined local time intervals are not influenced by the initial value of the sampling frequency f _from.

By the following relationship, the sampling frequency f _{ab can} be determined more accurately than can be taken from the manufacturer's instructions:

Σ ΔΤ _χ / η (x = 1 to n) = 1 / f _ab , (9) where n is the number of memory cells in the AMA.

Since the first memory cell follows immediately after the nth memory cell, ie the memory cells are cyclically described, n and not (n-1) enter into the calculation of f _ab .

The local time intervals T _toc are calibrated with the aid of a measuring and evaluation unit, which stores at least one in which many hundreds of sinusoidal signals are applied to the signal input in the memory cells and then digitized and evaluated according to the method described above the local time intervals T | _0C to calibrate.

Against this background, the present invention also relates to a computer program for carrying out the new method and to a data carrier with an executable version of the computer program.

Due to the large number of required measurements and arithmetic operations, the new method is not performed by hand. The program only has to enter the error distances and possibly the first value for the sampling frequency f _ab . [00114] If the channels of the memory array for a given sampling frequency f were _from calibrated, either the values of the so corrected local time intervals T | _{0C stored} in a data memory, or there are correction values for the local time intervals T | _0C determines and _stores , for example, the deviation from an assumed local time interval T | _0C , which is assumed to be constant for all memory cells.

Against this background, the present invention also relates to an analog memory array having a number (n) of selectively connectable to a signal input memory cells and a control circuit which successively and preferably cyclically the memory cells so that each memory cell with a local time interval T | _{0C stores,} to the immediately preceding memory cell, a voltage _{value of} a signal input to the signal input, the voltage values stored in the memory cells being successively digitized one after the other, and a data memory storing in the new method certain corrected or local time offset values are.

Further advantages will become apparent from the description and the accompanying drawings.

It will be understood that the features mentioned above and those yet to be explained below can be used not only in the particular combination indicated, but also in other combinations or in isolation, without departing from the scope of the present invention.

Embodiments of the invention are illustrated in the accompanying drawings and are explained in more detail in the following description. Show it:

Fig. 1 is a schematic representation of an analog memory array (AMA);

FIG. 2 shows a schematic representation of two inverter blocks from the control circuit for the memory array from FIG. 1; FIG. FIG. 3 shows a schematic representation of a sine signal stored in the memory array, and FIG

Fig. 4 is an enlarged view of the sine signal of Fig. 3, partially in the region of the rising edges.

FIG. 1 schematically shows an analog memory array 10 with, by way of example, nine memory cells 11. In fact, such memory arrays have many hundreds of memory cells 1 1, eg 1024. Each memory cell 1 1 is also referred to below as S _x , where x denotes the number of the memory cell 1 1 in the sequence, ie runs from 1 to 1024.

Each memory cell 1 1 is connected in parallel with a signal input 12 and a signal output 14. Furthermore, each memory cell 1 1 is connected to a shift register 15, in which the stored in the memory cells 1 1 voltages are reloaded in parallel.

From the shift register 15, the voltages are then read out with a clock signal 16 serially with an analog-to-digital converter 17 and digitized there.

The memory array 10 further comprises a control circuit 18 which cyclically and temporally one after the memory cells 1 1 drives so that it stores a voltage of a signal input to the signal input 12 with a local time interval T _toc to the immediately preceding memory cell 1 1.

The memory cells 1 1 are thus cyclically rewritten over the control circuit 18 cyclically with a sampling frequency f _ab , the previously stored voltage values are thus permanently overwritten.

The sampling frequency f _ab is significantly greater than the frequency of the clock signal 16. The sampling frequency f _ab is determined by an annular chain of inverters 19, in which an inverter block 21 with two inverters 19 is provided for each memory cell 1 1, as shown in FIG. 2.

The respective first inverter 19 is designed as an AND gate 22. The first input 23 of the AND gate 22 is connected to the output of the second inverter 19 in the preceding inverter block 22. Through this self-contained inverter chain wanders a signal wave when applied to the second input 24 of each AND gate 22, an enable signal.

The speed at which the signal wave travels through the inverter chain depends on the switching time required by the individual inverters 19 to pass a signal change at their input as a signal change at their output.

Between the two inverters 19 in each inverter block 21, an N MOS transistor 25 is arranged, which operates as a voltage-controlled resistor. This resistor forms, with the parasitic input capacitance of the following inverter, an RC element which serves as a variable delay element for the signal wave traveling through the inverter chain.

At the output of each second inverter 19 in an inverter block 21 so a write signal 27 is generated for the associated memory cell 1 1, which connects the memory cell 1 1 with the signal input 12 to which the analog signal to be stored and digitizing is applied.

By appropriate adjustment of the control voltage for the NMOS transistors, a write signal 27, also referred to as a domino wave, is generated, which travels at a sampling frequency f _ab between a few 100 MHz and several GHz through the inverter chain. The memory array 10 may comprise a plurality of channels, in each of which a number of memory cells 1 1 is arranged, wherein all channels are controlled by the control circuit 18.

Due to the component scattering in the inverters 19 and NMOS transistors 25, the local time intervals T | _0C between the successive write _signals 27 of two adjacent inverter blocks 21, although fixed but not equidistant. This means that a signal applied to the signal input 12 is not sampled equidistantly, but that the signal portion stored in the memory cells 11 is not linear in the time axis.

Therefore, the local time intervals T | _{0C are} calibrated, which takes place with the aid of a measuring and evaluation unit, which _applies a sinusoidal signal 30 to the signal input 12, stored in the memory cells 1 1 and then digitized and evaluated.

3 shows a representation of the digitized voltage values U over the time axis t. 31 denotes the first memory cell 1 1 in the analog memory array 10 and 32 denotes the last memory cell 1 1.

The two memory cells 31 and 32 correspond to the voltage values

Two further memory cells are denoted by 33 and 34, which have respectively stored exactly the rising edge 35 and 36 of the signal 30 in the zero crossing. Between the memory cells 33 and 34, the signal 30 thus has a global time interval T _g i _ob , which corresponds to the period T2 of the signal 30.

If it is assumed that there are a total of 99 further memory cells 1 1 between the memory cells 33 and 34, the signal 30 would be divided into hundreds of voltage values, which in the ideal case would each have an identical local time interval T _toc to the previous voltage value, which would be 1 / 100 of T _g i _ob would amount. For the reasons discussed in detail above, the local ones are

Time intervals T | _0C though firm but not equidistant. This means that the memory cells 33 and 34 are not both exactly in the zero crossing of the edges 35 and 36, respectively. In fact, it is even the case that neither the memory cell 33 nor the memory cell 34 will lie exactly at the zero crossing.

This situation is shown in FIG. 4, where on a greatly enlarged scale two positive edges 35 and 36 of the signal 30 are shown, which at zero crossing to one another have a time interval of T2 or m × T2. Neither the memory cell S _x nor the memory cell S _y are exactly in the zero crossing, but at the positive voltage values U _x and U _y .

[00140] The measurement and evaluation unit now searches the storage cell with the voltage value is on the rising edge closest to the zero crossing, this is the memory cell S _x, because the memory cell S _x i corresponds to a voltage value U _x i, the is absolutely larger than U _x .

Then, the measuring and evaluation unit searches on one of the subsequent rising edge 36, the memory cell with the voltage value that comes closest to the voltage value U _x , that is the memory cell S _y .

In the present case, it is assumed that the edge 36 is spaced from the edge 35 by a period T2. S _y could also lie m period lengths T ₂ away from S _x , which is automatically determined on the basis of the zero crossings of the signal 30 between S _x and S _y .

In order for S _x and S _{y to be} in the linear range of the signal 30, an error range is also specified as a function of the total voltage swing of the signal 30, which is, for example, 120 mV at a voltage swing of 1 volt.

Only within the error range of the zero crossing deviating voltages U _x and only within the error range of the voltage value U _x deviating voltage values U _y are taken into account in the evaluation according to the equation system (8).

Although the global time interval AT _xy between the memory cells S _x and S _y does not exactly correspond to m × T2 (m = 1, 2, 3, 4), the solution of the linear equation system (8) explained above nevertheless leads to the individual T | _0C can be determined with great accuracy.

For this purpose, for example, forty signals 30 are analyzed with different periods T2 each time 1000 times in the above manner, for a memory array 10 with n memory cells 1 1 k »n different global time intervals T _g i _{ob are} determined in the linear system of equations (8).

According to the above equation (7), for the individual global time intervals T _g i _ob previously weighted average values are calculated.

In this way, the inventors were able to calibrate a DRS4 chip with a standard deviation for each T _toc of less than 4.26 ps. The single T | _0C are thereby <100 fs exactly determined. For time measurements with a DRS4 calibrated according to the invention, the time resolution is <4.26 ps for any desired time interval between two ideal signals.

Alternatively, for the situation of FIG. 4, the global time interval between the memory cells S _x and S _{y can also} be determined more accurately.

The voltage value U _x for the memory cell S _x lies between the voltage values U _y- i and U _y for the memory cells S _y- i and S _y . According to the above-explained equation system (3) to (6), the At is determined by linear interpolation by which the global time interval AT _{xy is} larger than m · T2 (m = 1, 2, 3, ...). With this global time interval T _g i _ob , the correction factor K is then determined with which the individual local time intervals T _toc for the memory cells S _x to S _y are corrected by multiplication.

After each determination of a global time interval T _g i _ob , the associated local time intervals T | _0C until they converge to a narrow Gaussian end value.

Before this iteration procedure is performed for the first time, the output values for the local time intervals T | _0C values are set. For this, you can choose from the sampling frequency f _ab specified by the manufacturer of the AMA or from the sampling frequency f _ab according to the relation T | _0C = 1 / f _ab or can be determined by means of the equations (1) and (2) described above.

From the determined by one of the two methods local time intervals T | _0C can then be calculated according to the above equation (9) nor the actual sampling frequency f _ab .

In this way, for each channel of the memory array 10, a set of T | _0C , which _mirrors the actual time axis of the AMA 10 for a given sampling frequency and which is stored in a data memory.

Claims

claims

1 . Method for calibrating an analog memory array (10) having a number (n) of memory cells (1 1) selectively connectable to a signal input (12) and a control circuit (18) which sequentially and preferably cyclically activates the memory cells (1 1) in this way in that each memory cell (11) has a local time interval T | _0C to the immediately preceding memory cell (1 1) stores a voltage _{value of} a signal fed into the signal input (12), wherein the voltage values stored in the memory cells (1 1) are successively digitized in succession, with the steps:

a) for each memory cell is a local time interval T | _0C , wherein a first calibration is preferably carried out with the aid of a first signal which is fed into the signal input and stored in all memory cells and which has a constant gradient at least in sections, in which a local time interval T | _{0C is} determined, b) using a fed into the signal input and stored in all memory cells second periodic signal having a known period T2 and at least partially a linear slope, there is a recalibration in the at least once between a first memory cell S _x and a global time interval T _{xy is} determined from a not immediately adjacent second memory cell S _y , c) at least some of the local time intervals T _i determined in the previous step _0C are corrected using the global time interval T _g i _ob , and d) steps b) and c) are repeated until at least 50% of the local time intervals have been corrected at least once.

2. The method according to claim 1, characterized in that in step c) the local time intervals of the memory cells are corrected, which are assigned to the global time interval.

3. The method of claim 1 or 2, characterized in that the first signal is selected from the group consisting of sawtooth signals, trapezoidal signals, triangular signals and sinusoidal signals.

4. The method according to any one of claims 1 to 3, characterized in that the second signal is the first signal.

5. The method according to any one of claims 1 to 4, characterized in that the period T2 of the second signal is smaller than the sum of all local time intervals Tioc, preferably at least 10 times smaller.

6. The method according to any one of claims 1 to 5, characterized in that the global time interval of the period T2 or a multiple of the period T2 of the second signal corresponds.

7. The method according to any one of claims 1 to 6, characterized in that the global time interval T _g i _ob using the stored in the second memory cell S _y and in the first memory cell S _x and then digitized voltage value U, the period T2, the local time interval ΔΤ _Χ for the first memory cell S _x and / or the local time interval AT _y for the second memory cell S _y takes place.

8. The method according to any one of claims 1 to 7, characterized in that the global time interval for first and second memory cells S _x and S _{y is} determined whose stored voltage values U _x and U _y within a predetermined voltage intervals differ from each other or immediately above a predetermined comparison value lie.

9. The method according to claim 7 or 8, characterized in that the global time interval T _g i _ob using the voltage difference between the stored in the first memory cell S _x and in the immediately preceding memory cell S _x- i voltage U _x or U _{x -} i and / or using the voltage difference between see the stored in the second memory cell S _y and in the immediately preceding memory cell S _y- stored voltage value U _y or U _y- i.

10. The method according to any one of claims 7 to 10, characterized in that in step c) the local time intervals T _toc with the ratio between the respective global time interval AT _{x, y} and the sum of the previously determined local time intervals T | _0C for the global time interval AT _{x, y} associated memory cells S _x to S _{y are} corrected.

1 1. The method according to any one of claims 1 to 10, characterized in that the first and / or the second signal within a period has at least one positive and at least one negative edge with linear slope.

12. The method according to claim 1 1, characterized in that in step a) the local time intervals T | _{0C are determined} at least once for the positive edge and at least once for the negative edge, and from the thus determined local time intervals T | _0C for each memory cell S _x an averaged local time interval T | _{0C is calculated} for the respective memory cell S _x .

13. A method for calibrating an analog memory array (AMA) with a number (n) of selectively connectable to a signal input memory cells and a control circuit which successively and preferably cyclically drives the memory cells so that each memory cell with a local time interval to the immediately preceding Memory cell stores a voltage value of a signal input to the signal input, the voltage values stored in the memory cells are sequentially digitized successively, with the steps: e) using at least one fed into the signal input and stored in all memory cells periodic signal which has a known period T2 and at least partially has a linear slope, at least becomes a global Time interval AT _{xy determined} between a first memory cell S _x and a not immediately adjacent second memory cell S _y , f) step e) is repeated until k global time intervals AT _{x, y} for different combinations of first memory cells S _x and second memory cells S _{y were} determined , and g) from the k specific global time intervals T _xy become n local time intervals T | _0C , making use of each global time interval AT _{x, y of} the sum of the local time intervals T | _{0C of} the memory cells S _{x +} i to S _y , which are associated with the respective global time interval AT _{x, y} .

14. The method according to claim 13, characterized in that step e) is carried out for at least two signals having a different period, in each case T _xy determined and from a weighted average value is calculated, which is used in step g).

15. The method according to claim 13 or 14, characterized in that are used as the first memory cells S _x memory cells in which a voltage value U _{x is} stored, which is immediately before or after a zero crossing, ie before or after a sign change in the stored signal section , preferably within a predetermined error distance to the voltage value of the zero crossing.

16. The method according to any one of claims 13 to 15, characterized in that used as the second memory cells S _y memory cells in which a voltage value U _{y is} stored within a predetermined error distance to the voltage stored in the first memory cell S _x voltage value U _x and lie on a signal section with the same slope direction.

17. The method according to any one of claims 1 to 16, characterized in that from the sum of the local time intervals T _toc a sampling frequency f _{ab is determined} for the control circuit.

18. Computer program for carrying out the method according to one of claims 1 to 17.

19. A data carrier with an executable version of the computer program according to claim 18.

20. Analog memory array (10) having a number (n) of selectively with a signal input (12) connectable memory cells (1 1) and a control circuit (18), the time sequentially and preferably cyclically the memory cells (1 1) controls so that each memory cell (1 1) with a local time interval T | _0C to the immediately preceding memory cell (1 1) stores a voltage _{value of} a signal fed into the signal input (12), wherein the voltage values stored in the memory cells (1 1) are digitized successively in time, and with a data memory in which according to the method one or more of the claims 1 to 16 are stored for the local time intervals.