EP2883430B1 - Leiterplattenanordnung und verfahren zur herstellung einer elektrischen verbindung an einer leiterplatte - Google Patents

Leiterplattenanordnung und verfahren zur herstellung einer elektrischen verbindung an einer leiterplatte Download PDF

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Publication number
EP2883430B1
EP2883430B1 EP12882879.5A EP12882879A EP2883430B1 EP 2883430 B1 EP2883430 B1 EP 2883430B1 EP 12882879 A EP12882879 A EP 12882879A EP 2883430 B1 EP2883430 B1 EP 2883430B1
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EP
European Patent Office
Prior art keywords
ball
printed circuit
circuit board
passage
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP12882879.5A
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English (en)
French (fr)
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EP2883430A1 (de
EP2883430A4 (de
Inventor
Igor PEREZ-URIA
Per Ferm
Benny Gustafson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
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Publication of EP2883430A4 publication Critical patent/EP2883430A4/de
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0242—Shape of an individual particle
    • H05K2201/0248—Needles or elongated particles; Elongated cluster of chemically bonded particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0305—Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09572—Solder filled plated through-hole in the final product
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10234—Metallic balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
    • H05K2201/1075—Shape details
    • H05K2201/10878—Means for retention of a lead in a hole
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
    • H05K2201/10886—Other details
    • H05K2201/10916—Terminals having auxiliary metallic piece, e.g. for soldering
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0338—Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0455—PTH for surface mount device [SMD], e.g. wherein solder flows through the PTH during mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3494—Heating methods for reflowing of solder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.

Definitions

  • the present invention relates to printed circuit boards. More particularly, the invention relates to a printed circuit board arrangement and a method for forming electrical connection at a printed circuit board.
  • Power conversion technology is heading towards higher current density and power while at the same time minimizing. Accordingly, interconnection channels between host board and devices are slimmed to fit miniaturization product demands.
  • Harsh application environments (outdoor enclosures or application with limited forced convection) demands optimal thermal design integrity/minimal losses in the power distribution.
  • US 6 913 187 describes a method of providing thermal vias in a printed circuit board.
  • One or more holes are provided in the printed circuit board.
  • a metal ball is inserted to each hole and subjected to pressure such as to deform the ball and tightly fixating the resultant slug against the wall of the hole.
  • the deformed ball or slug fixed in the hole functions to conduct heat and/or electricity between a metallized top side and bottom side of the printed circuit board.
  • Ball grid array Electronic devices, such as integrated circuit chips, are commonly attached to a substrate or printed circuit card with ball connecters using a ball grid array (BGA) connection technique.
  • BGA ball grid array
  • Using the ball grid array usually involves attachment of an array of balls located on the underside of an electronic device to a corresponding array of contact pads located on a surface of a substrate, using individual solder joints.
  • solder joints It is known in the art to use copper plated and/or polymer-plated and/or lead free solder spheres in for example ball grid arrays or 3D packaging applications.
  • Solder copper balls placed between host board and device's signal/power source provide an effective/low ohmic interconnection channel.
  • US 6252779 discloses a method for joining electronic devices such as integrated circuits to vias in a substrate.
  • the method involves providing a substrate have a conductive opening therein and securely positioning an electrically conductive member within the conductive opening to plug the conductive opening.
  • JP 2006179519 A seems to disclose a method used to manufacture a printed board using a board wherein a through-hole is formed with a conductive covering film on its inner circumferential surface. At least a spherical conductor of which diameter is larger than that of the through hole and wherein the surface of a metallic ball is covered with a solder film, is pressed into the through hole, and then the solder is melted, thus filling the through hole therewith.
  • One object of the invention is to improve the prior art with respect to current transfer between layers of printed circuit boards.
  • a printed circuit board arrangement as defined by claim 1 is provided.
  • One advantage with the present invention is that the electrical connection provides for a reinforced current transfer between layers of the printed circuit board.
  • the currents transferred between layers of a printed circuit board can be increased with maintained or increased package size.
  • Existing limitations in the currents which can be transferred by means of the walls of the passage between the conductive layers of the printed circuit board is remedied by means of the second path passing the at least one first ball.
  • the electrical connection between the layers is low ohmic. This provides for low power losses and consequently the need for dissipating heat from the connection is less than in conventional connections between layers. Thus, the electrical transfer between layers can be achieved while keeping stress due to temperature limits within acceptable levels.
  • the use of the at least one first ball for the second path is cost effective.
  • the cost for producing the balls having high conductivity is low.
  • the mounting of the electrical connection comprising the at least one first ball is of low complexity and consequently cost effective.
  • the at least one first ball has an electrical conductivity ⁇ higher than 3 ⁇ 10 7 S/m at 20°.
  • the high conductivity of the at least one first ball secures the low resistance of the second path.
  • the first ball comprises in one example copper or a copper alloy.
  • the electrically conductive material formed on the walls is in low ohmic or low resistance contact with the surface of the at least one first ball.
  • an electrical path between the wall and at least one first ball forms part of the second electrical path between the first and second conductive layers of the printed circuit board.
  • the passage is filled or partially filled with solder.
  • the solder provides for the low ohmic or low resistance contact between the wall and the at least one first ball.
  • the printed circuit board arrangement comprises a second ball centered against an opening of the passage at the first and/or second side.
  • Each second ball has a diameter larger than the diameter of the passage and is electrically conducting.
  • the second ball can be used for communication of data and or for power transfer between the printed circuit board and other electrical equipment electrically connected to the second ball.
  • the second ball can also be used for dissipating heat from the printed circuit board.
  • the second ball closes the opening to the passage.
  • each second ball is soldered to its associated surface. Thus, the opening to the passage is closed by means of soldering.
  • At least one electrical device is electrically connected to the printed circuit board by means of the second ball(s).
  • the other electrical device may be a main board or motherboard.
  • the second ball may be centered in an opening formed in the other electrical device so as to provide electrical contact with the other electrical device.
  • the step of filling the passage comprises filling the passage with the plurality of first balls so that the passage completely encloses the first balls. Thereby the first balls form a substantial part of the second path.
  • the method further comprises the steps of providing an electrically conducting second ball having a diameter larger than the diameter of the passage and self centering the second ball against an opening of the passage at the first side of the printed circuit board.
  • the method has the step of filling the passage with the at least one first ball and thereafter inserting solder in the passage so as to at least partly fill the passage with the solder.
  • the method further comprises the steps of providing another electrically conducting second ball having a diameter larger than the diameter of the passage and self centering that second ball against the passage opening at the second side of the printed circuit board.
  • Each second ball may be fixed to the associated surface for example by means of solder.
  • Adjacent balls, first and/or second balls, may be fixed to each other for example by means of solder or etching.
  • the method comprises further a step of providing electrical contact between the second ball and an electrical conductor of another electrical device.
  • the providing of the electrical contact may comprise centering the second ball in an opening formed in the electrical device.
  • a printed circuit board arrangement 100 comprises a printed circuit board 110.
  • the printed circuit board 110 has a first side 111 and a second side 112.
  • An electrical connection 113 electrically connects a first conductive layer 117 and a second conductive layer 117 of the printed circuit board.
  • the respective first and second layers are arranged to transfer power and/or communication signals.
  • the respective first and second layers may also be arranged to transfer heat.
  • the layers may be formed as conductive patterns having one or a plurality of conductive lines and/or conductive areas.
  • the first and second layers are in one example metalized.
  • the metalized first and second layers comprise in one example copper or a copper alloy.
  • the first and second layers are formed on the first and second sides, respectively.
  • the electrical connection 113 comprises a passage 116 extending from an opening 119 in one of the sides 111, 112 of the printed circuit board 110 through the printed circuit board between the first and second layers.
  • the passage is formed as a straight or oblique cylinder.
  • the passage is shaped as a truncated cone.
  • the cylinder/cone may have a circular cross section.
  • the passage extends perpendicularly in relation to the printed circuit board sides.
  • the passage 116 only partly penetrates the printed circuit board (a blind via).
  • the passage 116 extends between an opening in each respective side of the printed circuit board forming a through hole.
  • Electrically conducting material 114 is formed on the wall 115 of the passage. This electrically conducting material forms a first path electrically connecting the first conductive layer 117 with the second conductive layer 117.
  • the wall of the passage is completely or partly plated with the electrically conductive material. The thickness of the conductive material formed on the walls of the passage sets the limit for the current level which it is possible to transfer by means of the first electrical path between the first and second layers.
  • the conductive material formed on the wall comprise in one example copper or a copper alloy.
  • the passage 116 encloses at least one first ball 120.
  • the at least one first ball 120 is electrically conducting.
  • the at least one first ball forms part of a second electrical path between the first and second conductive layers of the printed circuit board.
  • the second electrical path has a lower resistance than the first path.
  • the first ball has an electrical conductivity a higher than 3 ⁇ 107 S/m at 20° C.
  • the at least one first ball may comprise copper or a copper alloy.
  • the electrical conductivity is then characteristically 93-96% IACS.
  • the at least one first ball is solid.
  • a surface 121 of the first ball(s) is in one example plated with plating material. The plating may be present so as to avoid corrosion.
  • the plating material comprises in one example tin, silver, nickel, or gold or a combination of some of these metals.
  • the surface of the first balls treated with other solderability protectant e.g. OSP.
  • the at least one first ball has a size which is equal to or smaller than the length and diameter of the passage.
  • First balls of different shapes may be used.
  • at least some of the first balls are in one example sphere shaped.
  • Other first ball(s) may be of other shapes such as cylinder shaped.
  • at least some of the first ball(s) have one or a plurality of grooves and/or notches and/or channels formed therein. Thereby outgassing, ventilation and/or wetting can be improved.
  • the first balls may be selected so as to harmonize with a desired current and/or load.
  • the size, shape and/or electrical conductivity of the at least one ball can be selected so as to harmonize against a desired current and/or load in the electrical connection.
  • first balls of different sizes, shapes and/or electrical conductivity can be used so as to harmonize with the desired current/load. If more than one first ball is used, the first ball(s) 120 are in low ohmic or low resistance contact with each other. In one example, the first balls are in direct physical contact with each other.
  • the first ball(s) 120 is in low ohmic or low resistance contact with the first and second layers, as discussed above. Further, the first ball is in one example in low ohmic or low resistance contact with the electrically conductive material formed on the wall 115. According to the invention, the passage is filled or partially filled with solder 118 so as to achieve this low ohmic/resistance contact between first ball(s) and the wall.
  • the solder material comprises tin (Sn) or a tin alloy.
  • a printed circuit board arrangement 200 comprises a printed circuit board 210, as discussed in relation to Figure 1 .
  • the printed circuit board 210 has a first side 211 and a second side 212.
  • An electrical connection 213 electrically connects at least a first conductive layer 217 and a second conductive layer 217 of the printed circuit board.
  • layers are formed on the surface of each side of the printed circuit board. Further, layers are also formed integrated within the printed circuit board. At least one of the layers integrated within the surface board extend into electrical contact with the passage wall.
  • the electrical connection 213 comprises a passage 216 extending from an opening in one of the sides of the printed circuit board 210 through the printed circuit board between the at least first and second layers.
  • the passage 216 extends between an opening in each respective side of the printed circuit board forming a through hole.
  • electrically conducting material 214 is formed on the wall 215 of the passage. This electrically conducting material forms a first path electrically connecting the at least first and second conductive layers 217.
  • the passage 216 encloses at least one first ball 220, as discussed in relation to Figure 1 .
  • a second ball 230 is centered against an opening of the passage 216 at the first and/or second side.
  • a second ball 230 is centered against an opening of the passage at both sides of the printed circuit board.
  • Each second ball has a diameter larger than the size of the opening to the passage.
  • Each second ball 230 is electrically conducting.
  • the at least one second ball may form part of the second electrical path between the at least first and second conductive layers of the printed circuit board, as discussed in relation to Figure 1 .
  • the each second ball has an electrical conductivity ⁇ higher than 3 ⁇ 10 7 S/m at 20°C.
  • Each second ball may comprise copper or a copper alloy. The electrical conductivity is then characteristically 93-96 IACS.
  • each second ball is solid.
  • a surface 221 of each second ball is in one example plated with plating material. The plating may be present so as to avoid corrosion.
  • the plating material comprises in one example tin, silver, nickel, palladium or gold or a combination of some of these metals.
  • each second ball(s) may have one or a plurality of grooves and/or notches and/or channels formed therein. Thereby outgassing, ventilation and/or wetting can be secured.
  • Each second ball 230 is in one example soldered 232 to its associated surface 211 212 of the printed circuit board.
  • the printed circuit board arrangement 200 provides for an efficient thermo transport from the printed circuit board and especially the electrical connection 213 to the environment by means of the second ball(s).
  • the second ball(s) 230 form part of a third electrical path between any of the layers 217 and other equipment electrically connected to the second ball(s).
  • the third electrical path is arranged to transfer electrical power and/or electrical signals.
  • a printed circuit board arrangement 400 comprises a printed circuit board 410.
  • the printed circuit board 410 has a first side 411 and a second side 412 and an electrical connection 413 electrically connecting a first conductive layer 417 and a second conductive layer 417 of the printed circuit board.
  • the electrical connection 413 comprises a passage 416 extending from an opening 419 in one of the sides of the printed circuit board 410 through the printed circuit board between the first and second layers.
  • electrically conducting material 414 is formed on the wall 415 of the passage. This electrically conducting material forms a first path electrically connecting the first and second conductive layers 417.
  • the passage 416 encloses a plurality of balls 220, as discussed in relation to Figures 1 and 2 .
  • a second ball 430 is centered against an opening in the passage 416 at the second side 412.
  • the second ball 430 has a diameter larger than the size of the opening to the passage.
  • the second ball 430 is electrically conducting. It may form part of the second electrical path between the first and second conductive layers of the printed circuit board, as discussed in relation to Figures 1 and 2 .
  • a surface 421 of the second ball is in one example plated with solderable plating material.
  • the second ball(s) 430 form part of a third electrical path between any of the layers 417 and another electrical device 440 electrically connected to the second ball.
  • the third electrical path is arranged to transfer electrical power and/or electrical signals between the printed circuit board and the other electrical device 440.
  • the third electrical path is in one example also arranged to transfer heat between the printed circuit board and the other electrical device 440.
  • the other electrical device 440 is for example a main board or a motherboard.
  • the second ball 430 is centered in an opening 436 formed in the other electrical device so as to provide electrical contact with the other electrical device 440.
  • This arrangement wherein a plurality of printed circuit boards and/or electrical devices can be mounted on each other by means of the second ball centered in an opening of the respective printed circuit board/electrical device have many advantages. For example, it provides for a predetermined and consistent standoff height between the printed circuit boards and/or electrical devices. Further, it provides for design flexibility as the arrangement allows for selecting the size of the second ball relatively freely as long as the second balls does not fit into the passage 416. Therefore the size of the second ball can be selected to fit with a desired standoff height.
  • a plurality of first balls 320 and optionally also a second ball 330 forms a tower of balls for insertion in the passage. Adjacent balls are fixed to each other in fixing points 322 for example by means of etching. Alternatively, the balls are fixed to each other by means of soldering to a carrier 323.
  • a method 500 for forming an electrical connection at a printed circuit board comprises the following steps.
  • At least one passage is provided 510 in the printed circuit board extending from an opening in one side of the printed circuit board through the printed circuit board between a first conductive layer and a second conductive layer of the printed circuit board.
  • the walls of the passage is provided 520 with an electrically conducting material so as to electrically connect the first and second conducting layers of the printed circuit board by means of a first electrical path.
  • At least one electrically conducting first ball is provided 530.
  • the at least one first ball has a diameter which is equal to or smaller than the length and diameter of the passage.
  • the at least one first ball is filled 540 in the passage.
  • a second electrical path is provided for electrically connecting the first and second conducting layers, wherein the second electrical path has a lower resistance than the first path.
  • the step of filling 540 the passage comprises filling the passage with the plurality of first balls so that the passage completely encloses the first balls.
  • a method 600 for forming an electrical connection at a printed circuit board comprises the above described steps of providing 610 at least one passage in the printed circuit board, providing 615 the walls of the passage with an electrically conducting material, providing 620 at least one electrically conducting first ball and filling 645 the at least one first ball in the passage.
  • the method 600 comprises in one example also the steps of providing 625 an electrically conducting second ball having a diameter larger than the diameter of the passage and centering or self centering 635 the second ball against an opening of the passage at the first side of the printed circuit board.
  • the second ball may be fixed 640 to the surface of the printed circuit board for example by means of soldering.
  • first balls and optionally also the second ball are fixed 630 to each other before being filled 645 in the passage.
  • first balls and optionally also the second ball are etched to each other into a tower of balls of a desired design.
  • the first balls and optionally also the second ball are soldered to a carrier so as to provide to the tower of balls having a desired design.
  • solder is inserted 650 in the passage so as to at least partly fill the passage with the solder.
  • the second ball is first centered 635 and fixed 640 to the surface of the printed circuit board from one side of the printed circuit board, whereupon the first ball(s) are filled from the other, non-plugged side of the printed circuit board.
  • the method steps may be peformed in another order.
  • the first balls may be filled 645 in the passage from the non-plugged side
  • the solder may inserted 650 in the passage from the non-plugged side and thereafter the second ball is centered 635 and fixed 640 against the passage opening from the non-plugged side of the printed circuit board.
  • the passage When the passage is filled, it is on one example closed by providing 655 another electrically conducting second ball having a diameter larger than the diameter of the passage and self centering 660 that second ball against the passage opening at the second side of the printed circuit board. Also this other second ball may be fixed 665 to its associated surface for example by means of soldering.
  • the method may further comprise a step of providing 670 electrical contact between the second ball and an electrical conductor of another electrical device.
  • the providing 670 of the electrical contact may comprise centering the second ball in an opening formed in the electrical device.
  • the method comprises a one or a plurality of heating steps 675.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Combinations Of Printed Boards (AREA)

Claims (13)

  1. Leiterplattenanordnung (100; 200; 400), umfassend:
    eine Leiterplatte (110; 210; 410) mit einer ersten Seite (111; 211; 411) und einer zweiten Seite (112; 212; 412) und einer elektrischen Verbindung (113; 213; 413), die eine erste leitende Schicht (117; 217; 417) und eine zweite leitende Schicht (117; 217; 417) der Leiterplatte (110; 210; 410) elektrisch verbindet, wobei die elektrische Verbindung (113; 213; 413) umfasst:
    einen Durchgang (116; 216; 416) der sich durch die Leiterplatte (110; 210; 410) von der ersten Seite (111; 211; 411) zur zweiten Seite (112; 212; 412) der Leiterplatte (110; 210; 410) zwischen der ersten leitenden Schicht (117; 217; 417) und der zweiten leitenden Schicht (117; 217; 417) erstreckt, wobei elektrisch leitendes Material (114; 214; 414) auf Wänden (115; 215; 415) des Durchgangs (116; 216; 416) ausgebildet ist, wobei das elektrisch leitende Material (114; 214; 414) einen ersten Pfad bildet, der die erste leitende Schicht (117; 217; 417) mit der zweiten leitenden Schicht (117; 217; 417) elektrisch verbindet, und
    mindestens eine erste Kugel (120; 220; 420), die von dem Durchgang (116; 216; 416) umschlossen ist, wobei die mindestens eine erste Kugel (120; 220; 420) elektrisch leitend ist, wobei die mindestens eine erste Kugel (120; 220; 420) einen Durchmesser aufweist, der gleich oder kleiner als die Länge und der Durchmesser des Durchgangs (116; 216; 416) ist, wobei der Durchgang mit Lot gefüllt oder teilweise gefüllt ist, um einen niederohmigen Kontakt/Kontakt mit geringem Widerstand zwischen der mindestens einen ersten Kugel und der Wand zu erreichen;
    wobei die mindestens eine erste Kugel (120; 220; 420) einen Teil eines zweiten elektrischen Pfades zwischen der ersten leitenden Schicht (117; 217; 417) und der zweiten leitenden Schicht (117; 217; 417) der Leiterplatte (110; 210; 410) bildet, wobei der zweite elektrische Pfad einen niedrigeren Widerstand als der erste Pfad aufweist,
    dadurch gekennzeichnet, dass die mindestens eine erste Kugel (120; 220; 420) eine oder eine Mehrzahl von Rillen, Kerben und/oder Kanälen zur Verbesserung der Ausgasung, Belüftung und/oder Benetzung aufweist.
  2. Leiterplattenanordnung (100; 200; 400) nach Anspruch 1, wobei die mindestens eine erste Kugel (120; 220; 420) eine elektrische Leitfähigkeit σ von mehr als 3x107 S/m bei 20 °C aufweist.
  3. Leiterplattenanordnung (100; 200; 400) nach einem der vorhergehenden Ansprüche, wobei die erste Kugel (120; 220; 420) Kupfer oder eine Kupferlegierung umfasst.
  4. Leiterplattenanordnung (100; 200; 400) nach einem der vorhergehenden Ansprüche, umfassend eine elektrisch leitende zweite Kugel (230; 430), die gegen eine Öffnung (119; 419) des Durchgangs (116; 216; 416) auf der ersten Seite (111; 211; 411) und/oder der zweiten Seite (112; 212; 412) zentriert ist, wobei jede zweite Kugel (230; 430) einen Durchmesser aufweist, der größer als der Durchmesser des Durchgangs (116; 416) ist.
  5. Leiterplattenanordnung (100; 200; 400) nach Anspruch 4, wobei jede zweite Kugel (230; 430) mit ihrer zugeordneten Oberfläche (211, 212; 411, 412) verlötet (232; 432) ist.
  6. Leiterplattenanordnung (100; 200; 400) nach einem der Ansprüche 4 oder 5, wobei ein weitere elektrische Vorrichtung (440) mittels der/den zweiten Kugel(n) (230; 430) mit der Leiterplatte (110; 210; 410) elektrisch verbunden ist.
  7. Leiterplattenanordnung (100; 200; 400) nach Anspruch 6, wobei die andere elektrische Vorrichtung (440) eine Hauptplatine oder ein Motherboard ist.
  8. Leiterplattenanordnung (100; 200; 400) nach Anspruch 6 oder 7, wobei die zweite Kugel (430) in einer in der anderen elektrischen Vorrichtung (440) ausgebildeten Öffnung (436) zentriert ist, um einen elektrischen Kontakt mit der anderen elektrischen Vorrichtung (440) bereitzustellen.
  9. Verfahren (500; 600) zum Herstellen einer elektrischen Verbindung an einer Leiterplatte, wobei das Verfahren (500; 600) umfasst:
    - Bereitstellen (510; 610) mindestens eines Durchgangs, der sich durch die Leiterplatte von einer ersten Seite zu einer zweiten Seite der Leiterplatte zwischen einer ersten leitenden Schicht auf der ersten Seite und einer zweiten leitenden Schicht auf der zweiten Seite erstreckt;
    Bereitstellen (520; 615) eines elektrisch leitenden Materials an den Wänden des Durchgangs, um die erste leitende Schicht und die zweite leitende Schicht der Leiterplatte mittels eines ersten elektrischen Pfades elektrisch zu verbinden,
    Bereitstellen (530; 620) mindestens einer elektrisch leitenden ersten Kugel mit einem Durchmesser, der gleich oder kleiner ist als die Länge und der Durchmesser des Durchgangs,
    - Füllen (540; 645) des Durchgangs mit der mindestens einen ersten Kugel und anschließendes Einführen von Lot in den Durchgang, um den Durchgang zumindest teilweise mit dem Lot zu füllen, wobei die mindestens eine erste Kugel eine oder eine Mehrzahl von Rillen, Kerben und/oder Kanälen zur Verbesserung der Ausgasung, Belüftung und/oder Benetzung aufweist,
    Durchführen eines oder einer Mehrzahl von Erwärmungsschritten, wodurch ein zweiter elektrischer Pfad zum elektrischen Verbinden der ersten leitenden Schicht und der zweiten leitenden Schicht bereitgestellt wird, wobei der zweite elektrische Pfad einen niedrigeren Widerstand als der erste Pfad aufweist.
  10. Verfahren nach Anspruch 9, wobei der Durchgang mit der mindestens einen ersten Kugel so gefüllt wird, dass der Durchgang die mindestens eine erste Kugel vollständig umschließt.
  11. Verfahren nach einem der Ansprüche 9 oder 10, umfassend die Schritte des Bereitstellens (625) einer elektrisch leitenden zweiten Kugel mit einem Durchmesser, der größer als der Durchmesser des Durchgangs ist, und des Selbstzentrierens (635) der zweiten Kugel gegen eine Öffnung des Durchgangs auf der ersten Seite der Leiterplatte.
  12. Verfahren nach Anspruch 11, ferner umfassend die Schritte des Bereitstellens (655) einer weiteren elektrisch leitenden zweiten Kugel mit einem Durchmesser, der größer als der Durchmesser des Durchgangs ist, und des Selbstzentrierens (660) dieser zweiten Kugel gegen die Durchgangsöffnung an der zweiten Seite der gedruckten Schaltungsplatte.
  13. Verfahren nach einem der Ansprüche 10-12, umfassend die Schritte des Bereitstellens einer elektrisch leitenden zweiten Kugel mit einem Durchmesser, der größer ist als der Durchmesser des Durchgangs, des Selbstzentrierens der zweiten Kugel, benachbart zu der mindestens einen erste Kugel, gegen die Durchgangsöffnung an der zweiten Seite der Leiterplatte, und Befestigen der mindestens einen ersten Kugel und der zweiten Kugel aneinander (630), beispielsweise mittels Löten oder Ätzen.
EP12882879.5A 2012-08-10 2012-08-10 Leiterplattenanordnung und verfahren zur herstellung einer elektrischen verbindung an einer leiterplatte Active EP2883430B1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SE2012/050868 WO2014025298A1 (en) 2012-08-10 2012-08-10 A printed circuit board arrangement and a method for forming electrical connection at a printed circuit board

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EP2883430A1 EP2883430A1 (de) 2015-06-17
EP2883430A4 EP2883430A4 (de) 2016-05-11
EP2883430B1 true EP2883430B1 (de) 2022-10-05

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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017009922A1 (ja) * 2015-07-13 2017-01-19 富士機械製造株式会社 配線形成方法および配線形成装置
DE102020101906A1 (de) * 2020-01-27 2021-07-29 Röchling Automotive SE & Co. KG Kanalbauteil für ein Kraftfahrzeug mit bedarfsgerecht dimensionierten integrierten elektrischen Leitungen
US10999938B1 (en) * 2020-04-29 2021-05-04 Raytheon Company Method of wire bonding a first and second circuit card
CN113677093B (zh) * 2021-08-11 2022-07-22 维沃移动通信有限公司 电路板组件、电路板堆叠结构及电子设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3148310A (en) * 1964-09-08 Methods of making same
JP2006179519A (ja) * 2004-12-20 2006-07-06 Sony Corp プリント基板、同プリント基板の製造方法、及び同製造装置
WO2012170625A1 (en) * 2011-06-09 2012-12-13 Tessera, Inc. Low-stress tsv design using conductive particles

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ZA804558B (en) 1979-08-18 1981-09-30 Int Computers Ltd Multilayer circuit structures
US5401911A (en) * 1992-04-03 1995-03-28 International Business Machines Corporation Via and pad structure for thermoplastic substrates and method and apparatus for forming the same
JP3057924B2 (ja) * 1992-09-22 2000-07-04 松下電器産業株式会社 両面プリント基板およびその製造方法
CA2154409C (en) * 1994-07-22 1999-12-14 Yuzo Shimada Connecting member and a connecting method using the same
KR100271656B1 (ko) * 1998-05-30 2000-11-15 김영환 비지에이 반도체 패키지 및 그 제조방법
US6252779B1 (en) 1999-01-25 2001-06-26 International Business Machines Corporation Ball grid array via structure
JP4467721B2 (ja) * 2000-06-26 2010-05-26 富士通マイクロエレクトロニクス株式会社 コンタクタ及びコンタクタを使用した試験方法
SE520174C2 (sv) * 2000-12-29 2003-06-03 Ericsson Telefon Ab L M Förfarande och anordning för anordnande av vior i mönsterkort
US20060272850A1 (en) * 2005-06-06 2006-12-07 Matsushita Electric Industrial Co., Ltd. Interlayer connection conductor and manufacturing method thereof
US20110278725A1 (en) * 2007-01-31 2011-11-17 Nichepac Technology Inc. Stacking of transfer carriers with aperture arrays as interconnection joints
JP4904242B2 (ja) * 2007-10-12 2012-03-28 新光電気工業株式会社 配線基板及びその製造方法
JP2009141297A (ja) * 2007-12-11 2009-06-25 Panasonic Corp 多層配線板およびその製造方法
DE102009028744A1 (de) * 2009-08-20 2011-03-31 Semikron Elektronik Gmbh & Co. Kg Verfahren zur Herstellung einer elektrischen Verbindung zwischen Leiterplatten

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3148310A (en) * 1964-09-08 Methods of making same
JP2006179519A (ja) * 2004-12-20 2006-07-06 Sony Corp プリント基板、同プリント基板の製造方法、及び同製造装置
WO2012170625A1 (en) * 2011-06-09 2012-12-13 Tessera, Inc. Low-stress tsv design using conductive particles
EP2718968A1 (de) * 2011-06-09 2014-04-16 Tessera, Inc. Spannungsarmer tsv-entwurf mit leitfähigen partikeln

Also Published As

Publication number Publication date
CN104521332A (zh) 2015-04-15
EP2883430A1 (de) 2015-06-17
EP2883430A4 (de) 2016-05-11
WO2014025298A1 (en) 2014-02-13
US20150208506A1 (en) 2015-07-23

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