EP2812912A2 - Connection arrangement of an electric and/or electronic component - Google Patents

Connection arrangement of an electric and/or electronic component

Info

Publication number
EP2812912A2
EP2812912A2 EP13702765.2A EP13702765A EP2812912A2 EP 2812912 A2 EP2812912 A2 EP 2812912A2 EP 13702765 A EP13702765 A EP 13702765A EP 2812912 A2 EP2812912 A2 EP 2812912A2
Authority
EP
European Patent Office
Prior art keywords
layer
connection
solder
electronic component
electrical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP13702765.2A
Other languages
German (de)
French (fr)
Inventor
Christiane FRUEH
Andreas Fix
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP2812912A2 publication Critical patent/EP2812912A2/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/19—Soldering, e.g. brazing, or unsoldering taking account of the properties of the materials to be soldered
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B23K35/0244—Powders, particles or spheres; Preforms made therefrom
    • B23K35/025—Pastes, creams, slurries
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/30—Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
    • B23K35/3006—Ag as the principal constituent
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Definitions

  • the invention relates to a connection arrangement of at least one electrical and / or electronic component with a joining partner, a composite element and a method for forming the
  • a base part e.g. Substrate or the like
  • the fixing of the electrical components is effected, for example, by a connecting layer, such as e.g. an adhesive, solder or sintered layer.
  • a connecting layer such as e.g. an adhesive, solder or sintered layer. Due to the difference between room, joining and operating temperature, the stiffness of the connecting layer and the greatly different expansion coefficients of, for example, IC and substrate, however, very high mechanical or thermo-mechanical stresses can arise in the electronic components. This can lead to a so-called "shell fracture" on the electronic component, in particular in the case of thermal loads, in which partial areas of the surface of the electronic component are broken off. This can lead to very short life of such electronic
  • Compound layer and the electronic component can already degrade in the enclosed by the round recesses area of the substrate.
  • the introduction of the dimples is an additional manufacturing step to
  • the arrangement described in this way is completely coated together with the bonding connections from the outside with a metal oxide film (SnO, AIO).
  • the thus coated assembly is further encapsulated by a polymeric material.
  • the metal oxide coating causes a stress reduction for the semiconductor chip.
  • Such a coating is expensive because it has to be applied over the entire assembly.
  • the application of the coating on the arrangement as a spatial structure is very complicated and difficult.
  • only methods can be used in which the areas adjacent to the arrangement can be omitted before such a coating.
  • the invention is based on the object to form a connection arrangement of an electrical and / or electronic component such that the component, in particular a semiconductor chip, temperature change resistant during operation, in particular within a circuit arrangement of a motor vehicle, can be used.
  • connection arrangement of at least one electrical and / or electronic component and by a
  • connection arrangement comprises at least one electrical and / or electronic component.
  • the at least one electrical and / or electronic component has at least one connection surface, which is connected in a material-locking manner by means of a connection layer to a joining partner.
  • the bonding layer may be, for example, an adhesive, solder, weld, sintered compound or other known compound which
  • connection arrangement Characteristic of the connection arrangement according to the invention is that a reinforcing layer is arranged cohesively adjacent to the connection layer.
  • the reinforcing layer has a higher one for this purpose
  • connection layer Elastic modulus, as the connecting layer.
  • the reinforcing layer accordingly prevents supercritical expansion of the connecting layer or of the at least one electrical and / or electronic component connected to the connecting layer.
  • a particularly large protective effect is given by the fact that the reinforcing layer is formed like a frame by an outer and an inner boundary and surrounds at least with its outer boundary, the connection surface of the at least one electrical and / or electronic component.
  • Frame-like in this context means in particular that the
  • Reinforcing layer by its outer and / or its inner boundary at least in one plane, in particular in a substantially parallel plane to the connection surface of the at least one electrical and / or electronic component, closed circumferential course.
  • the outer and / or inner boundary preferably extend substantially parallel to the outer contour of the connection surface.
  • the connection surface can also have a circular, oval or otherwise different base surface. It is particularly advantageous if the reinforcing layer is designed to be interruption-free. In this manner, different dimensions of the at least one electrical and / or electronic component, the connection layer and the joining partner, for example a carrier substrate, can be applied to them
  • connection layer can be prevented.
  • the reinforcing layer acts through the frame-like formation like a stiff belt, which can absorb forces, but does not allow deformations.
  • connection layer a
  • the reinforcement layer is arranged in this area region on the connection layer. It is particularly advantageous if the reinforcing layer arranged on this surface area extends with its inner boundary at least to the connection surface of the at least one electrical and / or electronic component. Furthermore, it is advantageous if, in this arrangement, the reinforcing layer is formed at least in regions such that the reinforcing layer additionally surrounds a housing of the at least one electrical and / or electronic component, at least over a minimum height.
  • the reinforcing layer limits the lateral extent of the connecting layer with its inner boundary.
  • the inner boundary of the reinforcing layer encloses the
  • Connecting layer at least partially or preferably completely over their
  • a partial limitation over the layer thickness of the connecting layer can be embodied, for example, such that the reinforcing layer is arranged adjacent to the connecting layer on the joining partner and has a lower layer thickness than the one
  • Connection layer to be arranged at least partially spatially integrated.
  • the side of the reinforcing layer pointing in the direction of the connecting surface of the at least one electrical and / or electronic component and / or the side of the reinforcing layer facing in the direction of the joining partner is at least partially, preferably completely, remote from the
  • Connection layer arranged reinforcing layer given improved possibility, both the vulnerable edge region of the pad and the housing of the at least one electrical and / or electronic
  • connection arrangement provides that the inner boundary of the reinforcing layer extends at least partially - preferably completely - to within the connection area of the at least one electrical and / or electronic component.
  • connection surface in the overlapping region is connected in a materially bonded manner to the reinforcement layer.
  • edge region of the connecting surface of the at least one electrical and / or electronic component is fixed directly to the reinforcing layer, so that the expansion possibilities of the Total construction element on the low expansion possibility of
  • Reinforcing layer are limited. As a result, the risk of crack formation and propagation within the component is maximally reduced.
  • the reinforcing layer is preferably dependent on the selected
  • connection layer For example, care must be taken that a cohesive connection can be formed between the connection layer and the reinforcement layer and preferably also between the connection surface of the at least one electrical and / or electronic component and / or the joining partner.
  • a cohesive connection can be formed between the connection layer and the reinforcement layer and preferably also between the connection surface of the at least one electrical and / or electronic component and / or the joining partner.
  • the connecting layer and the joining partner are absorbed by the reinforcing layer.
  • care must furthermore be taken that the reinforcing layer has a greater modulus of elasticity than the connecting layer.
  • connection arrangement provides a reinforcing layer, which comprises at least one intermetallic phase.
  • Intermetallic phases have a large covalent
  • a preferred connection arrangement according to the invention has a
  • Connecting layer which comprises at least one metal, for example a metallic sintered compound, in particular of silver.
  • the reinforcing layer is formed from a solder material, in particular a tin, bismuth, zinc, gallium or aluminum-based solder material, wherein after a temperature treatment of the bonding layer and / or the solder material, the reinforcing layer comprises or at least one intermetallic phase at least one metallic phase is formed and thus completely replaces the previous solder material.
  • the connecting layer for example embodied as a sintered shaped part
  • the solder layer in the form of a
  • connection arrangement is formed, which is then arranged to form the connection arrangement according to the invention between the at least one electrical and / or electronic component and the joining partner.
  • the solder layer is embodied like a frame within the composite element and arranged on the connection layer and / or arranged adjacent to the connection layer such that its inner boundary limits the lateral surface extent of the connection layer.
  • Connecting arrangement can be prepared in advance. Furthermore, ease of handling and placement are comparable to any electrical and / or electronic component.
  • the temperature treatment is preferably oriented according to the required solder profile. Overall, therefore, a very simple and cost-effective way is given, a temperature-resistant intermetallic phase by conventional
  • connection arrangement is particularly suitable for semiconductor components, for example made of silicon, in particular with a flat pad, for example IGBT, MOSFET, DIODEN and semiconductor chip.
  • Such components are fastened by means of the connection layer, for example on a DBC substrate (direct copper bonded), a metal stamped grid, an organic or ceramic circuit carrier or an IMS substrate (insulated metal substrates) as a joining partner.
  • the bonding layer in particular as a sintered layer, preferably has a layer thickness of 10 to 500 ⁇ m, in particular 10 to 300 ⁇ m, particularly preferably 10 to 100 ⁇ m.
  • the reinforcing layer may be in their
  • Layer thickness similar to the connection layer are performed. If a solder layer is selected as reinforcement layer, which in particular is replaced by a temperature treatment by at least one intermetallic phase should, smaller layer thicknesses are preferred, for example, 0.5 to 100 .mu.m, in particular 0.5 to 60 .mu.m, more preferably 1 pm to 30 pm.
  • connecting materials may be used which, among other things, allow the use of the formed connection assembly at high operating temperatures.
  • FIG. 1a shows schematically a first embodiment of the connection arrangement according to the invention in a side view
  • FIG. 1 b schematically the embodiment of FIG. La in a plan view
  • FIG. 2a shows a schematic representation of a second embodiment of the connection arrangement according to the invention in a side view
  • FIG. 2b shows schematically a third embodiment of the connection arrangement according to the invention in a side view
  • FIG. 2c shows schematically a fourth embodiment of the connection arrangement according to the invention in a side view.
  • connection arrangement 100 a circuit substrate 40, for example a DBC substrate, is provided.
  • a semiconductor chip 10 is materially connected to the DBC substrate.
  • the semiconductor chip 10 faces on the DBC substrate 40
  • connection surface 11 is used for example for electrical contacting of the semiconductor chip 10 and / or for the heat dissipation. For cohesive connection is between the
  • a sintered layer 20 made of silver can be in the form of a paste, for example, and can be applied to the DBC substrate 40 by means of known paste printing methods.
  • the sintered layer 20 may be formed as a sintered molded part and in the then firmly present and to the
  • Pad 11 adapted form are placed on the DBC substrate 40.
  • the sintered layer 20 is formed such that one of the pad 11 facing upper
  • Surface region 21 protrudes beyond the connection surface 11 of the semiconductor chip 10. As can be seen in the plan view in FIG. 1b, this surface region 21 projects generally on the side of the semiconductor chip 10. Furthermore, a tin-based solder layer 30 - for example made of this area region 21
  • solder layer 30 with an inner
  • the inner boundary 35 of the solder layer 30 extends as far as the connection area 11. Furthermore, the housing of the semiconductor chip 10 is surrounded by the solder layer 20 at the level of the layer thickness s.
  • the arrangement thus formed, in particular the sintered layer 20 and / or the solder layer 30, is heat-treated.
  • the temperature treatment is preferably carried out in the region of the melting temperature of the solder layer 30.
  • Boundary areas i. within the area 21, and form a
  • Reinforcing layer 30 ' comprising at least one intermetallic phase, from.
  • Ag3Sn forms as an intermetallic phase.
  • SnCu0.7 as solder material
  • both Ag3Sn and Cu6Sn5 form as intermetallic phases.
  • the solder layer 30 very thin with, for example, 50 ⁇ m, the metals and / or metal alloys of both layers 20, 30 can diffuse very far into the solder layer 30 during the temperature treatment.
  • a duration of the temperature treatment is selected, in which the solder layer 30 is substantially replaced by the formed at least one intermetallic phase and in this way the total
  • FIGS. 2a-2c show further exemplary embodiments of the invention
  • solder layer 30 is laterally adjacent to
  • Sintered layer 20 is applied to the DBC substrate.
  • the reinforcing layer 30 'formed after the temperature treatment bonds with both the sintered layer 20 and the DBC substrate.
  • the inner boundary 35 limits the lateral surface extent of the sintered layer 20.
  • Connecting arrangement 300 corresponding to FIG. 2b is similar to the second one Embodiment.
  • the sintered layer 20 in the third embodiment is made substantially flush with the connection surface 11 or the housing of the semiconductor chip 10.
  • the solder layer 30 is formed in its layer thickness at least in the region of the housing of the semiconductor chip 10 such that at least a minimum height of
  • Temperature treatment is then surrounded by the reinforcing layer 30 'on the other side.
  • the solder layer 30 is integrated within the sintered layer 20.
  • the side of the solder layer 30 facing the connection surface 11 ends flush with the sinter layer 20, which at least over the layer thickness s of the solder layer 30 through the inner layer
  • Limitation 35 is limited. Furthermore, the side of the solder layer 30 facing away from the connection surface is covered by the sintering layer 20. After the temperature treatment, the formed reinforcing layer 30 'integrally bonds both to the sintered layer 20 and to the surface area reaching into the connecting surface 11.
  • solder layer can in principle only after the formation of the cohesive connection of the electrical and / or electronic
  • Component such as the semiconductor chip 10, with the joining partner, for example, with the DBC substrate 40, applied and / or arranged.
  • solder layer 30 to the sintered layer 20 in the form of a
  • solder layer 30 Sinter molding or the lateral placement of the solder layer 30 adjacent to the connection layer 20 such that the solder layer 30 with its inner
  • Limiting 35 limits the lateral surface extent of the connection layer 20, can also already before the formation of the connection assembly 100, 200, 300, 400 carried out to form a composite element.
  • the composite element is arranged between the at least one electrical and / or electronic component, for example the semiconductor chip 10, and the joining partner, for example the DBC substrate, and then the temperature treatment for forming the reinforcing layer 30 'is carried out.
  • connection layer 20 may be a solder layer, for example, a tin, bismuth, zinc, gallium or aluminum-based soft solder.
  • the reinforcing layer 30 ' may be formed from a metal layer, in particular tin, silver, copper, zinc, bismuth, gallium and / or aluminum, which is applied, for example, by a chemical and / or physical coating process.
  • materials for the connection layer 20 and the reinforcement layer 30 ' may be selected such that, due to a temperature treatment and the diffusion processes occurring between the two layers 20, 30, the reinforcement layer 30' comprises at least one intermetallic phase.

Abstract

The connection arrangement (100, 200, 300, 400) comprises at least one electric and/or electronic component (1). The at least one electric and/or electronic component (10) has at least one connection face (11), which is connected in a bonded manner to a join partner (40) by means of a connection layer (20). The connection layer (20) can for example be an adhesive, soldered, welded, sintered connection or another known connection that connects joining partners while forming a material connection. Furthermore, a reinforcement layer (30') is arranged adjacent to the connection layer (20) in a bonded manner. The reinforcement layer (30') has a higher modulus of elasticity than the connection layer (20). A particularly good protective effect is achieved if the reinforcement layer (30') is formed in a frame-like manner by an outer and an inner boundary (36, 35) and, at least with the outer boundary (36) thereof, encloses the connection face (11) of the at least one electric and/or electronic component (10).

Description

Titel  title
Verbindungsanordnung eines elektrischen und/oder elektronischen Bauelements  Connecting arrangement of an electrical and / or electronic component
Die Erfindung betrifft eine Verbindungsanordnung mindestens eines elektrischen und/oder elektronischen Bauelements mit einem Fügepartner, ein Verbundelement und ein Verfahren zur Ausbildung der The invention relates to a connection arrangement of at least one electrical and / or electronic component with a joining partner, a composite element and a method for forming the
Verbindungsanordnung gemäß dem Oberbegriff der unabhängigen Ansprüche. Connecting arrangement according to the preamble of the independent claims.
Stand der Technik State of the art
In vielen Bereichen der Technik werden elektronische Bauelemente, wie z.B. integrierte Schaltkreise (IC), Transistoren oder Dioden, innerhalb elektrischer Schaltungsanordnungen eingesetzt. Hierbei werden verschiedenste In many fields of technology, electronic components, such as e.g. integrated circuits (IC), transistors or diodes, used within electrical circuit arrangements. Here are various
elektronische Bauelemente auf einem Basisteil, z.B. Substrat oder Ähnlichem, fixiert. Das Fixieren der elektrischen Bauelemente erfolgt beispielsweise durch eine Verbindungsschicht, wie z.B. eine Klebe-, Lot- oder Sinterschicht. Durch den Unterschied zwischen Raum-, Füge- und Betriebstemperatur, der Steifigkeit der Verbindungsschicht und der stark unterschiedlichen Ausdehnungskoeffizienten von zum Beispiel IC und Substrat, können jedoch sehr hohe mechanische bzw. thermomechanische Spannungen in den elektronischen Bauelementen entstehen. Dadurch kann es insbesondere bei thermischen Belastungen zu einem sogenannten "Muschelbruch" am elektronischen Bauteil kommen, bei dem Teilbereiche der Oberfläche des elektronischen Bauelements herausgebrochen werden. Dies kann zu sehr kurzer Lebensdauer derartiger elektronischer electronic components on a base part, e.g. Substrate or the like, fixed. The fixing of the electrical components is effected, for example, by a connecting layer, such as e.g. an adhesive, solder or sintered layer. Due to the difference between room, joining and operating temperature, the stiffness of the connecting layer and the greatly different expansion coefficients of, for example, IC and substrate, however, very high mechanical or thermo-mechanical stresses can arise in the electronic components. This can lead to a so-called "shell fracture" on the electronic component, in particular in the case of thermal loads, in which partial areas of the surface of the electronic component are broken off. This can lead to very short life of such electronic
Baugruppen führen. Guide assemblies.
Um die Entstehung von mechanischen Spannungen innerhalb des To the emergence of mechanical stresses within the
elektronischen Bauelements zu reduzieren, ist es bekannt, um den Bereich des fixierten elektronischen Bauelements runde Vertiefungen, sogenannte Dimpels, in die Substratoberfläche einzubringen. Durch die runden Vertiefungen wird das Substrat in diesem Bereich elastischer, so dass sich mechanische Spannungen infolge unterschiedlicher Ausdehnungskoeffizienten des Substrats, der To reduce the electronic component, it is known to introduce the area of the fixed electronic component round recesses, called dimples, in the substrate surface. Due to the round recesses, the substrate becomes more elastic in this area, so that mechanical stresses due to different coefficients of expansion of the substrate, the
Verbindungsschicht und des elektronischen Bauelements bereits in dem von den runden Vertiefungen umschlossenen Bereich des Substrates abbauen können. Das Einbringen der Dimpels ist ein zusätzlicher Fertigungsschritt zur Compound layer and the electronic component can already degrade in the enclosed by the round recesses area of the substrate. The introduction of the dimples is an additional manufacturing step to
Bereitstellung des Substrates. Provision of the substrate.
Aus der Offenlegungsschrift US 2010/0187678 AI ist eine Anordnung eines Halbleiterchips auf einem Metallsubstrat bekannt. Dabei ist der Halbleiterchip durch Sintern einer Silberpaste bei niedrigem Druck auf dem Metallsubstrat befestigt. Ferner weist der Halbleiterchip Bondverbindungen auf, die den From the publication US 2010/0187678 AI an arrangement of a semiconductor chip on a metal substrate is known. In this case, the semiconductor chip is fixed by sintering a silver paste at low pressure on the metal substrate. Furthermore, the semiconductor chip has bonding connections, which the
Halbleiterchip mit Kontaktierungsstellen verbinden. Die derart beschriebene Anordnung wird zusammen mit den Bondverbindungen von außen mit einem Metalloxidfilm (SnO, AIO) vollständig beschichtet. Die auf diese Weise beschichtete Anordnung ist weiterhin durch ein Polymermaterial eingekapselt. Die Metalloxidbeschichtung bewirkt eine Stressreduktion für den Halbleiterchip. Eine derartige Beschichtung ist teuer, da sie über die ganze Anordnung aufgetragen werden muss. Ferner ist das Aufbringen der Beschichtung auf der Anordnung als räumliches Gebilde sehr aufwendig und schwierig. Des Weiteren können nur Verfahren verwendet werden, bei welchen die zur Anordnung benachbarten Bereiche vor einer derartigen Beschichtung ausgelassen werden können. Connect semiconductor chip to contact points. The arrangement described in this way is completely coated together with the bonding connections from the outside with a metal oxide film (SnO, AIO). The thus coated assembly is further encapsulated by a polymeric material. The metal oxide coating causes a stress reduction for the semiconductor chip. Such a coating is expensive because it has to be applied over the entire assembly. Furthermore, the application of the coating on the arrangement as a spatial structure is very complicated and difficult. Furthermore, only methods can be used in which the areas adjacent to the arrangement can be omitted before such a coating.
Offenbarung der Erfindung Disclosure of the invention
Vorteile advantages
Der Erfindung liegt die Aufgabe zu Grunde, eine Verbindungsanordnung eines elektrischen und/oder elektronischen Bauelementes derart auszubilden, dass das Bauelement, insbesondere ein Halbleiterchip, temperaturwechselfest im Betrieb, insbesondere innerhalb einer Schaltungsanordnung eines Kraftfahrzeuges, eingesetzt werden kann. The invention is based on the object to form a connection arrangement of an electrical and / or electronic component such that the component, in particular a semiconductor chip, temperature change resistant during operation, in particular within a circuit arrangement of a motor vehicle, can be used.
Ferner ist es Aufgabe, ein Verfahren zur Ausbildung einer derartigen It is also an object, a method for forming such
Verbindungsanordnung anzugeben. Specify connection arrangement.
Diese Aufgaben werden durch eine Verbindungsanordnung mindestens eines elektrischen und/oder elektronischen Bauelements, ferner durch ein These objects are achieved by a connection arrangement of at least one electrical and / or electronic component, and by a
Verbundelement zur Ausbildung der Verbindungsanordnung sowie durch ein Verfahren zur Herstellung desselben gemäß den kennzeichnenden Merkmalen der unabhängigen Ansprüche gelöst. Composite element for forming the connection arrangement and by a A method for producing the same according to the characterizing features of the independent claims solved.
Die Verbindungsanordnung umfasst mindestens ein elektrisches und/oder elektronisches Bauelement. Das mindestens eine elektrische und/oder elektronische Bauelement weist mindestens eine Anschlussfläche auf, welche mittels einer Verbindungsschicht mit einem Fügepartner stoffschlüssig verbunden ist. Die Verbindungsschicht kann beispielsweise eine Klebe-, Lot-, Schweiß-, Sinterverbindung oder eine andere bekannte Verbindung sein, welche The connection arrangement comprises at least one electrical and / or electronic component. The at least one electrical and / or electronic component has at least one connection surface, which is connected in a material-locking manner by means of a connection layer to a joining partner. The bonding layer may be, for example, an adhesive, solder, weld, sintered compound or other known compound which
Fügepartner unter Ausbildung eines Stoffschlusses verbindet. Joining joint partner forming a fabric bond.
Kennzeichnend für die erfindungsgemäße Verbindungsanordnung ist, dass angrenzend zur Verbindungsschicht stoffschlüssig eine Verstärkungsschicht angeordnet ist. Die Verstärkungsschicht weist hierfür einen höheren Characteristic of the connection arrangement according to the invention is that a reinforcing layer is arranged cohesively adjacent to the connection layer. The reinforcing layer has a higher one for this purpose
Elastizitätsmodul auf, als die Verbindungsschicht. Auf diese Weise kann in vorteilhafter Weise der Rissbildung in der Verbindungsschicht vorgebeugt werden, welche bei ansonst bekannten Verbindungsanordnungen auf Grund von mechanischen und/oder thermomechanischen Spannungen, insbesondere bei betriebsbedingten Temperaturwechsel, entsteht. Die Wirkung ist darin begründet, dass ein Material mit einem hohen Elastizitätsmodul einer Materialverformung einen hohen Widerstand entgegenbringen kann. Die Verstärkungsschicht verhindert demnach eine überkritische Ausdehnung der Verbindungsschicht oder des mindestens einen mit der Verbindungsschicht verbundenen elektrischen und/oder elektronischen Bauelements. Eine besonders große Schutzwirkung ist dadurch gegeben, wenn die Verstärkungsschicht durch eine äußere und eine innere Begrenzung rahmenartig ausgebildet ist und zumindest mit ihrer äußeren Begrenzung die Anschlussfläche des mindesten einen elektrischen und/oder elektronischen Bauelements umschließt. Rahmenartig bedeutet in diesem Zusammenhang insbesondere, dass dieElastic modulus, as the connecting layer. In this way, crack formation in the connection layer can advantageously be prevented, which arises in otherwise known connection arrangements due to mechanical and / or thermomechanical stresses, in particular during operational temperature changes. The effect is due to the fact that a material with a high modulus of elasticity can provide a high resistance to material deformation. The reinforcing layer accordingly prevents supercritical expansion of the connecting layer or of the at least one electrical and / or electronic component connected to the connecting layer. A particularly large protective effect is given by the fact that the reinforcing layer is formed like a frame by an outer and an inner boundary and surrounds at least with its outer boundary, the connection surface of the at least one electrical and / or electronic component. Frame-like in this context means in particular that the
Verstärkungsschicht durch ihre äußere und/oder ihre innere Begrenzung einen zumindest in einer Ebene, insbesondere in einer im Wesentlichen parallelen Ebene zur Anschlussfläche des mindestens einen elektrischen und/oder elektronischen Bauelements, geschlossenen umlaufenden Verlauf aufweist. Die äußere und/oder innere Begrenzung verlaufen bevorzugt im Wesentlichen parallel zur Außenkontur der Anschlussfläche. Die Anschlussfläche kann neben einer quadratischen oder rechteckigen Grundfläche auch eine kreisförmige, ovale oder auch anders geartete Grundfläche aufweisen. Besonders vorteilhaft ist es, wenn die Verstärkungsschicht unterbrechungsfrei ausgeführt ist. Auf diese Weise können an für sich unterschiedliche Ausdehnungen des zumindest einen elektrischen und/oder elektronischen Bauelements, der Verbindungsschicht und des Fügepartners, beispielsweise einem Trägersubstrat, durch die Reinforcing layer by its outer and / or its inner boundary at least in one plane, in particular in a substantially parallel plane to the connection surface of the at least one electrical and / or electronic component, closed circumferential course. The outer and / or inner boundary preferably extend substantially parallel to the outer contour of the connection surface. In addition to a square or rectangular base area, the connection surface can also have a circular, oval or otherwise different base surface. It is particularly advantageous if the reinforcing layer is designed to be interruption-free. In this manner, different dimensions of the at least one electrical and / or electronic component, the connection layer and the joining partner, for example a carrier substrate, can be applied to them
Verbindungsschicht unterbunden werden. Die Verstärkungsschicht wirkt durch die rahmenartige Ausbildung wie ein steifer Gürtel, welcher Kräfte aufnehmen kann, dabei aber keine Verformungen zulässt. Connection layer can be prevented. The reinforcing layer acts through the frame-like formation like a stiff belt, which can absorb forces, but does not allow deformations.
Durch die in den abhängigen Ansprüchen aufgeführten Maßnahmen sind vorteilhafte Weiterbildungen und Verbesserungen der erfindungsgemäßen Verbindungsanordnung möglich. The measures listed in the dependent claims advantageous refinements and improvements of the connection arrangement according to the invention are possible.
Eine vorteilhafte Ausführungsform der erfindungsgemäßen An advantageous embodiment of the invention
Verbindungsanordnung sieht vor, dass die Verbindungsschicht einen Connection arrangement provides that the connection layer a
Flächenbereich aufweist, welcher über die Anschlussfläche des mindestens einen elektrischen und/oder elektronischen Bauelements hinausragt. In vorteilhafter Weise wird die Verstärkungsschicht in diesem Flächenbereich auf der Verbindungsschicht angeordnet. Besonders vorteilhaft ist es, wenn die auf diesem Flächenbereich angeordnete Verstärkungsschicht mit ihrer inneren Begrenzung mindestens bis zur Anschlussfläche des zumindest einen elektrischen und/oder elektronischen Bauelements reicht. Weiterhin ist vorteilhaft, wenn in dieser Anordnung die Verstärkungsschicht zumindest bereichsweise derart ausgebildet ist, dass die Verstärkungsschicht zusätzlich zumindest über eine Mindesthöhe ein Gehäuse des zumindest einen elektrischen und/oder elektronischen Bauelements umsäumt. Has surface area, which protrudes beyond the connection surface of the at least one electrical and / or electronic component. Advantageously, the reinforcement layer is arranged in this area region on the connection layer. It is particularly advantageous if the reinforcing layer arranged on this surface area extends with its inner boundary at least to the connection surface of the at least one electrical and / or electronic component. Furthermore, it is advantageous if, in this arrangement, the reinforcing layer is formed at least in regions such that the reinforcing layer additionally surrounds a housing of the at least one electrical and / or electronic component, at least over a minimum height.
Insgesamt ist dadurch sowohl der gefährdete Randbereich der Anschlussfläche als auch des Gehäuses des zumindest einen elektrischen und/oder  Overall, this makes both the endangered edge region of the connection surface and the housing of the at least one electrical and / or
elektronischen Bauelements vor einer Risseinleitung und/oder Rissausbreitung, beispielsweise infolge betriebsbedingter Temperaturwechsel, wirkungsvoll geschützt. Bei einer alternativen oder weiterführenden Ausführungsform der electronic component against crack initiation and / or crack propagation, for example due to operational temperature changes, effectively protected. In an alternative or further embodiment of the
erfindungsgemäßen Verbindungsanordnung begrenzt die Verstärkungsschicht mit ihrer inneren Begrenzung die seitliche Ausdehnung der Verbindungsschicht. Hierbei umschließt die innere Begrenzung der Verstärkungsschicht die According to the invention, the reinforcing layer limits the lateral extent of the connecting layer with its inner boundary. Here, the inner boundary of the reinforcing layer encloses the
Verbindungsschicht zumindest teilweise oder bevorzugt vollständig über ihreConnecting layer at least partially or preferably completely over their
Schichtstärke hinweg. Eine teilweise Begrenzung über die Schichtstärke der Verbindungsschicht kann beispielsweise derart ausgeführt sein, dass die Verstärkungsschicht angrenzend zur Verbindungsschicht auf dem Fügepartner angeordnet ist und in der Schichtstärke geringer ausgeführt ist als die Layer thickness away. A partial limitation over the layer thickness of the connecting layer can be embodied, for example, such that the reinforcing layer is arranged adjacent to the connecting layer on the joining partner and has a lower layer thickness than the one
Verbindungsschicht. Weiterhin kann die Verstärkungsschicht innerhalb derLink layer. Furthermore, the reinforcing layer within the
Verbindungsschicht zumindest teilweise räumlich integriert angeordnet sein. Hierbei ist beispielsweise die in Richtung der Anschlussfläche des zumindest einen elektrischen und/oder elektronischen Bauteils weisende Seite der Verstärkungsschicht und/oder die in Richtung des Fügepartners weisende Seite der Verstärkungsschicht zumindest teilweise, bevorzugt vollständig, von derConnection layer to be arranged at least partially spatially integrated. In this case, for example, the side of the reinforcing layer pointing in the direction of the connecting surface of the at least one electrical and / or electronic component and / or the side of the reinforcing layer facing in the direction of the joining partner is at least partially, preferably completely, remote from the
Verbindungsschicht überdeckt. Connection layer covered.
Insgesamt ist dadurch eine weitere und in Kombination mit der auf der  Overall, this is another and in combination with the on the
Verbindungsschicht angeordneten Verstärkungsschicht verbesserte Möglichkeit gegeben, sowohl den gefährdeten Randbereich der Anschlussfläche als auch des Gehäuses des zumindest einen elektrischen und/oder elektronischenConnection layer arranged reinforcing layer given improved possibility, both the vulnerable edge region of the pad and the housing of the at least one electrical and / or electronic
Bauelements vor einer Risseinleitung und/oder Rissausbreitung wirkungsvoll zu schützen. Component to protect against crack initiation and / or crack propagation effectively.
Eine vorteilhafte Weiterbildung der erfindungsgemäßen Verbindungsanordnung sieht vor, dass die innere Begrenzung der Verstärkungsschicht zumindest teilsweise - bevorzugt vollständig - bis innerhalb der Anschlussfläche des mindestens einen elektrischen und/oder elektronischen Bauelements reicht. In diesem Fall weist die in Richtung der Anschlussfläche des zumindest einen elektrischen und/oder elektronischen Bauelements weisende Seite der An advantageous development of the connection arrangement according to the invention provides that the inner boundary of the reinforcing layer extends at least partially - preferably completely - to within the connection area of the at least one electrical and / or electronic component. In this case, the pointing in the direction of the pad of the at least one electrical and / or electronic device side of the
Verstärkungsschicht und die Anschlussfläche selbst einen überlappendenReinforcement layer and the pad itself an overlapping
Flächenbereich auf. Besonders vorteilhaft ist es, wenn die Anschlussfläche in dem überlappenden Bereich mit der Verstärkungsschicht stoffschlüssig verbunden ist. Auf diese Weise ist der Randbereich der Anschlussfläche des zumindest einen elektrischen und/oder elektronischen Bauelements unmittelbar an der Verstärkungsschicht fixiert, so dass die Ausdehnungsmöglichkeiten des Bauelements insgesamt auf die geringe Ausdehnungsmöglichkeit der Surface area. It is particularly advantageous if the connection surface in the overlapping region is connected in a materially bonded manner to the reinforcement layer. In this way, the edge region of the connecting surface of the at least one electrical and / or electronic component is fixed directly to the reinforcing layer, so that the expansion possibilities of the Total construction element on the low expansion possibility of
Verstärkungsschicht begrenzt sind. Dadurch ist das Risiko einer Rissbildung und -ausbreitung innerhalb des Bauelements maximal reduziert. Die Verstärkungsschicht ist bevorzugt in Abhängigkeit der gewählten Reinforcing layer are limited. As a result, the risk of crack formation and propagation within the component is maximally reduced. The reinforcing layer is preferably dependent on the selected
Verbindungsschicht auszuwählen. So ist beispielsweise darauf zu achten, dass zwischen der Verbindungsschicht und der Verstärkungsschicht und bevorzugt auch zwischen der Anschlussfläche des zumindest einen elektrischen und/oder elektronischen Bauelements und/oder dem Fügepartner eine stoffschlüssige Verbindung ausbildbar ist. Dadurch können beispielsweise mechanische und/oder thermomechanische Spannungen, die durch das unterschiedliche Ausdehnungsverhalten des zumindest einen elektrischen und/oder  Select connection layer. Thus, for example, care must be taken that a cohesive connection can be formed between the connection layer and the reinforcement layer and preferably also between the connection surface of the at least one electrical and / or electronic component and / or the joining partner. As a result, for example, mechanical and / or thermo-mechanical stresses caused by the different expansion behavior of the at least one electrical and / or
elektronischen Bauelements, der Verbindungsschicht und dem Fügepartner durch die Verstärkungsschicht aufgenommen werden. Hierzu ist weiterhin darauf zu achten, dass die Verstärkungsschicht einen größeren Elastizitätsmodul aufweist als die Verbindungsschicht. electronic component, the connecting layer and the joining partner are absorbed by the reinforcing layer. For this purpose, care must furthermore be taken that the reinforcing layer has a greater modulus of elasticity than the connecting layer.
Eine vorteilhafte Weiterbildung der erfindungsgemäßen Verbindungsanordnung sieht eine Verstärkungsschicht vor, welche mindestens eine intermetallische Phase umfasst. Intermetallische Phasen weisen einen großen kovalentenAn advantageous development of the connection arrangement according to the invention provides a reinforcing layer, which comprises at least one intermetallic phase. Intermetallic phases have a large covalent
Bindungsanteil auf. Dies führt zu einem großen Elastizitätsmodul und hoher Schmelz- bzw. Zersetzungstemperatur, beispielsweise größer 250°C, vor allem 300°C und mehr. Dies ist insbesondere dann vorteilhaft, wenn die Binding share on. This leads to a high elastic modulus and high melting or decomposition temperature, for example greater than 250 ° C, especially 300 ° C and more. This is particularly advantageous if the
Verbindungsanordnung beim Fügen des zumindest einen elektrischen und/oder elektronischen Bauelements mit dem Fügepartner oder im Betrieb hohenConnecting arrangement when joining the at least one electrical and / or electronic component with the joining partner or in operation high
Temperaturen ausgesetzt ist. Auf diese Weise kann die Zuverlässigkeit der Verbindungsanordnung auch bei hohen Temperaturen sichergestellt werden. Is exposed to temperatures. In this way, the reliability of the connection arrangement can be ensured even at high temperatures.
Eine bevorzugte erfindungsgemäße Verbindungsanordnung weist eine A preferred connection arrangement according to the invention has a
Verbindungsschicht auf, welche mindestens ein Metall umfasst, beispielsweise eine metallische Sinterverbindung, insbesondere aus Silber. Ferner ist die Verstärkungsschicht aus einem Lotmaterial gebildet, insbesondere einem Zinn-, Wismut-, Zink-, Gallium- oder Alluminiumbasierten Lotmaterial, wobei nach einer Temperaturbehandlung der Verbindungsschicht und/oder des Lotmaterials die Verstärkungsschicht mindestens eine intermetallische Phase umfasst oder aus mindestens einer metallischen Phase gebildet ist und somit das vorherige Lotmaterial vollständig ersetzt. Connecting layer, which comprises at least one metal, for example a metallic sintered compound, in particular of silver. Furthermore, the reinforcing layer is formed from a solder material, in particular a tin, bismuth, zinc, gallium or aluminum-based solder material, wherein after a temperature treatment of the bonding layer and / or the solder material, the reinforcing layer comprises or at least one intermetallic phase at least one metallic phase is formed and thus completely replaces the previous solder material.
Besonders vorteilhaft ist es, wenn die Verbindungsschicht, beispielsweise ausgeführt als Sinterformteil, und die Lotschicht in Form eines  It is particularly advantageous if the connecting layer, for example embodied as a sintered shaped part, and the solder layer in the form of a
Verbundelementes ausgebildet sind, welches dann zur Ausbildung der erfindungsgemäßen Verbindungsanordnung zwischen dem zumindest einen elektrischen und/oder elektronischen Bauelements und dem Fügepartner angeordnet wird. Hierbei ist die Lotschicht innerhalb des Verbundelements rahmenartig ausgeführt und auf der Verbindungsschicht angeordnet und/oder derart angrenzend an die Verbindungsschicht angeordnet, dass ihre innere Begrenzung die seitliche Flächenausdehnung der Verbindungsschicht begrenzt. Ein besonderer Vorteil zeigt sich dann darin, dass das Verbundelement in hohen Stückzahlen unabhängig von der Verwendung innerhalb einer Composite element are formed, which is then arranged to form the connection arrangement according to the invention between the at least one electrical and / or electronic component and the joining partner. In this case, the solder layer is embodied like a frame within the composite element and arranged on the connection layer and / or arranged adjacent to the connection layer such that its inner boundary limits the lateral surface extent of the connection layer. A particular advantage then shows up in the fact that the composite element in high quantities, regardless of the use within a
Verbindungsanordnung vorab hergestellt werden kann. Des Weiteren sind eine einfache Handhabung und ein Bestücken vergleichbar mit jedem elektrischen und/oder elektronischen Bauelement gegeben. Connecting arrangement can be prepared in advance. Furthermore, ease of handling and placement are comparable to any electrical and / or electronic component.
Die Temperaturbehandlung orientiert sich bevorzugt nach dem erforderlichen Lotprofil. Insgesamt ist somit eine sehr einfache und kostengünstige Möglichkeit gegeben, eine temperaturfeste intermetallische Phase durch gängige  The temperature treatment is preferably oriented according to the required solder profile. Overall, therefore, a very simple and cost-effective way is given, a temperature-resistant intermetallic phase by conventional
Verbindungsmaterialien und Verbindungsverfahren auszubilden. Forming connecting materials and connection methods.
Die erfindungsgemäße Verbindungsanordnung eignet sich besonders für Halbleiterbauelemente, beispielsweise aus Silizium, insbesondere mit einer flächigen Anschlussfläche, beispielsweise IGBT, MOSFET, DIODEN und Halbleiterchip. Derartige Bauelemente werden mittels der Verbindungsschicht beispielsweise auf einem DBC - Substrat (Direct copper bonded), einem metallischen Stanzgitter, einem organischen oder keramischen Schaltungsträger oder einem IMS - Substrat (Insulated metal Substrate) als Fügepartner befestigt. Die Verbindungsschicht, insbesondere als Sinterschicht, weist bevorzugt eine Schichtstärke von 10 - 500 μηη, insbesondere von 10 - 300 μηη, besonders bevorzugt von 10 - 100 μηη auf. Die Verstärkungsschicht kann in ihrer The connection arrangement according to the invention is particularly suitable for semiconductor components, for example made of silicon, in particular with a flat pad, for example IGBT, MOSFET, DIODEN and semiconductor chip. Such components are fastened by means of the connection layer, for example on a DBC substrate (direct copper bonded), a metal stamped grid, an organic or ceramic circuit carrier or an IMS substrate (insulated metal substrates) as a joining partner. The bonding layer, in particular as a sintered layer, preferably has a layer thickness of 10 to 500 μm, in particular 10 to 300 μm, particularly preferably 10 to 100 μm. The reinforcing layer may be in their
Schichtstärke ähnlich wie die Verbindungsschicht ausgeführt werden. Ist als Verstärkungsschicht eine Lotschicht gewählt, die insbesondere nach einer Temperaturbehandlung durch zumindest eine intermetallische Phase ersetzt sein soll, sind kleinere Schichtstärken bevorzugt, beispielsweise 0,5 - 100 pm, insbesondere 0,5 - 60 pm, besonders bevorzugt 1 pm - 30 pm. Layer thickness similar to the connection layer are performed. If a solder layer is selected as reinforcement layer, which in particular is replaced by a temperature treatment by at least one intermetallic phase should, smaller layer thicknesses are preferred, for example, 0.5 to 100 .mu.m, in particular 0.5 to 60 .mu.m, more preferably 1 pm to 30 pm.
Das erfindungsgemäße Fügeverfahren gemäß dem unabhängigen The joining method according to the invention according to the independent
Verfahrensanspruchs und die in den darauf rückbezogenen Unteransprüchen gezeigten Ausführungsformen ermöglichen in einfacher und kostengünstiger Weise einer Rissbildung und -weiterleitung innerhalb der Verbindungsschicht und/oder dem zumindest einen elektrischen und/oder elektronischen The method claim and the embodiments shown in the dependent subclaims allow a simple and cost-effective manner of crack formation and forwarding within the connection layer and / or the at least one electrical and / or electronic
Bauelements entgegenzuwirken. Hierbei können auch gängige Counteract component. Here also common
Verbindungsmaterialien verwendet werden, die unter anderem die Verwendung der gebildeten Verbindungsanordnung bei hohen Betriebstemperaturen erlauben. Among other things, connecting materials may be used which, among other things, allow the use of the formed connection assembly at high operating temperatures.
Kurze Beschreibung der Zeichnungen Brief description of the drawings
Weitere Vorteile, Merkmale und Einzelheiten der Erfindung ergeben sich aus der nachfolgenden Beschreibung bevorzugter Ausführungsbeispiele sowie anhand der Zeichnung. Diese zeigt in: Further advantages, features and details of the invention will become apparent from the following description of preferred embodiments and from the drawing. This shows in:
Fig. la: schematisch eine erste Ausführungsform der erfindungsgemäßen Verbindungsanordnung in einer Seitendarstellung, 1a shows schematically a first embodiment of the connection arrangement according to the invention in a side view,
Fig. lb: schematisch die Ausführung aus der Fig. la in einer Draufsicht, 1 b: schematically the embodiment of FIG. La in a plan view,
Fig. 2a: schematisch eine zweite Ausführungsform der erfindungsgemäßen Verbindungsanordnung in einer Seitendarstellung, 2a shows a schematic representation of a second embodiment of the connection arrangement according to the invention in a side view,
Fig. 2b: schematisch eine dritte Ausführungsform der erfindungsgemäßen Verbindungsanordnung in einer Seitendarstellung, 2b shows schematically a third embodiment of the connection arrangement according to the invention in a side view,
Fig. 2c: schematisch eine vierte Ausführungsform der erfindungsgemäßen Verbindungsanordnung in einer Seitendarstellung. 2c shows schematically a fourth embodiment of the connection arrangement according to the invention in a side view.
In den Figuren sind funktional gleiche Bauteile jeweils mit gleichen In the figures, functionally identical components are each the same
Bezugszeichen gekennzeichnet. Die Fig. la und lb zeigen eine erste Ausführungsform der erfindungsgemäßen Verbindungsanordnung 100. Zur Ausbildung der Verbindungsanordnung 100 wird ein Schaltungssubstrat 40, beispielsweise ein DBC-Substrat, bereitgestellt. Mit dem DBC-Substrat wird ein Halbleiterchip 10 stoffschlüssig verbunden. Hierzu weist der Halbleiterchip 10 auf der dem DBC-Substrat 40 zugewandtenReference number marked. 1a and 1b show a first embodiment of the connection arrangement 100 according to the invention. To form the connection arrangement 100, a circuit substrate 40, for example a DBC substrate, is provided. A semiconductor chip 10 is materially connected to the DBC substrate. For this purpose, the semiconductor chip 10 faces on the DBC substrate 40
Seite eine Anschlussfläche 11 auf. Die Anschlussfläche 11 dient beispielsweise zur elektrischen Kontaktierung des Halbleiterchips 10 und/oder zur dessen Entwärmung. Zur stoffschlüssigen Verbindung wird zwischen der Side a connection surface 11. The pad 11 is used for example for electrical contacting of the semiconductor chip 10 and / or for the heat dissipation. For cohesive connection is between the
Anschlussfläche 11 und dem DBC-Substrat 40 eine Sinterschicht 20 aus Silber angeordnet. Hierfür kann die Sinterschicht 20 beispielsweise in Pastenform vorliegen und mittels bekannten Pasten- Druckverfahren auf das DBC-Substrat 40 aufgetragen werden. Ebenso kann die Sinterschicht 20 als Sinterformteil ausgebildet werden und in der dann fest vorliegenden und an die Pad 11 and the DBC substrate 40, a sintered layer 20 made of silver. For this purpose, the sintered layer 20 can be in the form of a paste, for example, and can be applied to the DBC substrate 40 by means of known paste printing methods. Likewise, the sintered layer 20 may be formed as a sintered molded part and in the then firmly present and to the
Anschlussfläche 11 angepassten Form auf das DBC-Substrat 40 aufgelegt werden. Im konkreten Ausführungsbeispiel wird die Sinterschicht 20 derart ausgebildet, dass ein der Anschlussfläche 11 zugewandter oberer Pad 11 adapted form are placed on the DBC substrate 40. In the specific embodiment, the sintered layer 20 is formed such that one of the pad 11 facing upper
Flächenbereich 21 über die Anschlussfläche 11 des Halbleiterchips 10 hinausragt. Dieser Flächebereich 21 steht - wie in der Fig. lb in der Draufsicht zu erkennen - allgemein umseitig zum Halbleiterchip 10 über. Weiterhin wird auf diesen Flächenbereich 21 eine zinnbasierte Lotschicht 30 - beispielsweise ausSurface region 21 protrudes beyond the connection surface 11 of the semiconductor chip 10. As can be seen in the plan view in FIG. 1b, this surface region 21 projects generally on the side of the semiconductor chip 10. Furthermore, a tin-based solder layer 30 - for example made of this area region 21
SnAg3.5 oder aus SnCu0.7 - mit einer Schichtstärke s, beispielsweise 50 μηη, aufgebracht. Auf diese Weise wird die Lotschicht 30 mit einer inneren SnAg3.5 or SnCu0.7 - with a layer thickness s, for example, 50 μηη applied. In this way, the solder layer 30 with an inner
Begrenzung 35 und einer äußeren Begrenzung 36 ausgebildet. Die innere Begrenzung 35 der Lotschicht 30 reicht hierbei bis zur Anschlussfläche 11. Des Weiteren wird das Gehäuse des Halbleiterchips 10 in Höhe der Schichtstärke s von der Lotschicht 20 umseitig umsäumt. Limit 35 and an outer boundary 36 formed. In this case, the inner boundary 35 of the solder layer 30 extends as far as the connection area 11. Furthermore, the housing of the semiconductor chip 10 is surrounded by the solder layer 20 at the level of the layer thickness s.
Anschließend wird die so gebildete Anordnung, insbesondere die Sinterschicht 20 und/oder die Lotschicht 30, temperaturbehandelt. Die Temperaturbehandlung erfolgt bevorzugt im Bereich der Schmelztemperatur der Lotschicht 30. In demSubsequently, the arrangement thus formed, in particular the sintered layer 20 and / or the solder layer 30, is heat-treated. The temperature treatment is preferably carried out in the region of the melting temperature of the solder layer 30. In the
Fall, dass die Sintertemperatur der Sinterschicht 20 unterhalb der Case that the sintering temperature of the sintered layer 20 below the
Schmelztemperatur der Lotschicht 30 liegt, wird infolge der Melting temperature of the solder layer 30 is due to the
Temperaturbehandlung ein Sintervorgang angestoßen, wodurch der Temperature treatment initiated a sintering process, causing the
Halbleiterchip 10 mittels der Sinterschicht 20 mit dem DBC-Substrat 40 stoffschlüssig verbunden wird. Gleichzeitig setzen durch die Temperaturbehandlung Festkörperdiffusions-Vorgänge zwischen der Semiconductor chip 10 by means of the sinter layer 20 with the DBC substrate 40 is firmly bonded. At the same time put through the Temperature treatment solid-state diffusion processes between the
Sinterschicht 20 und der Lotschicht 30 ein. Dabei vermischen sich die Metalle und/oder Metalllegierungen beider Schichten 20, 30 zumindest in den Sintering layer 20 and the solder layer 30 a. In this case, the metals and / or metal alloys of both layers 20, 30 mix at least in the
Grenzbereichen, d.h. innerhalb des Flächenbereichs 21, und bilden eine Boundary areas, i. within the area 21, and form a
Verstärkungsschicht 30', umfassend mindestens eine intermetallischen Phase, aus. Im Falle von beispielsweise SnAg3.5 als Lotmaterial bildet sich Ag3Sn als intermetallische Phase aus. Im Falle von beispielsweise SnCu0.7 als Lotmaterial bildet sich sowohl Ag3Sn als auch Cu6Sn5 als intermetallische Phasen aus. Indem die Lotschicht 30 mit beispielsweise 50 μηη sehr dünn ausgeführt wird, können die Metalle und/oder Metalllegierungen beider Schichten 20, 30 während der Temperaturbehandlung sehr weit in die Lotschicht 30 hinein diffundieren. Bevorzugt wird eine Dauer der Temperaturbehandlung gewählt, bei welcher die Lotschicht 30 durch die gebildete mindestens eine intermetallische Phase im Wesentlichen ersetzt wird und auf diese Weise insgesamt die Reinforcing layer 30 ', comprising at least one intermetallic phase, from. In the case of, for example, SnAg3.5 as solder material, Ag3Sn forms as an intermetallic phase. For example, in the case of SnCu0.7 as solder material, both Ag3Sn and Cu6Sn5 form as intermetallic phases. By making the solder layer 30 very thin with, for example, 50 μm, the metals and / or metal alloys of both layers 20, 30 can diffuse very far into the solder layer 30 during the temperature treatment. Preferably, a duration of the temperature treatment is selected, in which the solder layer 30 is substantially replaced by the formed at least one intermetallic phase and in this way the total
Verstärkungsschicht 30' bildet. Aus Gründen der Vereinfachung wurde nicht dargestellt, dass die gebildete intermetallische Phase im Allgemeinen auch bereichsweise in die Sinterschicht 20 hineinreicht. In den Fig. 2a - 2c sind weitere beispielhafte Ausführungsformen der  Reinforcing layer 30 'forms. For reasons of simplification, it has not been shown that the intermetallic phase formed generally extends in some areas into the sintering layer 20. FIGS. 2a-2c show further exemplary embodiments of the invention
erfindungsgemäßen Verbindungsanordnung 200, 300, 400 gezeigt. Sie unterscheiden sich hauptsächlich in der Anordnung der Lotschicht 30 und der daraus gebildeten Verstärkungsschicht 30' innerhalb der Verbindungsanordnung 200, 300, 400. Connecting arrangement 200, 300, 400 according to the invention shown. They differ mainly in the arrangement of the solder layer 30 and the reinforcing layer 30 'formed therefrom within the connection arrangement 200, 300, 400.
In der zweiten Ausführungsform der erfindungsgemäßen Verbindungsanordnung 200 gemäß der Fig. 2a ist die Lotschicht 30 seitlich angrenzend an die In the second embodiment of the inventive connection arrangement 200 according to FIG. 2 a, the solder layer 30 is laterally adjacent to
Sinterschicht 20 auf dem DBC-Substrat aufgebracht. Dabei verbindet sich die nach der Temperaturbehandlung ausgebildete Verstärkungsschicht 30' stoffschlüssig sowohl mit der Sinterschicht 20 als auch mit dem DBC-Substrat.Sintered layer 20 is applied to the DBC substrate. In this case, the reinforcing layer 30 'formed after the temperature treatment bonds with both the sintered layer 20 and the DBC substrate.
Ferner begrenzt die innere Begrenzung 35 die seitliche Flächenausdehnung der Sinterschicht 20. Furthermore, the inner boundary 35 limits the lateral surface extent of the sintered layer 20.
Die dritte beispielhafte Ausführungsform der erfindungsgemäßen The third exemplary embodiment of the invention
Verbindungsanordnung 300 entsprechend der Fig. 2b ähnelt der zweiten Ausführungsform. Im Unterschied zu dieser wird die Sinterschicht 20 in der dritten Ausführungsform im Wesentlichen bündig mit der Anschlussfläche 11 bzw. dem Gehäuse des Halbleiterchips 10 ausgeführt. Zusätzlich wird die Lotschicht 30 in ihrer Schichtstärke zumindest im Bereich des Gehäuses des Halbleiterchips 10 derart ausgebildet, dass zumindest eine Mindesthöhe desConnecting arrangement 300 corresponding to FIG. 2b is similar to the second one Embodiment. In contrast to this, the sintered layer 20 in the third embodiment is made substantially flush with the connection surface 11 or the housing of the semiconductor chip 10. In addition, the solder layer 30 is formed in its layer thickness at least in the region of the housing of the semiconductor chip 10 such that at least a minimum height of
Gehäuses von einem Teil der Lotschicht 30 bzw. nach der Housing of a part of the solder layer 30 and after the
Temperaturbehandlung dann von der Verstärkungsschicht 30' umseitig umsäumt wird. Temperature treatment is then surrounded by the reinforcing layer 30 'on the other side.
In der vierten beispielhaften Ausführungsform der erfindungsgemäßen In the fourth exemplary embodiment of the invention
Verbindungsanordnung 400 gemäß der Fig. 2c wird die Lotschicht 30 innerhalb der Sinterschicht 20 integriert. Hierbei schließt die der Anschlussfläche 11 zugewandte Seite der Lotschicht 30 eben mit der Sinterschicht 20 ab, welche zumindest über die Schichtstärke s der Lotschicht 30 durch deren innere Connecting arrangement 400 according to FIG. 2 c, the solder layer 30 is integrated within the sintered layer 20. In this case, the side of the solder layer 30 facing the connection surface 11 ends flush with the sinter layer 20, which at least over the layer thickness s of the solder layer 30 through the inner layer
Begrenzung 35 begrenzt wird. Weiterhin wird die der Anschlussfläche abgewandte Seite der Lotschicht 30 von der Sinterschicht 20 überdeckt. Nach der Temperaturbehandlung verbindet sich die ausgebildete Verstärkungsschicht 30' stoffschlüssig sowohl mit der Sinterschicht 20 als auch mit dem in die Anschlussfläche 11 reichenden Flächenbereich. Limitation 35 is limited. Furthermore, the side of the solder layer 30 facing away from the connection surface is covered by the sintering layer 20. After the temperature treatment, the formed reinforcing layer 30 'integrally bonds both to the sintered layer 20 and to the surface area reaching into the connecting surface 11.
Allgemein sind noch weitere Ausführungsformen möglich, welche beispielsweise eine Kombination oder eine Abwandlung der bisher beschriebenen In general, other embodiments are possible which, for example, a combination or a modification of the previously described
Ausführungsformen darstellen. Represent embodiments.
Zusätzlich kann die Lotschicht grundsätzlich auch erst nach Ausbildung der stoffschlüssigen Verbindung des elektrischen und/oder elektronischen In addition, the solder layer can in principle only after the formation of the cohesive connection of the electrical and / or electronic
Bauelements, beispielsweise des Halbleiterchips 10, mit dem Fügepartner, beispielsweise mit dem DBC-Substrat 40, aufgetragen und/oder angeordnet werden. Component, such as the semiconductor chip 10, with the joining partner, for example, with the DBC substrate 40, applied and / or arranged.
Das Aufbringen der Lotschicht 30 auf die Sinterschicht 20 in Form eines The application of the solder layer 30 to the sintered layer 20 in the form of a
Sinterformteils bzw. das seitliche Anordnen der Lotschicht 30 angrenzend zur Verbindungsschicht 20 derart, dass die Lotschicht 30 mit ihrer inneren Sinter molding or the lateral placement of the solder layer 30 adjacent to the connection layer 20 such that the solder layer 30 with its inner
Begrenzung 35 die seitliche Flächenausdehnung der Verbindungsschicht 20 begrenzt, kann auch bereits vor der Ausbildung der Verbindungsanordnung 100, 200, 300, 400 unter Ausbildung eines Verbundelements erfolgen. In diesem Fall wird das Verbundelement zwischen dem zumindest einen elektrischen und/oder elektronischen Bauelement, beispielsweise dem Halbleiterchip 10, und dem Fügepartner, beispielsweise dem DBC-Substrat, angeordnet und anschließend die Temperaturbehandlung zur Ausbildung der Verstärkungsschicht 30' durchgeführt. Limiting 35 limits the lateral surface extent of the connection layer 20, can also already before the formation of the connection assembly 100, 200, 300, 400 carried out to form a composite element. In this case, the composite element is arranged between the at least one electrical and / or electronic component, for example the semiconductor chip 10, and the joining partner, for example the DBC substrate, and then the temperature treatment for forming the reinforcing layer 30 'is carried out.
Allgemein ist es auch möglich, die mindestens ein Metall umfassende Generally, it is also possible to include the at least one metal
Verbindungsschicht 20 als Lotschicht vorzusehen, beispielsweise aus einem Zinn-, Wismut-, Zink-, Gallium- oder Aluminium-basierten Weichlot. Ebenso kann allgemein die Verstärkungsschicht 30' aus einer Metallschicht, insbesondere Zinn, Silber, Kupfer, Zink, Wismut, Gallium und/oder Aluminium enthaltend, ausgebildet sein, welche beispielsweise durch ein chemisches und/oder physikalisches Beschichtungsverfahren aufgetragen wird. Grundsätzlich können Materialien für die Verbindungsschicht 20 und die Verstärkungsschicht 30' derart ausgewählt werden, dass auf Grund einer Temperaturbehandlung und den dabei zwischen beiden Schichten 20, 30 stattfindenden Diffusionsvorgängen die Verstärkungsschicht 30' mindestens eine intermetallische Phase umfasst. Provide bonding layer 20 as a solder layer, for example, a tin, bismuth, zinc, gallium or aluminum-based soft solder. Likewise, in general, the reinforcing layer 30 'may be formed from a metal layer, in particular tin, silver, copper, zinc, bismuth, gallium and / or aluminum, which is applied, for example, by a chemical and / or physical coating process. In principle, materials for the connection layer 20 and the reinforcement layer 30 'may be selected such that, due to a temperature treatment and the diffusion processes occurring between the two layers 20, 30, the reinforcement layer 30' comprises at least one intermetallic phase.

Claims

Ansprüche claims
Verbindungsanordnung (100, 200, 300, 400) mindestens eines elektrischen und/oder elektronischen Bauelements (10), insbesondere eines Halbleiterchips, mit einem Fügepartner (40), beispielsweise einem Schaltungsträger, wobei das mindestens eine elektrische und/oder elektronische Bauelement (10) mindestens eine Anschlussfläche (11) aufweist, welche mittels einer Verbindungsschicht (20) mit dem Fügepartner (40) stoffschlüssig verbunden ist, Connecting arrangement (100, 200, 300, 400) of at least one electrical and / or electronic component (10), in particular of a semiconductor chip, with a joining partner (40), for example a circuit carrier, wherein the at least one electrical and / or electronic component (10) has at least one connection surface (11) which is adhesively connected by means of a connection layer (20) to the joining partner (40),
dadurch gekennzeichnet, dass  characterized in that
angrenzend zur Verbindungsschicht (20) zur Verhinderung von Rissbildung innerhalb der Verbindungsschicht (20) auf Grund von thermischen und/oder thermomechanischen Spannungen stoffschlüssig eine Verstärkungsschicht (30') angeordnet ist, welche ein höheres Elastizitätsmodul aufweist als die Verbindungsschicht (20), wobei die Verstärkungsschicht (30') durch eine äußere und eine innere Begrenzung (36, 35) rahmenartig ausgebildet ist und zumindest mit ihrer äußeren Begrenzung (36) die Anschlussfläche (11) des mindestens einen elektrischen und/oder elektronischen Bauelements (10) umschließt.  a reinforcing layer (30 '), which has a higher modulus of elasticity than the connecting layer (20), is arranged in a materially joined manner adjacent to the connection layer (20) for preventing cracking within the connection layer (20) on the basis of thermal and / or thermomechanical stresses, wherein the reinforcement layer (30 ') by an outer and an inner boundary (36, 35) is like a frame and at least with its outer boundary (36) surrounds the connection surface (11) of the at least one electrical and / or electronic component (10).
Verbindungsanordnung (100, 200, 300, 400) nach Anspruch 1, Connecting arrangement (100, 200, 300, 400) according to claim 1,
dadurch gekennzeichnet, dass  characterized in that
die innere Begrenzung (35) der Verstärkungsschicht (30') bis innerhalb der Anschlussfläche (11) des mindestens einen elektrischen und/oder elektronischen Bauelements (10) reicht.  the inner boundary (35) of the reinforcement layer (30 ') reaches within the connection surface (11) of the at least one electrical and / or electronic component (10).
Verbindungsanordnung nach einem der Ansprüche 1 oder 2, Connecting arrangement according to one of claims 1 or 2,
dadurch gekennzeichnet, dass  characterized in that
die Verbindungsschicht (20) einen Flächenbereich (21) aufweist, welcher über die Anschlussfläche (11) des mindestens einen elektrischen und/oder elektronischen Bauelements (10) hinausragt, wobei die Verstärkungsschicht (30') in diesem Flächenbereich (21) auf der Verbindungsschicht (20) angeordnet ist und/oder dass die Verstärkungsschicht (20) mit ihrer inneren Begrenzung (35) die seitliche Flächenausdehnung der Verbindungsschicht (20) begrenzt. the connection layer (20) has a surface region (21) which projects beyond the connection surface (11) of the at least one electrical and / or electronic component (10), wherein the reinforcement layer (30 ') is arranged in this surface area (21) on the connecting layer (20) and / or that the reinforcing layer (20) with its inner boundary (35) limits the lateral area extent of the connecting layer (20).
Verbindungsanordnung (100, 200, 300, 400) nach einem der vorhergehenden Ansprüche, Connecting arrangement (100, 200, 300, 400) according to one of the preceding claims,
dadurch gekennzeichnet, dass characterized in that
die Verstärkungsschicht (30') mindestens eine intermetallische Phase umfasst. the reinforcing layer (30 ') comprises at least one intermetallic phase.
Verbindungsanordnung (100, 200, 300, 400) nach einem der vorhergehenden Ansprüche, Connecting arrangement (100, 200, 300, 400) according to one of the preceding claims,
dadurch gekennzeichnet, dass characterized in that
die Verbindungsschicht (20) mindestens ein Metall umfasst und die Verstärkungsschicht (30') aus einem Lotmaterial (30) gebildet ist, insbesondere aus einem Zinn-, Wismut-, Zink-, Gallium- oder Aluminium - basierten Lotmaterial, wobei nach einer Temperaturbehandlung der Verbindungsschicht (20) und/oder des Lotmaterials (30) die Verstärkungsschicht (30') mindestens eine intermetallische Phase umfasst oder aus mindestens einer intermetallischen Phase gebildet ist. the connecting layer (20) comprises at least one metal and the reinforcing layer (30 ') is formed from a solder material (30), in particular from a tin, bismuth, zinc, gallium or aluminum-based solder material, wherein after a temperature treatment Connecting layer (20) and / or the solder material (30), the reinforcing layer (30 ') comprises at least one intermetallic phase or is formed from at least one intermetallic phase.
Verbindungsanordnung (100, 200, 300, 400) nach einem der vorhergehenden Ansprüche, Connecting arrangement (100, 200, 300, 400) according to one of the preceding claims,
dadurch gekennzeichnet, dass characterized in that
die Verbindungsschicht (20) eine Metallschicht ist, insbesondere Zinn, Silber, Kupfer, Zink, Wismut, Gallium und/oder Aluminium enthaltend. the bonding layer (20) is a metal layer, in particular containing tin, silver, copper, zinc, bismuth, gallium and / or aluminum.
Verbindungsanordnung (100, 200, 300, 400) nach einem der vorhergehenden Ansprüche, Connecting arrangement (100, 200, 300, 400) according to one of the preceding claims,
dadurch gekennzeichnet, dass characterized in that
die Verbindungsschicht (20) eine Sinterschicht ist, insbesondere aus Silber. the bonding layer (20) is a sintered layer, in particular of silver.
8. ) Verbundelement, insbesondere zur Ausbildung einer Verbindungsanordnung8.) composite element, in particular for forming a connection arrangement
(100, 200, 300, 400) nach einem der vorhergehenden Ansprüche, umfassend eine Verbindungsschicht (20) enthaltend mindestens ein Metall und eine an die Verbindungsschicht (20) angrenzend angeordnete Lotschicht (30), (100, 200, 300, 400) according to one of the preceding claims, comprising a connection layer (20) comprising at least one metal and a solder layer (30) arranged adjacent to the connection layer (20),
dadurch gekennzeichnet, dass  characterized in that
die Lotschicht (30) durch eine äußere und eine innere Begrenzung (36, 35) rahmenartig ausgeführt ist und auf der Verbindungsschicht (20) angeordnet ist und/oder die Lotschicht (30) mit ihrer inneren Begrenzung (35) die seitliche Flächenausdehnung der Verbindungsschicht (20) begrenzt, wobei das Verbundelement derart ausgeführt ist, bei einer Temperaturbehandlung der Verbindungsschicht (20) und/oder der Lotschicht (30) zwischen der Verbindungsschicht (20) und der Lotschicht (30) zur Verhinderung von Rissbildung innerhalb der Verbindungsschicht (20) auf Grund von thermischen und/oder thermomechanischen Spannungen eine Verstärkungsschicht (30'), umfassend mindestens eine intermetallische Phase, auszubilden, wobei die gebildete Verstärkungsschicht (30') einen höheren E-Modul aufweist als die Verbindungsschicht (20).  the solder layer (30) is designed like a frame by an outer and an inner boundary (36, 35) and is arranged on the connection layer (20) and / or the solder layer (30) with its inner boundary (35) has the lateral surface extension of the connection layer ( 20), wherein the composite element is designed in such a way, during a temperature treatment of the bonding layer (20) and / or the solder layer (30) between the bonding layer (20) and the solder layer (30) to prevent cracking within the bonding layer (20) Reason of thermal and / or thermo-mechanical stresses, a reinforcing layer (30 '), comprising at least one intermetallic phase form, wherein the formed reinforcing layer (30') has a higher modulus of elasticity than the connecting layer (20).
9. ) Verbundelement nach Anspruch 8, 9.) Composite element according to claim 8,
dadurch gekennzeichnet, dass  characterized in that
nach der Temperaturbehandlung zumindest die Lotschicht (30) durch die gebildete Verstärkungsschicht (30') im Wesentlichen ersetzt ist.  after the temperature treatment, at least the solder layer (30) is essentially replaced by the formed reinforcing layer (30 ').
Verbundelement nach einem der Ansprüche 8 oder 9, Composite element according to one of claims 8 or 9,
dadurch gekennzeichnet, dass  characterized in that
die Lotschicht (30) Zinn, Wismut, Zink, Gallium und/oder Aluminium enthält und/oder die Verbindungsschicht (20) eine Sinterschicht oder ein Sinterformteil, insbesondere aus Silber, ist. the solder layer (30) contains tin, bismuth, zinc, gallium and / or aluminum and / or the bonding layer (20) is a sintered layer or a sintered molded part, in particular of silver.
11. ) Fügeverfahren, insbesondere zur Ausbildung einer Verbindungsanordnung11.) joining method, in particular for the formation of a connection arrangement
(100, 200, 300, 400) nach einem der Ansprüche 1 bis 7, wobei zur stoffschlüssigen Verbindung eine Verbindungsschicht (20) zwischen der Anschlussfläche (11) mindestens eines elektrischen und/oder elektronischen Bauelements (10) und einem Fügepartner (40) angeordnet wird, (100, 200, 300, 400) according to one of claims 1 to 7, wherein for the material connection a connection layer (20) between the connection surface (11) of at least one electrical and / or electronic component (10) and a joining partner (40) becomes,
dadurch gekennzeichnet, dass  characterized in that
angrenzend zur Verbindungsschicht (20) zur Verhinderung von Rissbildung innerhalb der Verbindungsschicht (20) auf Grund von thermischen und/oder thermomechanischen Spannungen eine Verstärkungsschicht (30') angeordnet wird, welche einen höheren Elastizitätsmodul aufweist als die Verbindungsschicht (20), wobei die Verstärkungsschicht (30') durch eine äußere und eine innere Begrenzung (36, 35) rahmenartig ausgebildet wird und die Anschlussfläche (11) des mindestens einen elektrischen und/oder elektronischen Bauelements (10) durch zumindest die äußere Begrenzung (36) der Verstärkungsschicht (30') umschlossen wird.  a reinforcing layer (30 '), which has a higher modulus of elasticity than the connecting layer (20), is arranged adjacent to the connection layer (20) for preventing cracking within the connection layer (20) due to thermal and / or thermomechanical stresses. 30 ') is formed like a frame by an outer and an inner boundary (36, 35) and the connection surface (11) of the at least one electrical and / or electronic component (10) by at least the outer boundary (36) of the reinforcing layer (30') is enclosed.
12. ) Fügeverfahren nach Anspruch 11, 12.) joining method according to claim 11,
dadurch gekennzeichnet, dass  characterized in that
die Verbindungsschicht (20) mindesten ein Metall umfasst und die Verstärkungsschicht (30') aus einer Lotschicht (30), insbesondere Zinn, Wismut, Zink, Gallium und/oder Aluminium enthaltend, gebildet wird, wobei die Lotschicht (30) durch eine äußere und eine innere Begrenzung (36, 35) rahmenartig ausgebildet wird und auf einen Flächenbereich (21) der Verbindungsschicht (20) aufgebracht wird, welcher über die Anschlussfläche (11) des mindestens einen elektrischen und/oder elektronischen Bauelements (10) hinausragt, und/oder die Lotschicht (30) derart angeordnet wird, dass sie mit ihrer inneren Begrenzung (35) die seitliche Flächenausdehnung der Verbindungsschicht (20) begrenzt, und die Verbindungsschicht (20) und/oder die Lotschicht (30) temperaturbehandelt werden und zwischen der Verbindungsschicht (20) und der Lotschicht (30) die Verstärkungsschicht (30') umfassend mindestens eine intermetallische Phase gebildet wird, wobei die gebildete Verstärkungsschicht (30') einen höheren E-Modul aufweist als die Verbindungsschicht (20), und wobei bevorzugt mindestens die Lotschicht (30) durch die ausgebildete Verstärkungsschicht (30') im Wesentlichen ersetzt wird. the connecting layer (20) comprises at least one metal and the reinforcing layer (30 ') is formed from a solder layer (30), in particular tin, bismuth, zinc, gallium and / or aluminum, wherein the solder layer (30) is formed by an outer layer an inner boundary (36, 35) is formed like a frame and is applied to a surface region (21) of the connection layer (20) which projects beyond the connection surface (11) of the at least one electrical and / or electronic component (10), and / or the solder layer (30) is arranged in such a way that with its inner boundary (35) it limits the lateral areal extent of the connection layer (20), and the connection layer (20) and / or the solder layer (30) are heat-treated and interposed between the connection layer (20 ) and the solder layer (30), the reinforcing layer (30 ') comprising at least one intermetallic phase is formed, wherein the formed reinforcing layer (30 ') has a higher modulus of elasticity than the connecting layer (20), and wherein preferably at least the solder layer (30) is substantially replaced by the formed reinforcing layer (30').
13. ) Fügeverfahren nach einem der Ansprüche 11 oder 12, 13.) joining method according to one of claims 11 or 12,
dadurch gekennzeichnet, dass  characterized in that
nach Ausbildung der stoffschlüssigen Verbindung des mindestens einen elektrischen und/oder elektronischen Bauelements (10) mit der Verbindungsschicht (20) die Lotschicht (30) aufgetragen und/oder angeordnet wird.  after formation of the cohesive connection of the at least one electrical and / or electronic component (10) with the connection layer (20), the solder layer (30) is applied and / or arranged.
14. ) Fügeverfahren nach einem der Ansprüche 11 bis 13, 14.) joining method according to one of claims 11 to 13,
dadurch gekennzeichnet, dass  characterized in that
die Verbindungsschicht (20) als Sinterschicht oder Sinterformteil, insbesondere aus Silber, ausgebildet wird.  the connecting layer (20) as a sintered layer or sintered molded part, in particular of silver, is formed.
EP13702765.2A 2012-02-09 2013-01-25 Connection arrangement of an electric and/or electronic component Pending EP2812912A2 (en)

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DE102012201935A DE102012201935A1 (en) 2012-02-09 2012-02-09 Connecting arrangement of an electrical and / or electronic component
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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011083931A1 (en) * 2011-09-30 2013-04-04 Robert Bosch Gmbh Layer composite of an electronic substrate and a layer arrangement comprising a reaction solder
US20160038293A1 (en) * 2013-03-15 2016-02-11 Conformis, Inc. Posterior-Stabilized Knee Implant Components and Instruments
JP2015115481A (en) * 2013-12-12 2015-06-22 株式会社東芝 Semiconductor component and method of manufacturing semiconductor component
US9875987B2 (en) 2014-10-07 2018-01-23 Nxp Usa, Inc. Electronic devices with semiconductor die attached with sintered metallic layers, and methods of formation of such devices
US9589860B2 (en) * 2014-10-07 2017-03-07 Nxp Usa, Inc. Electronic devices with semiconductor die coupled to a thermally conductive substrate
US9698116B2 (en) 2014-10-31 2017-07-04 Nxp Usa, Inc. Thick-silver layer interface for a semiconductor die and corresponding thermal layer
DE102015200989A1 (en) * 2015-01-22 2016-07-28 Robert Bosch Gmbh Connecting arrangement between a carrier element and an electronic circuit component and circuit carrier
DE102015113421B4 (en) 2015-08-14 2019-02-21 Danfoss Silicon Power Gmbh Method for producing semiconductor chips
EP3154079A1 (en) * 2015-10-08 2017-04-12 Heraeus Deutschland GmbH & Co. KG Method for connecting a substrate arrangement with an electronic component using a pre-fixing agent on a contact material layer, corresponding substrate arrangement and method of manufacturing thereof
KR20170059833A (en) * 2015-11-23 2017-05-31 삼성전기주식회사 Strip substrate and manufacturing method thereof
US10969118B2 (en) 2016-05-26 2021-04-06 Electrolux Home Products, Inc. Steam cooking appliance
US9941210B1 (en) 2016-12-27 2018-04-10 Nxp Usa, Inc. Semiconductor devices with protruding conductive vias and methods of making such devices
DE102018221148A1 (en) * 2018-12-06 2020-06-10 Heraeus Deutschland GmbH & Co. KG Method for producing a substrate adapter and substrate adapter for connecting to an electronic component
US20230131247A1 (en) * 2019-10-31 2023-04-27 Boe Technology Group Co., Ltd. Supporting backplane, manufacturing method therefor and backplane
DE102020117678B3 (en) 2020-07-03 2021-08-12 Infineon Technologies Ag SEMI-CONDUCTOR DEVICE WITH HETEROGENIC SOLDER JOINT AND METHOD OF MANUFACTURING IT
BR112023003159A2 (en) * 2020-09-02 2023-04-04 Qualcomm Inc POWER SAVING TECHNIQUES IN COMPUTING DEVICES THROUGH COMMUNICATION BUS CONTROL
NL2027068B1 (en) * 2020-12-08 2022-07-07 Stichting Chip Integration Tech Centre Integrated circuit comprising improved die attachment layer
EP4047648A1 (en) * 2021-02-18 2022-08-24 Siemens Aktiengesellschaft Power module with a power component bonded to a substrate by sintering and soldering and corresponding manufacturing method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5244566A (en) * 1975-10-06 1977-04-07 Mitsubishi Electric Corp Method of alloying semiconductor pellet
JPS5966131A (en) * 1982-10-08 1984-04-14 Nec Corp Mounting structure of semiconductor pellet
EP1039526A2 (en) * 1999-03-24 2000-09-27 Ford Motor Company Method and article for attaching high-operating-temperature electronic component
JP2007109834A (en) * 2005-10-13 2007-04-26 Fuji Electric Holdings Co Ltd Semiconductor device and method of manufacturing same
US20110084384A1 (en) * 2009-10-14 2011-04-14 Renesas Electronics Corporation Semiconductor device and method for manufacturing the same

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0545009Y2 (en) * 1987-04-06 1993-11-16
JPH01293539A (en) * 1988-05-23 1989-11-27 Fuji Xerox Co Ltd Forming method for bump of semiconductor device
JP2503282B2 (en) * 1989-12-08 1996-06-05 富士通株式会社 Light-receiving element carrier and light-receiving module having the carrier
JP2956617B2 (en) * 1996-10-31 1999-10-04 日本電気株式会社 Resin-sealed semiconductor device
JP2001230351A (en) * 2000-02-14 2001-08-24 Shibafu Engineering Corp Joining material for electronic module, module type semiconductor device, and method of manufacturing the same
DE102004058878A1 (en) * 2004-12-06 2006-06-14 Infineon Technologies Ag Semiconductor device and method for manufacturing a semiconductor device
JP2007201314A (en) * 2006-01-30 2007-08-09 Toyota Central Res & Dev Lab Inc Semiconductor device
US8283756B2 (en) * 2007-08-20 2012-10-09 Infineon Technologies Ag Electronic component with buffer layer
JP2010171271A (en) 2009-01-23 2010-08-05 Renesas Technology Corp Semiconductor device and method of manufacturing the same
US20110303448A1 (en) * 2010-04-23 2011-12-15 Iowa State University Research Foundation, Inc. Pb-Free Sn-Ag-Cu-Al or Sn-Cu-Al Solder
US8513798B2 (en) * 2010-09-09 2013-08-20 Infineon Technologies Ag Power semiconductor chip package
CN103190204B (en) * 2010-11-03 2016-11-16 3M创新有限公司 There is the flexible LED device of wire bond-tube core
US8736052B2 (en) * 2011-08-22 2014-05-27 Infineon Technologies Ag Semiconductor device including diffusion soldered layer on sintered silver layer
JP5608824B2 (en) * 2011-12-27 2014-10-15 パナソニック株式会社 Bonding structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5244566A (en) * 1975-10-06 1977-04-07 Mitsubishi Electric Corp Method of alloying semiconductor pellet
JPS5966131A (en) * 1982-10-08 1984-04-14 Nec Corp Mounting structure of semiconductor pellet
EP1039526A2 (en) * 1999-03-24 2000-09-27 Ford Motor Company Method and article for attaching high-operating-temperature electronic component
JP2007109834A (en) * 2005-10-13 2007-04-26 Fuji Electric Holdings Co Ltd Semiconductor device and method of manufacturing same
US20110084384A1 (en) * 2009-10-14 2011-04-14 Renesas Electronics Corporation Semiconductor device and method for manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2013117438A2 *

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US20160064350A1 (en) 2016-03-03
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CN104094387A (en) 2014-10-08
US9177934B2 (en) 2015-11-03
DE102012201935A1 (en) 2013-08-14
WO2013117438A2 (en) 2013-08-15

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