EP2593974A2 - Dispositif support pour une puce semi-conductrice, composant électronique comportant un dispositif support et composant optoélectronique comportant un dispositif support - Google Patents

Dispositif support pour une puce semi-conductrice, composant électronique comportant un dispositif support et composant optoélectronique comportant un dispositif support

Info

Publication number
EP2593974A2
EP2593974A2 EP11748290.1A EP11748290A EP2593974A2 EP 2593974 A2 EP2593974 A2 EP 2593974A2 EP 11748290 A EP11748290 A EP 11748290A EP 2593974 A2 EP2593974 A2 EP 2593974A2
Authority
EP
European Patent Office
Prior art keywords
carrier
solder
carrier device
semiconductor chip
coating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP11748290.1A
Other languages
German (de)
English (en)
Inventor
Thomas Zeiler
Lai Sham Khong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of EP2593974A2 publication Critical patent/EP2593974A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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Definitions

  • Carrier device for a semiconductor chip, electronic component with a carrier device and optoelectronic component with a carrier device
  • carrier device for a semiconductor chip
  • electronic component with a carrier device
  • optoelectronic device with a
  • LEDs Light emitting diodes
  • LEDs typically include a housing in which a lead frame is embedded. On the lead frame inside the housing is an LED chip
  • Such an LED is usually glued to the carrier via outlets of the leadframe led out of the housing. Since the connection of the housing to the lead frame is typically not continuous like this
  • solder material may thereby form a thin film which uncontrollably covers the lead frame within the housing.
  • Creep can be compounded by soldering and desoldering the LED several times.
  • Chip carrier such as ceramic carrier with conductor tracks or
  • Carrier device for a semiconductor chip a bondable and / or solderable metallic carrier with a
  • soldering means, in particular, that the metallic support is provided and suitable for fixing a semiconductor chip, for example by means of so-called “the attach” or chip bonding, and / or that a contact wire by means of "wire bonding” or
  • Wire bonding can be attached.
  • the metallic support may have a suitable layer in the form of a bondable coating.
  • the soldering area is intended and suitable for soldering the carrier and thus the carrier device to a suitable electrical contact.
  • the carrier device can be soldered to a contact point or a conductor track of a ceramic carrier or a printed circuit board.
  • the carrier is at least partially covered with a covering material, so that an interface between the carrier and the covering material is formed.
  • the cover material may in particular be adjacent to the carrier between the soldering area and the
  • Mounting region may be arranged for the semiconductor chip, so that the carrier and the cover material has a common
  • solder barrier suitable to allow creep of solder between the mounting region and the solder region along the interface as compared to a carrier without a solder barrier
  • solder barrier may be completely covered by the cover material or alternatively
  • Solder barrier which is disposed at the interface between the carrier and the cover material, is disposed entirely outside the cover and further adjacent to the interface. According to another embodiment, the
  • the solder barrier may in particular be arranged on the surface of the carrier, which also has the mounting area. On this surface can the
  • Extension direction extend on this surface over the entire carrier. Thereby, it may be possible that there is no direct creep path for a solder on the surface along the interface between the soldering area and the mounting area on the surface having the mounting area
  • Solder Barrier passes so that the mounting area is shielded from the soldering area by the solder barrier.
  • this encloses
  • Carrier up to the soldering area or up to the soldering area and the mounting area encloses.
  • the carrier
  • the solder barrier may be arranged on at least one surface and in particular on that surface of the carrier which has the mounting region.
  • the carrier is as
  • the carrier can as
  • Leadframe in a housing for an optoelectronic or be executed for an electronic component.
  • Soldering can be formed by a part of the lead frame, which is led out of the housing.
  • the carrier may be copper or
  • Copper and copper alloys are a particularly suitable material for Copper and copper alloys. Copper and copper alloys are a particularly suitable material for Copper and copper alloys. Copper and copper alloys are a particularly suitable material for Copper and copper alloys. Copper and copper alloys are a particularly suitable material for Copper and copper alloys. Copper and copper alloys are a particularly suitable material for Copper and copper alloys. Copper and copper alloys are a particularly suitable material for Copper and copper alloys. Copper and copper alloys are a particularly suitable material for
  • Leadframe due to their ease of processing and their electrical and thermal conductivity.
  • the lead frame may also include other or other materials common for lead frames.
  • the covering material comprises an epoxide or is formed from an epoxide.
  • the cover material may also be a silicone, an acrylate and / or an imide or
  • epoxides can have a high mechanical stability and a certain radiation stability.
  • the carrier may have a coating which covers the carrier material and thus, for example, before
  • the coating may be formed at least at the interface between the carrier and the cover material and particularly preferably the entire carrier, ie as an all-round coating, wherein on all sides also means that optionally the solder barrier forms an area in which no or only part of the Coating is present.
  • the carrier has the coating at least at the interface between the carrier and the covering material which further may have a high wettability for a solder. Such high wettability can advantageously serve to facilitate the solderability of the soldering area.
  • the coating may comprise an alloy with nickel and / or palladium and / or gold. Alloys with nickel and / or palladium and / or gold, for example PdAu or NiPdAu or NiAu, may be particularly suitable, the carrier material, in particular copper, from harmful
  • the surface energy conditions in a palladium, a gold and in particular a PdAu coating result in a high wettability of liquid solder, in particular of liquid tin, due to a low wetting angle. Due to the high wettability of such
  • Coating in particular also by the tin in the solder can very easily creep along the boundary surface between the carrier and the cover material and thus, for example, when soldering the carrier device by means of the soldering area, for example, to a printed circuit board or a circuit board from the soldering area in the direction of the mounting area Cover vehicle.
  • Carrier device are high enough that the solder is in a liquid state, means a reduction or prevention of the creep effect by the
  • Creep speed of the solder through the Solder barrier is reduced such that the solder or components of the solder during a conventional soldering process can not get to the mounting area.
  • the creep effect can advantageously be kept under control and can be predicted in the context of conventional soldering processes, such as a reflow soldering process.
  • the coating can also be a layer sequence with a plurality of layers with the aforementioned
  • the coating may comprise a layer of nickel, a layer of palladium on top and a layer of gold over it.
  • the coating may comprise a layer of nickel, a layer of palladium on top and a layer of gold over it.
  • the coating may comprise a layer of nickel, a layer of palladium on top and a layer of gold over it.
  • Wettability by a solder has as the carrier.
  • the solder barrier has a material which has a lower wettability by a solder than the carrier material or a coating of the carrier.
  • a suitable material may be silver or silver which has lower wettability, particularly for tin-based solders, compared to palladium and / or gold-containing coatings for the carrier.
  • the material may also be nickel, which may also form a good creep stop for solder.
  • the solder barrier has a material which has a lower wettability by a solder than the carrier material or a coating of the carrier.
  • a suitable material may be silver or silver which has lower wettability, particularly for tin-based solders, compared to palladium and / or gold-containing coatings for the carrier.
  • the material may also be nickel, which may also form a good creep stop for solder.
  • the solder barrier has a material which has a lower wettability by a solder than the carrier material or a coating of the carrier
  • Solder barrier have a material that in a
  • Solder is soluble. This may in particular mean that the material of the solder barrier is dissolved in the solder as it creeps along the interface with the solder barrier. The material of the solder barrier may thereby form an alloy with the solder, which has a lower creeping speed and a higher wetting at the interface between the carrier and the covering material than the solder alone. Such a material can
  • tin-based solders have, for example, silver or silver.
  • Solder barrier can be designed as a corresponding coating of the carrier.
  • Silver is soluble in tin and forms an alloy with tin which, for example, has a lower creep rate than pure tin on a palladium and / or gold coating on the support. If silver is used as a lead frame coating in known LEDs, then these are required, the
  • the material of the solder barrier may also be disposed in the coating, so that instead of the coating material or a part thereof, the material of the solder barrier is arranged.
  • Solder barrier on a depression can be used in particular in conjunction with one described above
  • the recess in this case can interrupt the coating and extend through the coating into the carrier material.
  • the solder barrier in this case has the surface of the layer exposed by the coating
  • Carrier material which advantageously a smaller
  • Wettability by the solder as the coating The fact that the solder barrier is arranged between the covering material and the carrier, the area of the carrier, which is free from the coating due to the solder barrier, can be protected by the covering material from harmful external influences.
  • the covering material in the case of a coating with a
  • Protruding coating but at least one
  • the underlying layer of coating still covers the carrier. Furthermore, by the depression with advantage the interface between the covering material and the carrier can be increased, so that an extension of a possible creeping path between the soldering area and the mounting area can be achieved.
  • Support device on at least one further bondable and / or solderable metallic carrier.
  • the further metallic carrier can be one or more of the above
  • the further metallic carrier may be at least partially covered by the covering material, wherein at an interface between the
  • Solder barrier is arranged. The others
  • Solder Barrier may include one or more of the above
  • the other carrier can be any carrier.
  • a further mounting region for a further semiconductor chip or a bonding region for connecting a semiconductor chip, for example via a bonding wire For example, have a further mounting region for a further semiconductor chip or a bonding region for connecting a semiconductor chip, for example via a bonding wire.
  • the recess is formed by means of a mechanical
  • Carrier be carved.
  • a depression can be formed in the carrier by means of an etching process.
  • an electronic component has a carrier device according to one or more of the aforementioned embodiments.
  • the electronic component can be embodied, for example, as an integrated circuit, that is to say as a so-called IC chip, or else as a discrete component.
  • the electronic component has a semiconductor chip which is arranged on the carrier device.
  • the semiconductor chip is arranged on the mounting area.
  • an optoelectronic component has a carrier device according to one or more of the aforementioned embodiments. Furthermore, the optoelectronic component has an optoelectronic semiconductor chip on the mounting region of the carrier device.
  • the cover material can as
  • Housing body to be molded to the carrier, wherein the
  • Optoelectronic semiconductor chip is arranged in the housing.
  • Optoelectronic semiconductor chip as a radiation-emitting semiconductor chip, in particular as a radiation-emitting
  • the optoelectronic semiconductor chip can also be embodied as a radiation-receiving semiconductor chip, for example as a photodiode.
  • Figures 1A and 1B are schematic representations of a
  • FIGS 2A to 5 are schematic representations of sections of carrier devices according to further embodiments.
  • FIGS. 1A and 1B a carrier device 100 for a semiconductor chip 3 is shown, wherein the semiconductor chip 3 is indicated by the dashed line.
  • FIG. 1A shows a sectional view of the carrier device 100
  • FIG. 1B shows a plan view of the carrier 1, 1 'of FIG.
  • Carrier device 100 at the interfaces 10, 10 'in Figure 1A shows.
  • the following description refers to
  • the carrier device 100 has a bondable and / or solderable metallic carrier 1 as well as another bondable and / or solderable metallic carrier 1 ', which in the
  • Support material made of copper or a copper alloy, a coating (not shown), in particular a galvanic coating, on the one hand serves as corrosion protection and on the other hand provides suitable surfaces that are suitable for soldering and / or bonding.
  • Examples may be, for example, a NiPdAu alloy, or alternatively, other
  • Alloys and / or layer sequences for example, with Ni, Pd and / or Au or be it.
  • the carrier 1 has a mounting portion 21 for the
  • Bonding area for connecting a dashed line indicated bonding wire has.
  • the carriers 1, 1 'each have a soldering area 20, 20', via which the carrier device 100 can be connected, for example, to contacts of a printed circuit board or a printed circuit board
  • solder Board can be soldered.
  • the dashed lines at the solder regions 20, 20 ' indicate the usual areas of the carriers 1, 1' at which solder after soldering of the carrier device 100 can and should be present. However, it is usually not desirable if solder also creeps along the carrier 1, 1 'to other areas.
  • the shown shape of the carriers 1, 1 ' is to be understood as purely exemplary and not restrictive. On the contrary, the carriers 1, 1 'can also have any other form which is adapted and suitable to the respective requirements. As an alternative to the embodiment shown, the carrier device 100 may also have only one carrier 1 or more than the two carriers 1, 1 'shown, wherein also on several carriers
  • Mounting areas may be arranged and, for example, at least one carrier may have more than one mounting area and / or more than one soldering area.
  • the carrier device 100 has a cover material 2, which in the embodiment shown is made of epoxy or a silicone or a silicone-epoxy hybrid material and, except for the solder regions 20, 20 ', the carriers 1, 1' are completely covered.
  • the covering material 2 is designed as a housing which serves for the encapsulation of the semiconductor chip 3.
  • the cover 2 is designed as a housing which serves for the encapsulation of the semiconductor chip 3.
  • the covering material 2 can, for example, in the region of the mounting region 21 a recess or opening
  • the covering material may, for example, also be arranged as a frame around the mounting region 21 and, for example, also as a
  • an interface 10, 10' which may have Permeationspfade and creepage paths for solder due to the respective material properties and manufacturing processes, so that when soldering the carrier device 100, for example, to a circuit board solder from the soldering areas 20, 20 'along the boundary surfaces 10, 10' in the direction of the mounting portion 21 can creep, as indicated by the arrows 9.
  • the carrier 1 To prevent unwanted covering of the carrier 1, 1 'under the cover 2 with solder, the carrier 1 at the
  • Mounting region 21 'at the further interface 10' has a further solder barrier 4 ', wherein both
  • solder barriers 4, 4 are explained in connection with FIGS. 2A to 5.
  • Masking material 4 are executed in the embodiment shown purely by way of example and may alternatively or additionally have one or more features as described above in the general part.
  • an electronic component may include a carrier device 100 according to the aforementioned embodiment and a
  • an optoelectronic component may comprise a carrier device 100 according to the aforementioned embodiment and an optoelectronic semiconductor chip 3 on the carrier device 100, for example a light emitting diode, a laser diode or a photodiode.
  • FIGS. 2A to 5 are various ones
  • the carrier 1 has a coating 11 which, except in FIG.
  • Palladium- and / or gold-containing alloy in particular a PdAu or a NiPdAu alloy, which on the one hand protects the carrier 1 from harmful influences and on the other hand a high wettability, especially for tin-containing
  • Soldering 20 can be increased with advantage.
  • Solder barrier 4 to a material which has a lower wettability by the solder than the carrier 1 or the coating 11.
  • solder barrier 4 in the embodiment shown silver or is made of silver, which for solder, in particular for tin-based solder, a lower wettability compared to the PdAu or NiPdAu coating 11 of the carrier 1 has.
  • the solder barrier may also be nickel, which can provide a good creep stop for solder.
  • a creep of a solder indicated by the arrow 9 can occur at the interface 10 from the soldering region 20 to the mounting region 21 be reduced or completely prevented. While in the exemplary embodiment according to FIG. 2A the solder barrier 4 is arranged on the coating 11, the solder barrier 4 according to the other one can be arranged
  • Embodiment in Figure 2B also be formed in the coating 11.
  • Solder barrier 4 a depression.
  • the recess is particularly in connection with the previously described
  • Coating 11 on the support which has a high wettability for solder, advantage.
  • Mounting area 21 can be achieved.
  • the coating 11 has a layer sequence of a plurality of layers 11 ', 11'', of which the layer 11', for example, a nickel layer and the layer 11 '' above can be a PdAu or an Au layer , There may also be other or different layers on the layer 11 '' be arranged.
  • the solder barrier 4 is formed in the embodiment shown as a recess which extends only through a portion of the coating 11 and protrudes into the coating 11 to the layer 11 ''. Similar to the exemplary embodiments of FIGS. 2A and 2B, the nickel of the layer 11 '' thus exposed at the interface 10 in the region of the solder barrier 4 can, due to its
  • Solder barrier 4 has a material which is soluble in a solder, so that the material of the solder barrier 4 is dissolved in the solder, as indicated by the arrows 49, when the solder along the interface 10 to
  • solder barrier creeps.
  • Covering material 2 has a lower creeping speed and a higher wetting of the carrier 1 or the coating 11 than the solder alone. This reduces the creeping speed of the solder along the indicated by the arrow 9 creepage path at the interface 10 or may even come to a complete halt.
  • the embodiments shown in particular depend on the materials of the carrier 1, optionally the coating 11 and the solder, the creep speed of the solder and the strength of the creep effect or the
  • solder barrier 4 particularly preferably a length along the extension direction from the soldering area 20, 20' to the mounting area 21 of greater than or equal to 50 and less than or equal to 300 ym to a
  • solder barrier 4, 4 'to be in the form of a three-dimensional structure, for example as an elevation, instead of a layer
  • solder barrier 4, 4 'to be arranged on further surfaces of the carrier 1, 1'.
  • solder barrier 4, 4 ' can also protrude at least partially from the cover material 2, as shown in FIG.
  • solder barrier 4, 4 ' also completely outside the
  • Covering material 2 to be arranged and adjacent to the interface 10, 10 '(not shown).
  • solder barriers 4, 4 'and / or combinations of the previously described solder barriers 4, 4' can also be arranged on the carrier 1.
  • the carrier 1 For example, the
  • Solder barriers 4, 4 ' also be formed in multiple stages. This may in particular mean that a plurality of identical or different solder barriers 4, 4 'one behind the other between the respective soldering area 20, 20' and the respective
  • solder barriers 4, 4 ' according to the embodiments shown not only at the interface 10, 10 'may be arranged, for example, but also be formed circumferentially around the respective carrier 1, 1', so that all sides a solder stop on the carriers 1, 1 'can be effected.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Led Device Packages (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Light Receiving Elements (AREA)

Abstract

L'invention concerne un dispositif support pour une puce semi-conductrice (3) comportant un support métallique (1) pouvant être métallisé et/ou soudé, présentant une zone de montage (21) pour la puce semi-conductrice (3) et une zone de soudage (20). Le support (1) est au moins partiellement recouvert d'un matériau de recouvrement (2). Une barrière pour métal d'apport (4) est disposée entre la zone de soudage (20) et la zone de montage (21) sur une interface (10) entre le support (1) et le matériau de recouvrement (2). L'invention concerne également un composant électronique et un composant optoélectronique.
EP11748290.1A 2010-07-16 2011-06-27 Dispositif support pour une puce semi-conductrice, composant électronique comportant un dispositif support et composant optoélectronique comportant un dispositif support Withdrawn EP2593974A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102010027313A DE102010027313A1 (de) 2010-07-16 2010-07-16 Trägervorrichtung für einen Halbleiterchip, elektronisches Bauelement mit einer Trägervorrichtung und optoelektronisches Bauelement mit einer Trägervorrichtung
PCT/EP2011/060742 WO2012007271A2 (fr) 2010-07-16 2011-06-27 Dispositif support pour une puce semi-conductrice, composant électronique comportant un dispositif support et composant optoélectronique comportant un dispositif support

Publications (1)

Publication Number Publication Date
EP2593974A2 true EP2593974A2 (fr) 2013-05-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP11748290.1A Withdrawn EP2593974A2 (fr) 2010-07-16 2011-06-27 Dispositif support pour une puce semi-conductrice, composant électronique comportant un dispositif support et composant optoélectronique comportant un dispositif support

Country Status (7)

Country Link
US (1) US9076781B2 (fr)
EP (1) EP2593974A2 (fr)
JP (1) JP2013532898A (fr)
KR (1) KR20130083898A (fr)
CN (1) CN103003965B (fr)
DE (1) DE102010027313A1 (fr)
WO (1) WO2012007271A2 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6322828B2 (ja) * 2014-02-07 2018-05-16 ローム株式会社 発光モジュールおよび発光装置
DE102014102810A1 (de) * 2014-03-04 2015-09-10 Osram Opto Semiconductors Gmbh Herstellung optoelektronischer Bauelemente
JP6662610B2 (ja) * 2015-11-12 2020-03-11 旭化成エレクトロニクス株式会社 光センサ装置
DE102016103862A1 (de) 2016-03-03 2017-09-07 Osram Opto Semiconductors Gmbh Optoelektronische Leuchtvorrichtung, Träger für einen optoelektronischen Halbleiterchip und optoelektronisches Leuchtsystem
DE102017105235B4 (de) * 2017-03-13 2022-06-02 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Bauelement mit Verstärkungsschicht und Verfahren zur Herstellung eines Bauelements
CN115632304A (zh) * 2022-09-30 2023-01-20 青岛海信激光显示股份有限公司 发光芯片和激光器

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4183611A (en) * 1976-05-13 1980-01-15 Amp Incorporated Inlaid contact
JPS61107751A (ja) 1984-10-30 1986-05-26 Nec Kansai Ltd 樹脂モ−ルド型半導体装置
US4950623A (en) * 1988-08-02 1990-08-21 Microelectronics Center Of North Carolina Method of building solder bumps
US5973337A (en) * 1997-08-25 1999-10-26 Motorola, Inc. Ball grid device with optically transmissive coating
JP3548673B2 (ja) 1997-08-28 2004-07-28 シャープ株式会社 電子回路素子
JP2000068303A (ja) 1998-08-24 2000-03-03 Sony Corp 半導体装置の製造方法
JP3871820B2 (ja) * 1998-10-23 2007-01-24 ローム株式会社 半導体発光素子
DE10010979A1 (de) * 2000-03-07 2001-09-13 Bosch Gmbh Robert Elektrische Schaltung und Substrat hierzu
US6545344B2 (en) * 2000-06-27 2003-04-08 Texas Instruments Incorporated Semiconductor leadframes plated with lead-free solder and minimum palladium
DE10351120A1 (de) * 2003-11-03 2005-06-09 eupec Europäische Gesellschaft für Leistungshalbleiter mbH Lötstopbarriere
US7615873B2 (en) * 2004-04-21 2009-11-10 International Rectifier Corporation Solder flow stops for semiconductor die substrates
US7474286B2 (en) 2005-04-01 2009-01-06 Spudnik, Inc. Laser displays using UV-excitable phosphors emitting visible colored light
US7365371B2 (en) * 2005-08-04 2008-04-29 Cree, Inc. Packages for semiconductor light emitting devices utilizing dispensed encapsulants
TWI367552B (en) * 2007-08-22 2012-07-01 Everlight Electronics Co Ltd Soldering process for electrical component and apparatus thereof
US20100102436A1 (en) * 2008-10-20 2010-04-29 United Test And Assembly Center Ltd. Shrink package on board
DE102008053489A1 (de) * 2008-10-28 2010-04-29 Osram Opto Semiconductors Gmbh Trägerkörper für ein Halbleiterbauelement, Halbleiterbauelement und Verfahren zur Herstellung eines Trägerkörpers
DE102009008738A1 (de) * 2009-02-12 2010-08-19 Osram Opto Semiconductors Gmbh Halbleiteranordnung und Verfahren zum Herstellen einer Halbleiteranordnung

Also Published As

Publication number Publication date
KR20130083898A (ko) 2013-07-23
CN103003965B (zh) 2016-03-16
JP2013532898A (ja) 2013-08-19
US20130256862A1 (en) 2013-10-03
CN103003965A (zh) 2013-03-27
DE102010027313A1 (de) 2012-01-19
US9076781B2 (en) 2015-07-07
WO2012007271A3 (fr) 2012-03-08
WO2012007271A2 (fr) 2012-01-19

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