EP2553725A1 - Dispositif imageur cmos a architecture en trois dimensions - Google Patents
Dispositif imageur cmos a architecture en trois dimensionsInfo
- Publication number
- EP2553725A1 EP2553725A1 EP11709958A EP11709958A EP2553725A1 EP 2553725 A1 EP2553725 A1 EP 2553725A1 EP 11709958 A EP11709958 A EP 11709958A EP 11709958 A EP11709958 A EP 11709958A EP 2553725 A1 EP2553725 A1 EP 2553725A1
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- EP
- European Patent Office
- Prior art keywords
- pixel
- substrate
- imaging device
- circuit
- pixels
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/1464—Back illuminated imager structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/79—Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H01L27/144—Devices controlled by radiation
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H—ELECTRICITY
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14632—Wafer-level processed structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/14643—Photodiode arrays; MOS imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
Definitions
- the invention relates to the field of imaging devices, or image sensors, CMOS type and made in 3D technology (in three dimensions), that is to say comprising an architecture formed of several superimposed substrates.
- the invention is particularly applicable to CMOS imaging devices made in silicon technology, comprising pixels of small sizes, and capable of performing optical detection in the visible range.
- a CMOS imaging device is an integrated circuit, conventionally consisting of a matrix of pixels and a control electronics.
- Each pixel comprises a photodetector for converting the energy of the incident photons received by the pixel into electron-hole pairs, an integrating capacitance which stores the generated charges and a plurality of MOS transistors.
- the control electronics is responsible in particular to evacuate in series, that is to say pixel by pixel, the electrical information delivered by each pixel to the output of the matrix.
- a CMOS imaging device is made in the form of a 2D chip (in two dimensions) comprising all of its elements (pixels and control electronics) on a single semiconductor substrate, for example based on silicon.
- An integrated circuit made in the form of a 3D chip has the particular advantage, compared to a similar integrated circuit but realized in the form of a 2D chip, to reduce the length of the necessary electrical interconnections, thus reducing the transfer times data between the different elements of the chip.
- 3D technology makes it possible to increase the number of interconnections between the chips, and therefore to have a communication that is no longer series but massively parallel between the superposed chips.
- the photodiodes are made at a first substrate which is stacked on a second substrate comprising the analog electronics of the pixels (photodiode reading circuits and pixel selection means), the second substrate being itself stacked on a third substrate on which is performed the digital signal processing electronics.
- These substrates are electrically connected to each other by through vias.
- the first substrate contains only the photodiodes, a ratio of 100% is obtained between the photodiode effective photodetection area and the total area of the pixels.
- An object of the present invention is to provide an imaging device having the advantages provided by a three-dimensional architecture and which is compatible with the production of small pixels and very high performance, particularly in terms of sensitivity. .
- an imaging device comprising at least:
- each pixel comprising at least one photodetector
- each read circuit comprising at least one charge conversion circuit intended to be delivered by at least one of the voltage photodetectors
- At least one electronic processing circuit able to process the voltages intended to be delivered by the read circuits
- the imaging device comprising at least a first substrate on which the pixels and the readout circuits are formed, and at least one second substrate, distinct from the first substrate, on which the electronic processing circuit is formed, the second substrate being electrically connected to the first substrate via at least one electrical interconnection forming a connection between the read circuits and the electronic processing circuit.
- first substrate and second substrate denote respectively a first layer of material and a second layer of material distinct from the first layer, for example based on at least one semiconductor material, and which are, in the imaging device according to the invention, electrically interconnected by at least one electrical interconnection and advantageously superimposed one above the other.
- the electronic processing circuit of the imaging device is associated with a plurality of pixels, which is very suitable for the processing that an image captured by the imaging device must undergo: analog-to-digital conversion of the signals delivered by the pixels, compression, detection of contours, detection of movements, etc.
- the operations performed by the processing circuit may correspond to the operations performed on the signals delivered by the read circuits, after these signals have been multiplexed.
- the imaging device also makes it possible to relax the stresses on the electrical interconnections between the first and second substrates. Indeed, for each pixel, all the elements directly connected to the reading node, that is, that is, the node at which the charges generated by the photodetector are converted into voltage, these elements forming the charge-to-voltage conversion circuit, are formed on the first substrate which also comprises the photodetectors, the connection to the second substrate by the electrical interconnection or interconnections being carried out downstream of this charge conversion.
- the imaging device according to the invention therefore comprises a three-dimensional architecture in which the performances, such as the signal / noise ratio obtained, are not degraded by the addition of a capacitance due to the electrical connection made between the two substrates. of the device.
- the imaging device according to the invention is also compatible with the production of pixels of larger sizes.
- the imaging device according to the invention can use existing pixel configurations for which optimization phases have been realized.
- the photodetectors and the analog electronics of the pixels such as the read circuit are preserved on the first substrate, the digital processing being performed at the second substrate.
- This design enables the realization of a 3D imaging device that can reuse, with a minimum of modifications, the optimized designs of existing pixels of 2D imaging devices.
- Each pixel may comprise one of the reading circuits electrically connected to the photodetector and to an output of said pixel.
- the imaging device may comprise charge transfer pixels, which are high sensitivity pixels, in which a charge transfer photodiode is associated with a transfer MOS transistor, these two elements being made on the same substrate.
- Each reading circuit comprises at least:
- a second MOS transistor or a charge amplifier forming the voltage-to-voltage conversion circuit of said read circuit.
- Each read circuit comprises all the elements directly connected to the reading node, that is to say the node on which the conversion of the charges into voltage takes place.
- these elements correspond at least to the transistor for charging and discharging the photodetector, and to the follower transistor Of voltage.
- these elements additionally comprise, with respect to those of a pixel 31, at least one other transfer MOS transistor, or of isolation, enabling direct integration of the charges. generated by the photodetector when discharging the junction capacitance of the photodetector.
- the read circuits are made on the first substrate, the read capabilities corresponding to all the capacitors connected to the gate of the second MOS transistor or the charge amplifier, are present in full on the first substrate.
- the capacitances formed by the electrical connections between the two substrates of the imaging device according to the invention do not add to the reading capabilities.
- junction capabilities of photodetectors form part of the reading capabilities but do not form all of these reading abilities.
- the capacitances formed by the electrical connections between the photodetectors and the MOS transistor or the charge amplifier are also part of the reading capabilities.
- Each pixel may furthermore comprise at least one isolation MOS transistor produced on the first substrate, between the photodetector of said pixel and the reading circuit associated with said photodetector.
- Each pixel may comprise one of the read circuits distinct from the read circuits of the other pixels.
- the imaging device may furthermore comprise at least one multiplexing circuit formed on the second substrate and capable of forming first pixel selection means, the reading circuits being able to be electrically connected to the electronic processing circuit via the multiplexing circuit. an output of the multiplexing circuit being connected to at least one input of the electronic processing circuit by at least one interconnection bus made on the second substrate.
- Each read circuit may be electrically connected to the second substrate by a separate electrical interconnection of the electrical interconnects connecting the other read circuits to the second substrate.
- the pixels can be arranged in matrix and the outputs of the pixels of the same column of the matrix can be electrically connected to each other by a connection bus made on the first substrate.
- connection bus may be electrically connected to a separate electrical interconnection of the electrical interconnections connected to the other connection buses and made between the first substrate and the second substrate, the interconnections electrical connectors that can electrically connect the connection buses to inputs of the multiplexing circuit.
- each pixel may be arranged in a matrix and the outputs of the pixels of the same column of the matrix may be electrically connected to each other by a connection bus made on the first substrate, the connection buses being electrically connectable to each other. others and the electrical interconnection, each pixel may further comprise at least one MOS transistor disposed between the read circuit of said pixel and the connection bus to which said pixel is connected and forming first pixel selection means.
- the imaging device may further comprise second pixel selection means cooperating with the first pixel selection means so that the electronic processing circuit receives successively as input the voltages intended to be delivered by the read circuits, the second means of selecting pixels that can be formed by the multiplexing circuit and / or by the first MOS transistor of the read circuit and / or by another MOS transistor formed on the first substrate and disposed between the read circuit of said pixel and the connection bus to which said pixel is connected.
- each pixel may comprise first pixel selection means arranged between the photodetector of said pixel and the read circuit, an output of the reading circuit being connectable to second pixel selection means cooperating with the first pixel selection means so that the electronic processing circuit receives successively at input the voltages intended to be delivered by the read circuits.
- the plurality of pixels may form a macropixel
- the imaging device may comprise a plurality of macropixels made on the first substrate and a plurality of electronic processing circuits made on the second substrate, each macropixel being electrically connectable to one of the electronic processing circuits. via at least one separate electrical interconnection that can electrically connect the first substrate to the second substrate.
- the electronic processing circuit (s) may be capable of performing at least one analog-to-digital conversion of the signals intended to be delivered by the pixel reading circuits.
- the one or more electrical interconnections may comprise electrically conductive balls electrically connecting electrical contacts of the first substrate to electrical contacts of the second substrate, and / or electrical contacts of the first substrate bonded by molecular adhesion to electrical contacts of the second substrate, and or through vias made through the first substrate and / or the second substrate.
- FIGS. 1 and 5 to 7 diagrammatically and partially show imaging devices, objects of the present invention, according to three different embodiments,
- FIGS. 2 to 4 show exemplary embodiments of reading circuits of a pixel of an imaging device, object of the present invention.
- FIG. 1 schematically and partially represents a imaging device 100 according to a first embodiment.
- the imaging device 100 comprises a first substrate 102, for example based on a semiconductor material such as silicon, on which is realized a detection circuit of the imaging device 100 formed by a plurality of pixels 104 arranged in the form of a matrix of n rows and m columns.
- the imaging device 100 has a much larger number of pixels 104, for example several million or tens of millions.
- the pixels 104 each have a square shape whose sides have a dimension substantially equal to or less than about 2 pm.
- Each pixel 104 comprises a photodetector, for example a photodiode 106, for converting the energy of incident photons received by each of the pixels 104 into electron-hole pairs.
- a photodetector for example a photodiode 106
- the photodetectors of the imaging device 100 could be phototransistors.
- Each pixel 104 of the imaging device 100 also comprises a reading circuit 108 of the charges generated by the photodiode 106.
- This reading circuit 108 comprises in particular a circuit ensuring the charging and discharging of the photodiode 106 as well as the conversion of the charges generated by the photodiode 106.
- each pixel 104 also comprises first pixel selection means making it possible, by sequentially selecting the pixels 104, to read sequentially the information detected by the different pixels of the imaging device 100.
- these first selection means comprise, in each pixel 104, a MOS transistor 110 enabling, when all the MOS transistors 110 of the same pixel line 104 are put in the on state, select this line and read the information of the pixels 104 of this line, that is to say to read the signals detected by the pixels 104 of this line.
- the rows of the pixel array 104 are read sequentially one after the other.
- these first pixel selection means are not formed by the MOS transistors 110 connected to the outputs. read circuits 108, but by a MOS transistor (referenced 122 on the examples shown in Figures 2 and 4) present in each read circuit 108 and can also be used to perform the charging and discharging of the photodetector 106 of the pixel 104.
- the imaging device 100 also comprises a second substrate 112 on which multiplexing circuits 114 and electronic processing circuits 116 are formed, the multiplexing circuits 114 being electrically connected to the electronic processing circuits 116 by means of buses 117 made on the second substrate 112.
- a single multiplexing circuit 114 and a single electronic processing circuit 116 connected together by a bus 117 are shown.
- the voltages delivered by the pixels 104 are routed to the multiplexing circuits 114 via buses 118 and electrical interconnections 120.
- the buses 118 are made on the first substrate 102 while the electrical interconnections 120 are made between the first substrate 102 and the second substrate 112.
- each pixel group 104 forming a "macropixel".
- Each macropixel can be associated with a circuit of multiplexing 114 and a clean electronic processing circuit 116.
- the pixels 104 represented in FIG. 1 are part of the same macropixel forming a matrix of 16 ⁇ 16 pixels, ie 256 pixels, of which only nine pixels 104 are represented in FIG. 1.
- each bus 118 being connected to an electrical interconnection 120.
- each macropixel of the imaging device 100 is thus electrically connected to the second substrate 112 via sixteen buses 118 connected to sixteen electrical interconnections 120, an electrical interconnection 120 for each column of pixels 104 of a macropixel.
- the pixel lines 104 of the imaging device 100 are sequentially addressed one after the other.
- each pixel 104 comprises or by one of the MOS transistors of the read circuit 108 of each pixel 104.
- a voltage corresponding to a signal detected by a pixel 104 is transmitted on each of the buses 118, then transmitted to the multiplexing circuit 114 via the electrical interconnections 120.
- the circuit of multiplexing 114 forms second pixel selection means for sequentially sending to the electronic processing circuit 116 the voltages received from each of the electrical interconnections 120.
- the MOS transistors forming the first pixel selection means cooperate with the multiplexing circuit. 114, which forms second pixel selection means, for the electronic processing circuit 116 to successively receive as input the voltages delivered by the read circuits 108 of each pixel 104.
- the electronic processing circuit 116 can achieve an analog - digital conversion of the received signals, and possibly other functions such as memory and / or a pre ⁇ digital processing on the voltages supplied by the pixels (e.g., a function image stabilization, video acceleration, motion detection, contour detection, data compression, ).
- the necessary space on the second substrate 112 for producing the electronic processing circuits 116 is related to the complexity of the function or functions implemented by these circuits 116. Thus, depending on the complexity of the function or functions performed by the circuits 116, it will be possible to reduce more or less the dimensions of the pixels 104 of the imaging device 100.
- the electrical interconnections 120 can be made in different ways.
- these electrical interconnections 120 may be formed by electrically conductive balls electrically connecting the electrical contacts of the first substrate 102 (these contacts forming the output pads of the buses 118) to electrical contacts of the second substrate 112 (these contacts forming input pads of the multiplexing 114).
- beads of electrically conductive material are first disposed on the contacts of one of the two substrates 102, 112, or distributed over the contacts of the two substrates 102, 112.
- the substrates 102, 112 are then positioned so that the electrical contacts of the two substrates are arranged opposite one another, separated by the balls of electrically conductive material.
- a heat treatment is then performed to melt the balls, the two substrates being welded to each other via the electrical interconnections 120 formed by the molten conductive material and then solidified beads.
- the electrical interconnections 120 may be formed by a molecular bonding made between the two substrates 102, 112, the electrical contacts of the two substrates 102 and 112 then being secured to each other by this bonding.
- a molecular bonding is obtained by first realizing a planarization of the two substrates, and then bringing the two substrates into contact. Annealing makes it possible to achieve solidarity between the two substrates 102 and 112.
- the electrical interconnects 120 may also be formed by through vias formed through the substrates 102 and 112.
- the electrical interconnections 120 are formed by means of balls of electrically conductive material or by molecular bonding of the two substrates 102 and 112, the front face of the first substrate 102, on which surface the electronic elements of the pixels 104 are made, is disposed facing the second substrate 112 (because the electrical contacts of the two substrates 102, 112 must be arranged opposite each other).
- the first substrate 102 should be thinned so that the photodetection can be carried out from the rear face of the first substrate 102 which is intended to be illuminated. This thinning allows the light to pass through the first substrate 102 to illuminate the photodiodes 106 of the pixels 104.
- a first exemplary embodiment of a pixel 104 comprising a photodiode 106 and a reading circuit 108 electrically connected to the photodiode 106 and the pixel line selection MOS transistor 110 is shown in FIG.
- the pixel 104 is an active pixel type 3T, that is to say comprising an analog electronics formed by three MOS transistors.
- a first MOS transistor 122 has its source and its drain respectively connected to the photodiode 106 and to a potential VDD.
- a second MOS transistor 124 has its drain connected to the potential VDD, its source being connected to the drain of the pixel line selection transistor 110 which forms the third MOS transistor of this type 3T pixel.
- the gate of the second transistor 124 is connected to the source of the first transistor 122.
- the first MOS transistor 122 here forms a means of charging and discharging the photodiode 106 and resets the pixel when the first MOS transistor 122 is turned on, the voltage across the junction capacitance of the photodiode 106 being then set to VDD.
- the second MOS transistor 124 forms a voltage follower converting the charges stored in the junction capacitance of the photodiode 106 into a voltage.
- the MOS transistor 110 for selecting pixels makes it possible to deliver, when the line on which this pixel 104 is located, that is to say by putting this MOS transistor 110 in the on state, the voltage provided by the second MOS transistor 124 on the bus 118.
- the pixel 104 shown in FIG. 2 forms an active pixel because its reading circuit 108 performs both reading of the charges generated by the photodiode 106 and an amplification of the signal read through the second MOS transistor 124 which forms a voltage follower and which converts the charges generated by the photodiode 106 into a voltage.
- the pixel 104 shown in FIG. 2 does not include the pixel line selection MOS transistor 110.
- the pixel line selection function is filled by the first MOS transistor 122, the discharge of the photodiode 106 taking place only when it is sought to address the pixel line on which this pixel 104 is located. .
- FIG. 1 A second exemplary embodiment of a pixel 104 comprising a photodiode 106 and a read circuit 108 connected to the photodiode 106 and to the pixel line selection MOS transistor 110 is shown in FIG.
- the pixel 104 is an active pixel of the CTIA or charge amplifier type.
- the photodiode 106 is connected to the negative input of a charge amplifier 126, a bias voltage being applied to the positive input of the charge amplifier 126.
- the output of the charge amplifier 126 is connected to its negative input via a capacitor 128 and a first MOS transistor 130, these two elements being connected in parallel with each other.
- the output of the charge amplifier 126 is also connected to the source of the pixel line selection MOS transistor 110.
- the first MOS transistor 130 here forms a means for charging and discharging the capacitor 128.
- the charge / voltage conversion is carried out here by the charge amplifier. Associated with the capacitor 128.
- the MOS transistor 110 makes it possible to deliver, when the line on which this pixel 104 is located, by putting the first MOS transistor 110 in the on state, the voltage being output of the charge amplifier 126 on the bus 118.
- the pixel 104 shown in FIG. 3 also forms an active pixel.
- the pixel line selection MOS transistor 110 which role can be filled by the first MOS transistor 130, similarly to the first MOS transistor 122 as previously described.
- FIG. 4 A third exemplary embodiment of a pixel 104 comprising a photodiode 106 and a read circuit 108 connected to the photodiode 106 and to the first pixel line selection MOS transistor 110 is shown in FIG. 4.
- the pixel 104 is an active pixel type 4T, that is to say comprising an analog electronics formed by four MOS transistors.
- the reading circuit 108 represented in FIG. 4 comprises the first MOS transistor 122 and the second MOS transistor 124, whose roles are similar to those of FIG. previously described in connection with the example of Figure 2.
- the pixel 104 of this third exemplary pixel embodiment 104 further comprises an additional MOS transistor 132 placed between the photodiode 106 and the read circuit 108.
- This MOS transistor 132 provides an isolation between the reading circuit 108 and the photodiode 106, and makes it possible to directly integrate the charges generated by the photodiode 106 during the discharge of the junction capacitance of the photodiode 106 without having to reset the photodiode 106 to obtain the measurement made by the pixel.
- FIG. 5 shows schematically and partially an imaging device 200 according to a second embodiment.
- the pixels 204 of the imaging device 200 do not comprise a pixel line selection MOS transistor 110, and the output of each reading circuit 108 of each pixel 120 is connected directly to an electrical interconnection 120 forming a direct electrical connection between this pixel output 204 and the multiplexing circuit 114.
- the multiplexing circuit 114 has as much of inputs that pixels 204, and includes an electronics for performing the multiplexing of the voltages from all the pixels 204 which are simultaneously sent to the input of the multiplexing circuit 114.
- pixels 104 previously described with reference to FIGS. 2 to 4 may be applied for the realization of the pixels 204 of the imaging device 200, the only difference being the absence of the pixel line selection MOS transistor 110. .
- FIG. 6 shows schematically and partially an imaging device 300 according to a third embodiment.
- each pixel 304 of the imaging device 300 comprises another pixel selection MOS transistor 306 for selecting one of the pixel columns 304.
- each pixel 304 of a macropixel of the imaging device 300 can be individually addressed by turning on the MOS transistors 110 and 306 of the pixel in question. Since the imaging device 300 makes it possible to individually address the pixels 304, the buses 118 of the same macropixel are connected. electrically to each other and the electrical connection of a macropixel to the second substrate 112 is achieved through a single electrical interconnection 120.
- the electrical interconnection 120 is directly connected to the electronic processing circuit 116, the multiplexing circuit used in the imaging devices 100 and 200 no longer useful here since the measurements made by the pixels 304 of the same macropixel are sent sequentially, pixel by pixel, in the electronic processing circuit 116 associated with this macropixel.
- the different embodiments of the reading circuits 108 previously described in connection with FIGS. 2 to 4 also apply to the imaging device 300.
- FIG. 7 schematically and partially shows an imaging device 400 according to a fourth embodiment.
- each pixel 404 of the imaging device 400 are passive pixels of the 1T type. Indeed, each pixel 404 comprises a photodiode 106 and a MOS transistor 110 of pixel line selection.
- the pixels 404 of the imaging device 400 do not include read circuits made within the pixels 404.
- the imaging device 400 comprises read circuits 108 common to several pixels 404. In the example of FIG. 7, each read circuit 108 is common to two pixels 404. It will be preferred not to connect more than three pixels 404 to one and the same circuit. reading 108.
- the reading circuit 108 does not simultaneously receive the charges delivered by the two photodiodes 106 which are connected to the read circuit 108.
- An output of the read circuit 108 is connected to another MOS transistor 406 serving as a pixel column selection means.
- each read circuit 108 is connected to an interconnection 120 which is specific to it.
- the pixel selection is performed at the first substrate (by the MOS transistors 110 and 406), it is possible to connect some or all of the sources of the transistors 406 to each other, connecting the outputs of the transistors 406 to each other. reading circuits 108, in order to minimize the number of interconnections 120 to be made between the first substrate 102 and the second substrate 112.
- each macropixel is associated with a separate electronic processing circuit, it is possible for one or more electronic processing circuits 116 and / or one or more multiplexing circuits 114 to be common to several macropixels of the imaging device.
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Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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FR1052222A FR2958079B1 (fr) | 2010-03-26 | 2010-03-26 | Dispositif imageur cmos a architecture en trois dimensions |
PCT/EP2011/054594 WO2011117376A1 (fr) | 2010-03-26 | 2011-03-25 | Dispositif imageur cmos a architecture en trois dimensions |
Publications (1)
Publication Number | Publication Date |
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EP2553725A1 true EP2553725A1 (fr) | 2013-02-06 |
Family
ID=42988237
Family Applications (1)
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EP11709958A Withdrawn EP2553725A1 (fr) | 2010-03-26 | 2011-03-25 | Dispositif imageur cmos a architecture en trois dimensions |
Country Status (4)
Country | Link |
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US (1) | US8969773B2 (fr) |
EP (1) | EP2553725A1 (fr) |
FR (1) | FR2958079B1 (fr) |
WO (1) | WO2011117376A1 (fr) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5963421B2 (ja) * | 2011-11-17 | 2016-08-03 | オリンパス株式会社 | 固体撮像装置および撮像装置 |
US10297630B2 (en) * | 2012-06-18 | 2019-05-21 | Forza Silicon Corporation | Pinned charge transimpedance amplifier |
DE102013110695A1 (de) * | 2012-10-02 | 2014-04-03 | Samsung Electronics Co., Ltd. | Bildsensor, Verfahren zum Betreiben desselben und Bildverarbeitungssystem mit demselben |
US9153616B2 (en) * | 2012-12-26 | 2015-10-06 | Olympus Corporation | Solid-state imaging device and imaging device with circuit elements distributed on multiple substrates, method of controlling solid-state imaging device, and imaging device with circuit elements distributed on multiple substrates |
TWI659652B (zh) * | 2013-08-05 | 2019-05-11 | 新力股份有限公司 | 攝像裝置、電子機器 |
JP6463944B2 (ja) * | 2013-11-25 | 2019-02-06 | キヤノン株式会社 | 撮像素子、撮像装置及び携帯電話機 |
DE102014204647A1 (de) * | 2014-03-13 | 2015-09-17 | Robert Bosch Gmbh | Optische Erfassungsvorrichtung und Verfahren zum Herstellen einer optischen Erfassungsvorrichtung |
Citations (1)
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JP2009170448A (ja) * | 2008-01-10 | 2009-07-30 | Nikon Corp | 固体撮像素子 |
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CN101010944B (zh) * | 2004-09-02 | 2010-06-16 | 索尼株式会社 | 摄像装置及摄像结果的输出方法 |
JP4769535B2 (ja) * | 2005-10-06 | 2011-09-07 | 富士フイルム株式会社 | 固体撮像素子 |
US20070096233A1 (en) * | 2005-10-13 | 2007-05-03 | In Gyun Jeon | Cmos image sensor |
FR2904143A1 (fr) * | 2006-07-24 | 2008-01-25 | St Microelectronics Sa | Capteur d'images eclaire par la face arriere a temperature de substrat uniforme |
US8049256B2 (en) | 2006-10-05 | 2011-11-01 | Omnivision Technologies, Inc. | Active pixel sensor having a sensor wafer connected to a support circuit wafer |
US7781716B2 (en) * | 2008-03-17 | 2010-08-24 | Eastman Kodak Company | Stacked image sensor with shared diffusion regions in respective dropped pixel positions of a pixel array |
US7858915B2 (en) * | 2008-03-31 | 2010-12-28 | Eastman Kodak Company | Active pixel sensor having two wafers |
-
2010
- 2010-03-26 FR FR1052222A patent/FR2958079B1/fr not_active Expired - Fee Related
-
2011
- 2011-03-25 EP EP11709958A patent/EP2553725A1/fr not_active Withdrawn
- 2011-03-25 US US13/637,223 patent/US8969773B2/en not_active Expired - Fee Related
- 2011-03-25 WO PCT/EP2011/054594 patent/WO2011117376A1/fr active Application Filing
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009170448A (ja) * | 2008-01-10 | 2009-07-30 | Nikon Corp | 固体撮像素子 |
Also Published As
Publication number | Publication date |
---|---|
US8969773B2 (en) | 2015-03-03 |
WO2011117376A1 (fr) | 2011-09-29 |
FR2958079A1 (fr) | 2011-09-30 |
US20130048832A1 (en) | 2013-02-28 |
FR2958079B1 (fr) | 2012-09-21 |
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