EP2529482A1 - Amplificateur différentiel ayant une plage de tension d'entrée "rail-to-rail" - Google Patents

Amplificateur différentiel ayant une plage de tension d'entrée "rail-to-rail"

Info

Publication number
EP2529482A1
EP2529482A1 EP11711834A EP11711834A EP2529482A1 EP 2529482 A1 EP2529482 A1 EP 2529482A1 EP 11711834 A EP11711834 A EP 11711834A EP 11711834 A EP11711834 A EP 11711834A EP 2529482 A1 EP2529482 A1 EP 2529482A1
Authority
EP
European Patent Office
Prior art keywords
voltage
rail
input
differential
differential input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP11711834A
Other languages
German (de)
English (en)
Inventor
Alexander Frey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP2529482A1 publication Critical patent/EP2529482A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/4521—Complementary long tailed pairs having parallel inputs and being supplied in parallel

Definitions

  • the invention relates to a differential amplifier with a rail-to-rail input voltage range.
  • Differential amplifiers represent an important class of basic circuit blocks for realizing analog circuits. Differential amplifiers are generally implemented in CMOS (Complementary Metal Oxide Semiconductor) or else in bipolar technology as an operational or transconductance amplifier. The properties are specified by various parameters such as power consumption, bandwidth, gain, noise characteristics and so on.
  • CMOS Complementary Metal Oxide Semiconductor
  • a special feature of differential amplifiers also represents the input voltage range that can be processed by the circuit with respect to the supply voltage of the circuit. Without speziel- le circuit measures the input voltage range ⁇ typically is less than the supply voltage range.
  • Figure 1 illustrates the basic problem in the realization of a rail-to-rail input voltage range using the example of differential input stages of a differential amplifier in conventional CMOS circuit technology.
  • the prior art as well as the invention will be explained below with reference to a realization in CMOS technology. In a similar way, however, a realization in bipolar technology is possible.
  • FIG. 1 schematically shows an implementation of a differential input stage 1, with a parallel peeled ⁇ th pair of n-MOS transistors 2a and 2b, which are connected via a current source 3 to a supply voltage rail 4, which leads a low supply voltage VSS.
  • This circuit makes it possible to handle high voltage level, especially in the area of a high level VDD of the supply voltage Ver ⁇ .
  • the circuit arrangement is not operational, as the control voltage to the control terminals of the transistors 2a and 2b no longer sufficient to maintain the Transis ⁇ motors 2a and 2b in the required analog operating to operate .
  • an input differential stage 1 ' can be realized with a parallel-connected pair of p-MOS transistors 2a' and 2b ', which are connected via a current source 3' to a supply voltage rail 5 the high supply voltage VDD ⁇ leads are connected.
  • the supply voltage rails are often also called
  • input levels are processed in the supply voltage of the p-MOS transistor pair in the region of the low level VSS, whereas the input level at the Be ⁇ rich of the high level VDD of the supply voltage processed by the n-MOS transistor pair.
  • average levels can in principle be processed by both input stages.
  • a central task of a differential input stage is the provision of a desired input slope or
  • Transconductance g m which represents a so-called small signal parameter.
  • an input voltage signal is converted into a current signal, which is then converted back into a réellestu ⁇ fe of the differential amplifier through a load element in a comparable reinforced voltage signal.
  • the input ⁇ transconductance g m is crucial for basic circuit characteristics, such as gain or control stability. Accordingly, the control and Dimensio ⁇ discrimination of this parameter is in the design process to a crucial importance. A desired, as constant as possible
  • Value for the input slope g m is set in a conventional manner via bias conditions in a suitable operating point. This is done separately for rail-to-rail Differenzverstär ⁇ ker for the n-MOS branch and the p-MOS branch.
  • FIG. 2 shows such a circuit arrangement, for example, from the publications JH Huijsing et al. "Low-voltage operational amplifier with rail-to-rail input and output ranges", IEEE J. Solid State Circuits, vol 20, no. 6, pages 1144-1150, 1985 and M. Augustyniak et al. , "A 24x16 CMOS-based chronocoloumetric dna microarray", Tech Dig.
  • the transistors Tu, Ti 2, T13 and T i4 which are executed by way of example as MOSFETs (metal oxide semiconductor field-effect transistor), such ver switches ⁇ in a known manner, that they complementary differential input stages ei ⁇ nes classic rail-to Train differential amplifier.
  • a first differential input stage 11-P (p-differential input stage) formed from the transistors Tu and T 1 2 is fed from a first current source 12-P via a first current mirror 13-P, which is realized by transistors T 2 i and T 22. supplied with a first bias current I p .
  • the first current source 12-P is supply voltage rail to an unillustrated first Versor- connected which carries a high supply voltage VDD versor ⁇ .
  • Current source 12-N via a second current mirror 13-N, which is rather realized by transistors 31 and T 32, supplied with a second bias current I n .
  • a third current mirror 14 which is formed by the transistor T 2 i in conjunction with a transistor T 23, a replica-p differential input stage 15, which is formed from transistors T15 and T16 and which consists of the transistors T 2 i and T 22 formed first differential input stage 11-P exactly replaces supplied with the first bias current I p .
  • the second current source 12-P is connected to a second supply voltage rail, not shown, which leads to a low supply voltage VSS.
  • the replica-p differential input stage 15 is connected to the control terminals of the transistors 31 and T 32.
  • the circuit is initially operated exclusively via the first differential input stage 11-P.
  • the second differential ⁇ input stage 11-N is turned off because the second bias current I n flows through the transistor T 4i .
  • This is achieved 42 and 41 ⁇ a ge ⁇ suitable dimensioning of the current mirror chain ⁇ 2, T 23, T.
  • the transistor T 22 is driven out of its saturation region and the current and thus also the input slope g m are reduced.
  • the decreasing current in the replica-p differential input stage 15 leads to a decreasing control current at the transistor T 4i via the transistor T 42, which in turn results in less bias current I n of the second differential input stage 11-N flowing away via the transistor T41 and thus more bias current to operate the second differential input stage 11-N is available.
  • the circuit arrangement according to FIG. 2 is therefore based on the principle of compensating the decreasing input slope g m in the first differential input stage 11-P by an increasing input slope in the second differential input stage 11-N.
  • the disadvantage here is that for this purpose a relatively complex circuit ⁇ tion scheme is required, in particular, the replica p-differential input stage also has a large space requirement, which also leads to increased costs.
  • the circuit arrangement according to FIG. 2 leads to a profile of the input slope g m over the input voltage, as shown in FIG. It is clear that yields in a transition region between the operation of the first differential input stage 11-P and the second differential input stage 11-N in the illustrated example, in a range between about 2 and 2.5 volts, a significant elevation of the input ⁇ steepness which is very disadvantageous, for example with regard to the control stability.
  • the invention is therefore based on the object to provide a differential amplifier with a rail-to-rail input voltage range, which ensures with simple circuitry means as constant as possible input slope over the entire input voltage range.
  • This object is achieved by a differential amplifier with a rail-to-rail input voltage range having
  • a first differential input stage for amplifying a
  • differential input voltage signal having a pair of first transistors connected to the first supply voltage rail via a first current source
  • a second differential input stage for amplifying the differential input voltage signal which comprises a pair of second transistors complementary to the first transistors. having sistoren, which is connected via a second current source to the second supply voltage rail, and - switching means which th the first differential input stage switch off ⁇ and the second differential input stage switching on, when the voltage value of the input voltage signal exceeds a predetermined first voltage threshold value at an increasing input voltage, and which Turn off the second differential input stage and turn on the first differential ⁇ input stage when the voltage value of the input voltage signal falls below a predetermined second voltage threshold, which is above the firstistsschwell learners with decreasing input voltage.
  • the switching means comprises a first controllable switching element which is connected between the first current source and the first supply voltage ⁇ rail, a second controllable scarf Tele ⁇ ment, which is connected between the second current source and the second supply voltage rail, and a HystE ⁇ resebehafteten comparator whose output is connected to the control inputs of the first and second switching element, on.
  • the switching elements are advantageously designed as Transisto ⁇ ren.
  • An embodiment of the invention provides that the comparator has adjustable voltage threshold values.
  • the differential amplifier according to the invention can be adapted to specific requirements of different concrete applications and can thus be used universally.
  • the input of the comparator is connected to a positive voltage input of the differential input stages, which leads to a further simplification of the circuit topology.
  • FIG. 1 is a schematic representation of an n-MOS and a p-MOS differential input stage of a differential amplifier ⁇ kers according to the prior art
  • Fig. 2 is a schematic representation of a rail-to-rail Dif ⁇ ferenz amplifier according to the prior art
  • Fig. 3 is a graphical representation of the input slope in
  • Fig. 4 is a graphical representation of the phase margin in Ab ⁇ dependence on the input voltage for the differential amplifier according to Figure 2,
  • Fig. 5 is a schematic representation of an inventive
  • Fig. 7 is a graphical representation of the phase margin in Ab ⁇ dependence on the input voltage for the inventive differential amplifier according to Figure 5.
  • a switching means 50 which includes a first controllable switching element 51 in the form of a transistor T 5 i, a second controllable switching element 52 in the form of a transistor T 5 2 and a hysteresis comparator 53.
  • the first switching element 51 is connected between the first current source 12-P and the first supply voltage rail, not shown
  • the second switching element 52 is connected between the second current source 12-N and the second supply voltage rail, not shown.
  • the output of the comparator 53 is connected to the control inputs of the first and second switching elements 51 and 52, respectively.
  • the input of the comparator 53 is connected to the positive voltage input "+" of the differential input stages.
  • the first differential input stage 11-P is to switched ⁇ and the second differential input stage 11-N is ⁇ turned on when the voltage value of the input voltage signal exceeds the predetermined first voltage threshold Viow with increasing input voltage, and the second Differenzein ⁇ grade 11-N turned off and the first Differential input ⁇ stage 11-P is turned on when the voltage value of the input output voltage signal falls below the predetermined second voltage threshold V h i gh with falling input voltage, where V high is above Vi ow .
  • FIG. 6 shows the input slope as a function of the input voltage when the two complementary differential input stages 11-P and 11-N are considered separately.
  • Characteristic 60 shows the course for the p-MOS branch and characteristic 61 the course for the n-MOS branch.
  • the phase reserve also shows a significantly improved course compared to the prior art (compare FIG.
  • the nominal case tm typically mean
  • corner cases so-called "corner cases” darge ⁇ represents.
  • the slump for the inventive scarf ⁇ processing arrangement to 2 ° can (77 ° to 75 °). Consequently, the differential amplifier according to the invention has a significantly improved control stability.
  • the simplified circuit scheme compared to the prior art also leads to a power saving through the elimination of current paths and in particular the elimination of the replica differential input stage leads to a significant area and thus cost savings.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

L'invention concerne un amplificateur différentiel ayant une plage de tension d'entrée "rail-to-rail" avec un premier étage d'entrée différentiel (11-P) qui est relié par une première source de courant (12-P) à une première barre omnibus de tension d'alimentation et un deuxième étage d'entrée différentiel (11-N) complémentaire qui est relié par une deuxième source de courant (12-N) à la deuxième barre omnibus de tension d'alimentation. Il est prévu des moyens de commutation (50) qui déconnecte le premier étage d'entrée différentiel (11-P) et connecte le deuxième étage d'entrée différentiel (11-N), quand la valeur de tension du signal de tension d'entrée en présence d'une tension d'entrée croissante dépasse une première valeur seuil de tension (Vlow) prédéfinie et qui déconnecte le deuxième étage d'entrée différentiel (11-N) et connecte le premier étage d'entrée différentiel (11-P) quand la valeur de tension du signal de tension d'entrée en présence d'une tension d'entrée décroissante passe en dessous d'une deuxième valeur seuil de tension (Vhigh) prédéfinie. De ce fait, une pente d'entrée constante avec une réserve de phase élevée peut être obtenue, ce qui permet d'utiliser l'invention en particulier dans le domaine des biocapteurs.
EP11711834A 2010-04-06 2011-03-25 Amplificateur différentiel ayant une plage de tension d'entrée "rail-to-rail" Withdrawn EP2529482A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102010013958A DE102010013958A1 (de) 2010-04-06 2010-04-06 Differenzverstärker mit einem Rail-to-Rail-Eingangsspannungsbereich
PCT/EP2011/054588 WO2011124480A1 (fr) 2010-04-06 2011-03-25 Amplificateur différentiel ayant une plage de tension d'entrée "rail-to-rail"

Publications (1)

Publication Number Publication Date
EP2529482A1 true EP2529482A1 (fr) 2012-12-05

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP11711834A Withdrawn EP2529482A1 (fr) 2010-04-06 2011-03-25 Amplificateur différentiel ayant une plage de tension d'entrée "rail-to-rail"

Country Status (5)

Country Link
US (1) US20130021101A1 (fr)
EP (1) EP2529482A1 (fr)
JP (1) JP2013524665A (fr)
DE (1) DE102010013958A1 (fr)
WO (1) WO2011124480A1 (fr)

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Publication number Priority date Publication date Assignee Title
EP1692767B1 (fr) * 2003-12-11 2019-02-27 Conversant Intellectual Property Management Inc. Pompe de charge a impedance haute capacite pour boucle d'asservissement de phase /boucle d'asservissement de delai
TWI502881B (zh) * 2013-02-01 2015-10-01 Himax Tech Ltd 放大器與其動態偏壓產生裝置
US9312825B2 (en) * 2014-05-09 2016-04-12 Analog Devices Global Amplifier input stage and amplifier
JP2019033414A (ja) * 2017-08-09 2019-02-28 富士電機株式会社 差動回路およびｏｐアンプ
US11251760B2 (en) 2020-05-20 2022-02-15 Analog Devices, Inc. Amplifiers with wide input range and low input capacitance

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Publication number Priority date Publication date Assignee Title
US5153529A (en) * 1991-08-30 1992-10-06 Motorola, Inc. Rail-to-rail input stage of an operational amplifier
FR2728743B1 (fr) * 1994-12-21 1997-03-14 Sgs Thomson Microelectronics Amplificateur a grande excursion de mode commun et a transconductance constante
US5714906A (en) * 1995-08-14 1998-02-03 Motamed; Ali Constant transductance input stage and integrated circuit implementations thereof
JP2001144558A (ja) * 1999-11-15 2001-05-25 Matsushita Electric Ind Co Ltd 差動増幅器
US6380801B1 (en) * 2000-06-08 2002-04-30 Analog Devices, Inc. Operational amplifier
US6462619B1 (en) * 2001-01-08 2002-10-08 Texas Instruments Incorporated Input stag of an operational amplifier
GB2381971B (en) * 2001-11-08 2006-01-11 Micron Technology Inc Rail-to-rail CMOS comparator
US6518842B1 (en) * 2002-06-07 2003-02-11 Analog Devices, Inc. Bipolar rail-to-rail input stage with selectable transition threshold
JP3920236B2 (ja) * 2003-03-27 2007-05-30 Ｎｅｃエレクトロニクス株式会社 差動増幅器
DE60318047T2 (de) * 2003-08-27 2008-11-27 Infineon Technologies Ag Puffer mit einem der Speisespannung gleichen Eingangsspannungsbereich
US7375585B2 (en) * 2005-05-02 2008-05-20 Texas Instruments Incorporated Circuit and method for switching active loads of operational amplifier input stage
JP2008311904A (ja) * 2007-06-14 2008-12-25 Panasonic Corp 演算増幅回路
US7714651B2 (en) * 2007-11-05 2010-05-11 National Semiconductor Corporation Apparatus and method for low power rail-to-rail operational amplifier

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Title
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Also Published As

Publication number Publication date
WO2011124480A1 (fr) 2011-10-13
JP2013524665A (ja) 2013-06-17
US20130021101A1 (en) 2013-01-24
DE102010013958A1 (de) 2011-10-06

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