EP2499573A1 - Ensemble mémoire - Google Patents

Ensemble mémoire

Info

Publication number
EP2499573A1
EP2499573A1 EP10765435A EP10765435A EP2499573A1 EP 2499573 A1 EP2499573 A1 EP 2499573A1 EP 10765435 A EP10765435 A EP 10765435A EP 10765435 A EP10765435 A EP 10765435A EP 2499573 A1 EP2499573 A1 EP 2499573A1
Authority
EP
European Patent Office
Prior art keywords
memory
data
area
speed
program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP10765435A
Other languages
German (de)
English (en)
Inventor
Rainer Puchalla
Daniel Hensel
Klaus Schneider
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP2499573A1 publication Critical patent/EP2499573A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60R—VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
    • B60R16/00—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for
    • B60R16/02—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/251—Local memory within processor subsystem
    • G06F2212/2515—Local memory within processor subsystem being configurable for different purposes, e.g. as cache or non-cache memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory

Definitions

  • the present invention relates to the field of memory architectures in data processing systems.
  • cache memories are often used for temporary storage in order to achieve higher data processing rates.
  • a command processor is to be provided with data and commands from a main memory with a very short access time.
  • main memory Depending on the type of data stored in the main memory, it may be embodied as a random access memory (RAM) or as a ROM (read only memory). Due to the necessarily required, high storage capacity short access times can only be realized with a huge technical effort, which is not economically and technically difficult. It follows that the data flow rates may vary depending on the embodiment of the main memory. For this reason, the aforementioned buffers having a smaller storage capacity and the consequent shorter access time are switched, for example, between functional units communicating with each other, such as between a main memory and a command processor.
  • Operation of the buffer memory is usually organized such that the data and instructions requested by a command processor during program execution are likely to already be in the buffer memory when needed, resulting in a reduction in access times due to the reduction of pauses in the execution of a computer program and a concomitant increase in the processing speed allows.
  • a main memory is used both for data and for command storage, which is required for example in diagnostic systems, which are used for example in engine controls for the diagnosis of drives, but it is often necessary to store an area in the main memory reserve, however, which further increases the required capacity.
  • the data memory can be used as program memory, for which purpose a program instruction sequence is copied from a permanent program memory into a non-permanent data memory.
  • a cache memory is used for the temporary storage of diagnostic program instructions in a system for checking a microprocessor.
  • this solution is not resource-efficient because it requires the provision of a cache dedicated to instruction caching.
  • the invention is based on the knowledge that an efficient memory arrangement can be achieved by dynamically configuring a memory as a data memory for data storage or as a buffer memory, i. Cache memory, for temporary program command storage, can be realized.
  • the invention relates to a memory arrangement having a memory, wherein at least one memory area of the memory can be configured as a data memory or as a buffer memory as a function of a required memory operating speed. If the at least one memory area of the memory is configured as a data memory, then it can be used for example for permanent data storage. On the other hand, if the at least one memory area is configured as a temporary buffer memory, it is used, for example, for storing program instructions.
  • a further memory area of the memory area is configured as a data memory or as a temporary buffer memory.
  • both memory areas of the memory can be configured as data memories or as permanent buffer memories, so that the entire memory can be configured as a data memory or as a temporary buffer memory.
  • a control device or a processor is provided for configuring the memory so that the configuration of the memory can advantageously be performed by a higher-level entity.
  • the memory arrangement comprises a further memory, which is connected upstream of the aforementioned memory, wherein a memory operating speed of the memory is not higher, preferably lower, than a memory operating speed of the further memory.
  • a memory operating speed of the memory is not higher, preferably lower, than a memory operating speed of the further memory.
  • the memory arrangement comprises a further one
  • Memory for example, the aforementioned memory, which is upstream of the memory, wherein the further memory via the memory, for example exclusively via the memory, can be reached, whereby advantageously an increase in the memory working speed can be achieved, in particular when the memory as a Cache memory is configured.
  • the memory arrangement comprises a further memory, which is coupled to the memory, for example upstream thereof, wherein the further memory has a data memory area for data storage and / or a program memory area for program instruction storage, wherein the at least one memory area of the memory as a temporary buffer memory, which is assigned to the data storage area and / or the program memory area, is configurable, and / or wherein a further memory area of the memory as a data memory, which is assigned to the data storage area and / or the program memory area, configurable.
  • the memory may contain a data storage rich for longer-term data storage and a temporary cache memory area for cache storage, whereby an advantageous flexibility of the memory array is achieved.
  • the required memory operating speed comprises an access speed, which is required, for example, for processing certain data, or a storage speed.
  • the required memory operating speed may also depend on a required data processing speed or on a required instruction reading speed, so that the memory arrangement according to the invention can be used in a multiplicity of different data processing scenarios.
  • the required memory working speed can be determined on the basis of a required data processing speed or a required command reading speed, as a result of which the memory can advantageously be configured as needed.
  • the at least one memory area of the memory can be configured during initialization of the memory arrangement.
  • the memory device can be initialized, for example, by a processor accessing it, or initialized during initialization of the processor, which advantageously ensures that the memory configuration can be carried out in an application-specific manner, for example for diagnostic purposes.
  • the invention relates to a data processing device, for example a motor control unit, which may be programmable, with the memory arrangement according to the invention and a processor device, for example a processor, which is designed to access the memory arrangement.
  • a data processing device for example a motor control unit, which may be programmable
  • a processor device for example a processor, which is designed to access the memory arrangement.
  • the invention relates to a drive control device for controlling a vehicle drive, which has the memory arrangement according to the invention, which for storing drive diagnostic data or program commands for carrying out a diagnosis of the vehicle drive.
  • the invention relates to a memory configuration method for configuring an operating mode of a memory, comprising the step of configuring at least one memory area of the memory as a function of a required memory operating speed as a data memory or as a temporary buffer memory.
  • Fig. 1 a data processing device
  • Fig. 2 is a data processing device.
  • FIG. 2 shows a data processing device having a memory arrangement comprising a memory 101 and a further memory 103 arranged upstream of it.
  • the data processing arrangement further comprises an instruction processor 105 connected downstream of the memory 101.
  • the memory 101 is preferably configurable and can be used, for example, as a temporary buffer memory or as a primary data memory.
  • the further memory 103 comprises, for example, a data memory area 107 and a program memory area 109, wherein both memory areas communicate with the memory 101.
  • the data storage area 107 can be realized for example by a RAM (Random Access Memory).
  • the program storage area 109 can be realized by means of a ROM (ROM: Read Only Memory).
  • the memory 101 may be configured as a buffer memory or as a data memory.
  • one or more memory areas of the memory 101 may be configured as a buffer memory and / or as a data memory.
  • FIG. 2 shows the data processing device from FIG. 1 according to a further exemplary embodiment, in which the memory 101 has a memory area 201 which is configured, for example, as a buffer memory area and has a further memory area 203, which for example serves as a data and / or program memory is configured.
  • the data storage area 107 and the program storage area 109 communicate with the buffer storage area 201 of the memory 101.
  • the other storage area 203 is used as the primary data storage on which the command processor 105 can separately access, for example.
  • these accesses can be bus-oriented.
  • separate lines 205 and 207 may be provided for this purpose, wherein the command processor 105 communicates with the buffer memory area 201 by means of the lines 205 and with the data and / or program memory area 203 by means of the lines 207.
  • the lines 205 and 207 may be temporarily providable or hardwired.
  • the aforementioned RAMs can be used as a data memory or as a main memory of the data processing device. These can also be used as read / write memory. Since the access time for all memory cells is approximately the same for both reading and writing, the RAMs are therefore referred to herein as random access memory, ie "random access".
  • the RAMs can be used as non-permanent memories, that is, the data is preferably stored only until the power supply is interrupted.
  • such a buffer memory can also be used as a program memory, for which purpose a command sequence can be copied from a permanent program memory into the non-permanent data memory.
  • the memory 101 may be used primarily as a buffer memory, which may be its primary function, and additionally as a data and / or program memory, which may be its secondary function. The switching between the primary and the secondary function can for example be demand-driven and dynamic.
  • the processing speed of the memory array of the required data processing speed can be adjusted. For example, if the memory 101 is configured as a data and / or program memory, then the maximum possible processing speed, i. the memory operating speed, lower compared to the temporary cache mode. However, if the reduced processing speed for the respective application is sufficient, the memory 101 can be advantageously configured as a program and / or data memory.
  • the data processing device can use the data to determine when it is possible to configure the memory 101 in the respective operating mode. If the memory 101 is to be used as a program and / or data memory, this can be determined, for example, during an initialization thereof. In this case, the memory 101, which is otherwise used as a cache memory, can be reconfigured from the primary function to the secondary function. However, if the memory 101 is to be used as a buffer memory, a reconfiguration to the primary function can take place. As a result of this dynamic switching of the operating modes, there is the possibility of using the memory 101 as required, so that an optimization with respect to the running time or with regard to the available resources with regard to the program and / or data memory can take place as required.
  • the memory arrangement according to the invention or the data processing device can be used in an engine control unit, which can perform a diagnosis of a drive.
  • a diagnostic function is advantageously started in the engine control unit, however, for the execution of which a maximum Processing speed is not necessary.
  • a signal can be recorded over time, wherein the evaluation of the acquired data can then be carried out by means of an algorithm.
  • This signal data can be stored, for example, in the dynamically configurable memory 101, which can be configured as a data memory, and assigned to the algorithm for
  • known diagnostic functions can be divided into two groups.
  • the first group contains, for example, functions that are executed during a driving operation.
  • the second group there may be special diagnostic functions that can only be active during a stay in a workshop, for example.
  • the main memory is used as program memory, although this functionality is required only very rarely and never during an actual driving operation.
  • the diagnostic function can also be loaded into an upload memory area, which can not be provided statically but dynamically in the memory 101.
  • reconfigure the cache into the primary or secondary function it is possible, for example, to implement a hardware-based control in a control unit which, for example, configures the memory 101 as a function of a particular application, for example a diagnostic function.
  • reconfiguring the cache does not necessarily have to be done via a hardware controller. It can also be implemented by software as a software program, which in the ECU initialization - triggered by a diagnostic tester - performs the reconfiguration of the cache.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Mechanical Engineering (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)

Abstract

L'invention concerne un ensemble mémoire comportant une mémoire (101), au moins une zone de mémoire (201, 203) de la mémoire (101) pouvant être configurée comme une mémoire de données ou une mémoire tampon en fonction d'une vitesse de travail de mémoire requise.
EP10765435A 2009-11-09 2010-10-13 Ensemble mémoire Withdrawn EP2499573A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102009046518A DE102009046518A1 (de) 2009-11-09 2009-11-09 Speicheranordnung
PCT/EP2010/065331 WO2011054641A1 (fr) 2009-11-09 2010-10-13 Ensemble mémoire

Publications (1)

Publication Number Publication Date
EP2499573A1 true EP2499573A1 (fr) 2012-09-19

Family

ID=43480900

Family Applications (1)

Application Number Title Priority Date Filing Date
EP10765435A Withdrawn EP2499573A1 (fr) 2009-11-09 2010-10-13 Ensemble mémoire

Country Status (7)

Country Link
US (1) US20120173837A1 (fr)
EP (1) EP2499573A1 (fr)
JP (1) JP2013510353A (fr)
KR (1) KR20120103581A (fr)
CN (1) CN102656569A (fr)
DE (1) DE102009046518A1 (fr)
WO (1) WO2011054641A1 (fr)

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EP2569046B1 (fr) * 2010-05-14 2018-12-05 C.R. Bard, Inc. Dispositif et procédé de placement de cathéter
US9571350B2 (en) 2013-01-23 2017-02-14 International Business Machines Corporation Network element diagnostic evaluation
DE102014203062A1 (de) * 2014-02-20 2015-08-20 Bayerische Motoren Werke Aktiengesellschaft Vergrößern des verfügbaren FLASH-Speichers eines Micro-Controllers
AU2015339511B2 (en) 2014-10-27 2020-05-14 Tensha Therapeutics, Inc. Bromodomain inhibitors
US10311963B2 (en) * 2017-04-19 2019-06-04 Arm Limited Data processing
US10482010B2 (en) * 2017-06-29 2019-11-19 Intel Corporation Persistent host memory buffer

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Also Published As

Publication number Publication date
DE102009046518A1 (de) 2011-05-12
US20120173837A1 (en) 2012-07-05
JP2013510353A (ja) 2013-03-21
WO2011054641A1 (fr) 2011-05-12
CN102656569A (zh) 2012-09-05
KR20120103581A (ko) 2012-09-19

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