EP2458037A1 - Procédé pour anodisation de masque contrôlée avec précision - Google Patents

Procédé pour anodisation de masque contrôlée avec précision Download PDF

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Publication number
EP2458037A1
EP2458037A1 EP11162495A EP11162495A EP2458037A1 EP 2458037 A1 EP2458037 A1 EP 2458037A1 EP 11162495 A EP11162495 A EP 11162495A EP 11162495 A EP11162495 A EP 11162495A EP 2458037 A1 EP2458037 A1 EP 2458037A1
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EP
European Patent Office
Prior art keywords
layer
anodization
anodized
mask
anodizable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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EP11162495A
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German (de)
English (en)
Inventor
Joseph Zerky
Hendrikus Tilmans
Chris Van Hoof
Robert Puers
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Katholieke Universiteit Leuven
Interuniversitair Microelektronica Centrum vzw IMEC
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Katholieke Universiteit Leuven
Interuniversitair Microelektronica Centrum vzw IMEC
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Publication of EP2458037A1 publication Critical patent/EP2458037A1/fr
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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/04—Anodisation of aluminium or alloys based thereon
    • C25D11/12—Anodising more than once, e.g. in different baths
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/022—Anodisation on selected surface areas
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/04—Anodisation of aluminium or alloys based thereon
    • C25D11/06—Anodisation of aluminium or alloys based thereon characterised by the electrolytes used
    • C25D11/08—Anodisation of aluminium or alloys based thereon characterised by the electrolytes used containing inorganic acids
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/04—Anodisation of aluminium or alloys based thereon
    • C25D11/06—Anodisation of aluminium or alloys based thereon characterised by the electrolytes used
    • C25D11/10—Anodisation of aluminium or alloys based thereon characterised by the electrolytes used containing organic acids
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/04—Anodisation of aluminium or alloys based thereon
    • C25D11/18—After-treatment, e.g. pore-sealing
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/04—Anodisation of aluminium or alloys based thereon
    • C25D11/18—After-treatment, e.g. pore-sealing
    • C25D11/24—Chemical after-treatment
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/04—Anodisation of aluminium or alloys based thereon
    • C25D11/18—After-treatment, e.g. pore-sealing
    • C25D11/24—Chemical after-treatment
    • C25D11/246—Chemical after-treatment for sealing layers

Definitions

  • the present invention is related to methods for precisely controlling a masked anodization process.
  • the present invention is further related to manufacturing semiconductor devices, especially to methods of encapsulation and to such devices. More specifically it may relate to zero-Level or wafer level packaging of semiconductor devices.
  • the present invention relates to Nano- and/or Micro-Electro-Mechanical Systems (NEMS and /or MEMS) and to processes of encapsulating (or packaging) said systems.
  • NEMS and /or MEMS Nano- and/or Micro-Electro-Mechanical Systems
  • Creating patterns of a dielectric or porous material within a conductive thin film by means of masked anodization has several advantages over conventional thin film deposition and etching techniques, such as the simplicity of the fabrication process and the relatively planar (and aligned) structures that result from such process.
  • Masking the anodization process is normally achieved by applying a masking structure on top of the layer to be anodized.
  • the masking structure can be applied by means of conventional photolithography (photoresist mask) or by means of deposition and patterning of another material that is resistant to the anodization process (hard mask).
  • a photoresist mask is simpler to implement than a hard mask but photoresists are normally attacked during the anodization process resulting in poor control over the lateral extent of the anodized patterns.
  • NEMS/MEMS Nano- and/or Micro-Electro-Mechanical Systems
  • Said NEMS/MEMS systems cannot be directly packaged in a plastic or ceramic package, the so-called first level package, since NEMS/MEMS are often composed of fragile and/or mobile free-standing parts that can easily be damaged during dicing and assembly. To avoid such damage, NEMS/MEMS devices have to be protected at the wafer level, before dicing. This is possible by the so-called zero-level packaging or wafer-level packaging techniques.
  • NEMS/MEMS systems therefore require an encapsulation under vacuum or under a controlled atmosphere and pressure in order to ensure either a good performance or an acceptable lifetime of operation.
  • the encapsulation has to be performed without the direct deposition of sealing material on the NEMS/MEMS device, as such deposition can cause damage to the device. Therefore there is a need to deposit first an encapsulation made of a layer having holes (pores) through which a vacuum and/or controlled atmosphere can be realized and thereafter deposit a sealing layer.
  • a simple and cheap process led to the idea of encapsulating NEMS/MEMS devices with a porous membrane. This facilitates the manufacturing of the device as it avoids the need to shape access holes in the membrane using photolithography since the device can be released through the pores of the membrane.
  • Porous alumina (AlOx) membranes are recently being investigated for use as porous membranes in said thin film vacuum packaging of NEMS/MEMS devices as shown in figure 1 , which shows a schematic image of a substrate 1 (e.g. Si), carrying on its surface a MEMS device 2, encapsulated by a porous membrane 3.
  • the membrane 3 is covered by a sealing layer 4.
  • the porous membrane 3 is obtained by anodization of an aluminum thin film (deposited on top of a dielectric thin film) in a low-pH electrolyte, and using a patterned photoresist layer as the mask.
  • the anodization process may be performed on masked Al layers using a photoresist mask ( Hellin Rico et al., J. Electrochem. Soc.
  • the pores 5 are elongate openings through the membrane's thickness, through which pores the release of the MEMS device 2 takes place, which is the etching away of a sacrificial layer deposited onto the MEMS device prior to the deposition of the membrane layer 3.
  • This masked anodization process using photoresist has the drawback that the openings in the photoresist do not appropriately limit the anodization process to the desired area, as shown in figure 2 .
  • This figure shows the substrate 1, with a dielectric thin film 11 on the surface of the substrate, and a membrane layer 12 on the thin film 11.
  • a photoresist mask 13 covers the membrane film except for a portion 14 which defines the area of the membrane which is to be anodized.
  • anodization generally takes place by submerging the substrate into an anodization bath. When the substrate is left too long in the anodization bath, anodization continues until an anodized region 15 is formed which is too wide (see borders 16), i.e. unwanted continuous growth of the anodized region occurs.
  • the problem of performing the masked anodization process on a full wafer scale is the fact that areas defined by the masks being present in the central areas (middle) of the substrate (wafer) surface are not yet completely anodized while the areas defined by the masks being present around the substrate (wafer) edges are already completely anodized and will become over-anodized.
  • the problem of unwanted continuous growth is caused by edge peeling (resulting in "undercut") of the photoresist mask due to:
  • anodizable layer e.g. a conductive (metal) layer into an anodized layer e.g. a dielectric or porous layer.
  • a further object is to provide a microelectronic process technology for Nano- and Micro Electro Mechanical Systems (NEMS/MEMS) in order to achieve a controllable and uniform (full) wafer scale encapsulation or packaging process for said NEMS/MEMS devices.
  • NEMS/MEMS Nano- and Micro Electro Mechanical Systems
  • the above objectives are accomplished by a method and device according to the present invention.
  • the present invention solves the problem of achieving a uniform and controllable anodization by surrounding a group (plurality) of mask structures with an additional surrounding mask structure.
  • the problem is solved by using an additional surrounding photoresist or other mask structure with high precision which defines small areas on the surface to be exposed selectively to the anodization process without causing over-anodization leading towards delamination or undercut of the mask layer during the anodization.
  • said additional surrounding mask structure results in self-limitation of the anodization process as the anodized border becomes anodized (oxidized) simultaneously with the anodized areas within said border, so that said border prevents further anodization current from reaching the anodized region of the mask structures to avoid unwanted further anodization. Since the electrical current needed for the anodization process is supplied at the edge (perimeter) of the substrate, surrounding every group of structures on the anodization mask with an additional surrounding mask structure (defining a borderline of anodized material) results in self-limitation of the anodization process as the anodized border becomes simultaneously anodized (oxidized) and prevents further anodization current from reaching the anodized region.
  • the additional surrounding mask structure (defining the borderline or protection ring) may be applied at different scales during the mask design for the anodization process (i.e. the borderline can surround a small group or a large group of structures, or possibly surround the whole substrate (wafer).
  • the width of the additional surrounding mask structure and the surrounded area can be chosen (or adjusted) to guarantee a full vertical anodization of the enclosed structures, and at the same time protect these structures from large lateral extensions of the anodization process.
  • an additional surrounding mask structure is surrounding a group of individual NEMS/MEMS devices and will result in self-limitation of the anodization process as the anodized border becomes simultaneously anodized (oxidized) and prevents further anodization current from reaching the anodized region of the mask structures to avoid unwanted further anodization.
  • the invention is related to a method for masked anodization, said method comprising the steps of
  • the step of anodizing said anodizable layer is performed by inserting the substrate in an electrolyte and applying a voltage (or electrical current) on said substrate.
  • the step of anodizing said anodizable layer may also be performed using a two-step anodization process comprising a first anodizing step to form a first anodized layer, followed by a second anodizing step after etching away the first anodized layer.
  • the step(s) of anodizing is(are) performed by inserting the substrate in an electrolyte selected from the group consisting of sulphuric acid, phosphoric acid, oxalic acid, hydrofluoric acid, ethanol, isopropyl alcohol, and mixtures of these chemicals.
  • said anodizing step(s) produce(s) elongate pores in said anodized structure(s), said pores extending from the front surface to the back surface of said anodizable layer.
  • the anodizable layer is an Al layer and the step(s) of anodizing is(are) performed by inserting the substrate in a sulphuric-acid based electrolyte at temperatures in the range of 20-40°C and applying a voltage of around 20V.
  • the anodizable layer is a metal layer which is to be anodized to form a metal oxide layer
  • said anodization bath comprises an etchant suitable for etching said oxide
  • said anodization step comprises a first time period during which said voltage is applied, said voltage being removed at the end of said first time interval, and a second time period following said first time period, during which second period the substrate is left in said bath, to thereby remove a barrier layer at the bottom of said pores.
  • said metal may be aluminium and said etchant phosphoric acid.
  • the sacrificial layer can be made of a material selected from the group consisting of polycrystalline SiGe, oxide-based or nitride-based films, polymer, single crystal or polycrystalline Si.
  • said substrate may comprise a NEMS/MEMS device, which is(are) encapsulated in said cavity.
  • the step of removing at least some of the sacrificial material is performed using a selective wet or dry etching that does not damage the enclosed NEMS/MEMS device.
  • the sacrificial layer may be silicon-oxide and the selective etching may be performed using a vapor-phase hydrofluoric (HF) acid mixed with other gases such as nitrogen and ethanol or water vapor in a reduced-pressure chamber.
  • HF vapor-phase hydrofluoric
  • the sacrificial layer may be a polymer-based material and the selective etching may be performed using a dry plasma etching in a low-pressure chamber in the presence of oxygen ions.
  • the sealing layer may be :
  • the anodizable layer may be a metal layer or semiconducting layer.
  • Said anodizable layer may be selected from the group consisting of Al, Ta, Ti, Cu, Ni, polycrystalline Si, polycrystalline SiGe.
  • the mask structures may be formed by photolithographic patterning of a photosensitive layer.
  • Figure 1 illustrates the concept of thin film MEMS packaging using a porous membrane as known in the prior art.
  • Figure 2 illustrates the large lateral extension of the Al anodization process using a photoresist mask (problem to be solved by the invention).
  • Figure 3a illustrates an intermediate stage during the anodization process of the invention whereby the anodization current may still reach the anodization region before the vertical anodization is complete.
  • Figure 3b is a top view of a wafer comprising several masks and provided with a ring electrode arranged along the circumference of the wafer.
  • Figure 3c illustrates the final stage of the anodization process of the invention (when the vertical anodization is complete) whereby the borderline is completely anodized (oxidized) forming a dielectric isolation ring around the anodization region which blocks further supply of the electric charges needed for anodization.
  • Figure 4a-4d illustrate different steps in a suitable process flow to use the masked anodization process for thin film packaging of a NEMS/MEMS device according to embodiments of the invention.
  • Figure 4a illustrates the step of depositing a metal layer on top of the sacrificial layer covering the NEMS/MEMS structure and interconnects.
  • Figure 4b illustrates the step of masked anodization and thin barrier oxide layer removal.
  • Figure 4c illustrates the step of removing the sacrificial layer and depositing a sealing layer.
  • Figure 4d illustrates the step of removing the layers covering the metal pads for electrical access and illustrates the final NEMS/MEMS device encapsulation.
  • Figure 5 illustrates the form the pores formed by anodization of an Aluminium layer, and the oxide barrier layer formed at the bottom of the pores.
  • Figure 6 illustrates an example of a mask design defining a ring structure in accordance with the invention.
  • a method for uniform and controllable masked anodization comprising at least the steps of (with reference to figure 3 ) :
  • Figure 3a shows again a substrate 10.
  • a dielectric layer 11 is deposited on the substrate, which may for example be a sacrificial layer.
  • Layer 12 is a membrane layer and layer 13 is a mask layer, preferably a patterned photoresist layer.
  • the mask layer comprises at least one first mask 20, which defines the areas 21 which are to be anodized.
  • the mask layer further comprises a second mask 22 which defines an area 23 which surrounds said one or more first areas 21 to be anodized, forming a closed ring structure (not necessarily a circular-shaped ring) around said areas 21.
  • Figure 3b shows a top view of a semiconductor wafer 30 carrying on its surface the mask layer 13 which comprises a plurality of masks 20 which define areas 21 to be anodized.
  • the mask layer defines a ring structure 23 to be anodized which encircles the masks 20.
  • the 'second mask structure' 22 thus corresponds to the totality of the mask layer 13 minus the mask structures 20.
  • an electrode 31 is placed, which is in electrical contact with the layer 12 to be anodized (preferably a metal layer, see further).
  • the electrode 31 will play the role of the anode during the anodization.
  • This assembly is submerged in an anodization bath, filled with an electrolyte.
  • the second electrode (the cathode) is part of the anodization bath (preferably a metal plate immersed in the anodization bath, facing the front side of the wafer, i.e. the side carrying the masks 20/22).
  • the charge flows in the direction shown by the arrows 32 in figures 3a and 3b , i.e. starting from the outer edge of the wafer 30, and from the outer edge of each mask 20 towards the centre.
  • FIG. 3a illustrates an intermediate stage during the anodization process of the invention whereby the anodization current (charge flow) may still reach the anodization regions 21 before the vertical anodization is complete.
  • Figure 3c illustrates the final stage of the anodization process of the invention (when the vertical anodization is complete) whereby the ring structure 23 is completely anodized (oxidized), thereby acting as borderline and hence forming a dielectric isolation ring around the anodization regions 21, which blocks further supply of the electric charges needed for anodization.
  • the material for use as anodizable layer 12 may be a metal or semiconducting layer which is selected from Al, Ta, Ti, Cu, Ni, polycrystalline Si, polycrystalline SiGe, etc...
  • a metal or semiconducting layer which is selected from Al, Ta, Ti, Cu, Ni, polycrystalline Si, polycrystalline SiGe, etc...
  • Aluminum layers may be used of around 0.5-10 ⁇ m thick which may be deposited e.g. by using a sputtering process performed at low temperature. Prior to anodizing, the Al layers may be cleaned by placing them in an ultrasonic bath of deionized water.
  • the first and second mask structures 20,22 may be formed by state of the art photolithographic patterning of a photosensitive layer (resist).
  • a photosensitive layer photosensitive layer
  • the advantage of using a photoresist (photosensitive layer) is the simplicity of forming the mask structures compared to other techniques involving deposition and patterning (by chemical or physical etching) of another mask material.
  • the step of anodizing said anodizable layer 12 may lead to the formation of a porous (metal) layer.
  • the pores (holes) in said porous layer may have a length greater than ten times their width, and a width in the range 5-200 nm, e.g. 20 nm or between 20nm and 200 nm, or between 5 and 20 nm.
  • the step of anodizing said anodizable (metal) layer 12 may be performed by means of a one-step anodization process.
  • said one step-anodization process may be performed by inserting the substrate in an electrolyte and applying a voltage (or electrical current) on said substrate.
  • Said electrolyte may be sulphuric acid, phosphoric acid, oxalic acid, hydrofluoric acid, ethanol, isopropyl alcohol, or a mixture of these or other chemicals.
  • a voltage in the range of 5-200V pores are formed on the surface of the anodizable (metal) layer which are distributed randomly or in a hexagonal order.
  • optimized process conditions anodization voltage, electrolyte, and temperature should be chosen to reach the best volume expansion factor for the porous layer.
  • the step of anodizing said anodizable (metal) layer 12 may be performed by means of a two-step anodization process.
  • Said two step-anodization process may be performed by first applying a short anodizing step which patterns the surface of the anodizable (metal) layer 12. Later, this patterned surface acts as self-assembled marks for the second anodizing step [ Mei et al., "Formation mechanism of alumina nanotubes and nanowires from highly ordered porous anodic alumina template," Journal of Applied Physics, Vol. 97, 034305 (2005 )].
  • An extended second anodizing step after etching away the first anodized layer not only improves the regularity of the cell arrangement but also reduces the number of defects and dislocations.
  • a third anodizing step does not significantly improve the ordering of the pores and the size of the well-ordered domains.
  • the voltage (current) applied to achieve anodization of the anodizable (metal) layer is applied between the anodizable (metal) layer on the substrate and the electrolyte or a reference electrode therein.
  • the voltage applied for anodizing lies in the range between a few volts and a few hundreds of volts.
  • a voltage of 20V can be used for example when performing anodization in a sulphuric-acid based electrolyte at temperatures in the range of 20-40°C.
  • said additional structure 23 when the anodization of the additional structure 23 (vertical anodization) is complete, said additional structure forms a protective structure 23 acting as a dielectric isolation ring which blocks further supply of the electric charges needed for anodization and thereby avoids unwanted extension of the anodized structures 21 surrounded by the additional structure 23.
  • the anodizable (metal) layer may be an Aluminum layer and the anodization process conditions may be optimized for a given electrolyte, such as anodizing voltage and temperature, and acid concentration.
  • a given electrolyte such as anodizing voltage and temperature, and acid concentration.
  • Synthesis of porous aluminium oxide (AlO x ) membranes can start from a sputter-deposited or evaporated Al film.
  • the main anodizing parameters to be selected are dependent on the type of the electrolyte since this affects the diameter of the pores and the inter-pore distance, voltage and temperature, and the sequence of anodizing steps.
  • the anodization may occur within a glass- or Teflon-based chamber in which a conductive reference electrode is inserted.
  • the substrate 30 carrying the metal layer 12 to be anodized may be inserted into the anodization chamber by means of a Teflon- or polymer-based holder which protects the edges and backside of the substrate from contacting the anodization electrolyte.
  • the anodization process may be performed by applying the anodization voltage (or current) between the reference electrode and the anodizable (metal) layer 12 on the substrate.
  • Figure 4a-4d illustrate different steps in a suitable process flow to use the masked anodization process for thin film packaging of a NEMS/MEMS device.
  • the substrate (10,11,50,51) and the sacrificial layer (40) may be any substrate and layer used and compatible with semiconductor processing, more particular NEMS/MEMS processing.
  • substrates which may be used are, for example, single crystal or polycrystalline Si, single crystal or polycrystalline Ge, glass, quartz, polymer, etc.
  • fragile devices 50 may be located in the cavity, said fragile device may be any NEMS/MEMS device requiring a vacuum or controlled atmosphere and pressure encapsulation.
  • the sacrificial layer 40 may be made of a material selected from polycrystalline SiGe, oxide-based or nitride-based films, polymer, single crystal or polycrystalline Si, etc.
  • Said sacrificial material may be a material which can be removed using a wet or dry etching technique that does not extensively damage the enclosed NEMS/MEMS device (selective etching).
  • a silicon oxide sacrificial layer 40 can be removed by vapor-phase hydrofluoric (HF) acid mixed with other gases (such as nitrogen and ethanol or water vapor) in a reduced-pressure chamber.
  • HF vapor-phase hydrofluoric
  • Such diluted vapor-phase HF mixture can remove the sacrificial silicon oxide layer without reacting with the NEMS/MEMS device or the porous layer surrounding the cavity.
  • the sacrificial material 40 is filling a cavity 44 which is present under said membrane layer 41.
  • the cavity can further comprise a NEMS/MEMS device 50, the functioning and structure of which is inert to said sacrificial material etchant. It can comprise a fragile object, on which substantially no material may be deposited during the closure process to guarantee the proper working and lifetime of the device.
  • the cavity 44 is closed except for said pores and optionally a vent hole (not shown).
  • a vent hole is an additional hole which connects the cavity with the outside.
  • the material for use as metal layer 41 may be a metal or semiconducting layer which is selected from Al, Ta, Ti, Cu, Ni, polycrystalline Si, polycrystalline SiGe, etc...
  • a metal or semiconducting layer which is selected from Al, Ta, Ti, Cu, Ni, polycrystalline Si, polycrystalline SiGe, etc...
  • Aluminum layers of around 0.5-10 ⁇ m thick may be deposited by a sputtering process performed at low temperature. Prior to anodizing, the Al layers may be cleaned by placing them in an ultrasonic bath of deionized water.
  • the step of anodizing said metal layer in order to form a porous metal oxide layer is such that a layer with pores (holes) is achieved, also referred to as porous membrane.
  • Said porous membrane has a front main surface and a back main surface and the pores (holes) in said membrane (holes can be a set of sub-surface interconnected pores) extend from the front main surface towards the back main surface.
  • the pores (holes) in said porous layer may have a length greater than ten times their width, and a width in the range 5-200 nm, e.g. 20 nm or between 20nm and 200 nm, or between 5 and 20 nm.
  • a protective structure acting as a dielectric isolation ring surrounding the NEMS/MEMS devices which blocks further supply of the electric charges needed for anodization and thereby avoids unwanted extension of the anodized structures surrounded by the additional structure.
  • a thin oxide barrier layer may be present after anodization at the bottom of the pores (holes) of the porous oxide layer 43 and may be removed by leaving the wafer for longer time in the anodization electrolyte after the completion of the vertical anodization process (after the end of the anodization current) and by further adding a small amount of an etching chemical to the anodization electrolyte.
  • This allows for chemical etching of a very small portion of the porous layer because the anodization electrolyte (mixture) and temperature can be chosen to provide slow etching of the porous oxide layer (for example by adding a small amount of phosphoric acid which is an etchant of aluminium oxide).
  • the advantage of performing the barrier oxide layer removal in the anodization electrolyte is that the inner surface of the pores (holes) is already wet upon completion of the anodization process which facilitates the access of the etching chemicals to the bottom of the pores.
  • the oxide barrier layer may alternatively be removed by a separate wet or dry chemical etching step after the anodization step, although difficulties are expected when attempting to use wet etching techniques because porous aluminium oxide may have hydrophobic properties that prevent the etching chemicals from penetrating the narrow pores to reach the barrier oxide layer.
  • Figure 5a illustrates the above described barrier layer.
  • the figure illustrates the elongate shape of the pores 60 in the anodized region 21 shown in figure 3c .
  • the barrier layer is formed by the small amount 61 of oxide at the bottom of the pores 60.
  • the step of removing the sacrificial material 40 under the porous Al layer (membrane) may be performed using an etchant until said sacrificial material is at least partially removed (etched away) through the pores 60 (holes) in said porous layer 43.
  • the sacrificial material may be an oxide-based compound (such as SiO 2 ) and the removal of this material may be performed in a reduced-pressure chamber containing a mixture of gases including an etchant of the sacrificial material (such as hydrofluoric acid) in a vapor form in addition to other gases such as ethanol vapor, nitrogen, or water vapor.
  • the sacrificial layer 40 may be a polymer-based material such as photoresist, which can be removed through the pores of said porous 43 layer by dry plasma etching in a low-pressure chamber in the presence of oxygen ions. The removal of the sacrificial material results in a cavity 44 that may be used to host a NEMS/MEMS structure.
  • the sealing layer 45 may be deposited by an evaporation technique or a chemical (CVD) or physical vapour deposition (PVD) technique in a low-pressure chamber.
  • Said sealing layer 45 may be a conductive layer such as Al, Cu, Ni, polycrystalline Si or SiGe.
  • the sealing layer 45 may be a dielectric material such as oxide- or nitride-based silicon compounds, or a polymer.
  • the sealing layer may be a combination or a stack of two or more materials.
  • the very high aspect ratio of the pores 60 of the porous membrane 43 prevents the deposition of the sealing layer 45 onto the NEMS/MEMS structure 50 and thus prevents damage or alteration of the NEMS/MEMS structure. Deposition of the sealing layer results in a sealed cavity 44 that may host a NEMS/MEMS device.
  • the cavity 44 may be sealed under controlled atmosphere and pressure by controlling the gases and pressure present in a chamber used to deposit the sealing layer which in turn closes the pores (holes) 60 leading to the formation of a sealed cavity 44 with controlled atmosphere and pressure.
  • a controlled constitution of ambient gas is meant.
  • the notion of 'horizontal' is defined as substantially orthogonal to the direction of a gravitational field, for example the earth's gravitational field.
  • the notion of 'essentially no material passing through the openings' should be understood as 'no or only a limited amount of material passing in and/or through the openings'.
  • Nano- and Micro-Electro-Mechanical Systems refers to miniature systems with both electrical and non-electrical (e.g. mechanical) functionalities.
  • Examples of NEMS/MEMS devices are inkjet printer heads, miniature mechanical switches, and sensors for applications that include accelerometers (e.g. for air bags in cars) and gyroscopes (e.g. for roll-over detection in cars).
  • the term "zero-level packaging” refers to the encapsulation of NEMS/MEMS structures at the wafer level before dicing the individual NEMS/MEMS devices. Because the NEMS/MEMS structures themselves are often freestanding and fragile they must be encapsulated at the wafer level to avoid damage during wafer dicing and in use. Additionally a porous thin film (membrane) may be part of said encapsulation.
  • the membrane is preferably provided directly above the NEMS/MEMS device. After removing the sacrificial layer (surrounding the NEMS/MEMS structure) through the membrane, the membrane is sealed in order to provide the desired zero level encapsulation and to enclose the required atmosphere at a desired pressure in the cavity.
  • One advantage of this approach is that it reduces the thickness and area of the packaged device compared to the traditional approach.
  • anodization of a 1 ⁇ m-thick Al layer (deposited by sputtering on top of a silicon oxide layer on 200mm Si wafer) has been performed using a photoresist mask not including the border line structure resulting in a large unwanted extension of the anodization region width from 160 ⁇ m up to 800 ⁇ m as shown in figure 2 .
  • the anodization process is performed in a Teflon-based chamber housing a sulfuric-acid-based electrolyte.
  • the anodization temperature and voltage used here are within the range of 20-30°C and 10-20V respectively.
  • the anodization region width has been well controlled by the photoresist mask resulting in only approximately 6 ⁇ m lateral extension of the edges of the anodized regions 21. This means that in the areas 25, substantially no undercut of the photoresist occurs.
  • the latter is illustrative for the good control of the anodization process using a simple photoresist mask comprising a borderline (ring) which surrounds the anodized region and illustrates advantages of embodiments according to the present invention.
  • a thin film vacuum package has been constructed according to embodiments of the invention and the process flow of Figures 4a-4d by following the subsequent steps :

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105492659A (zh) * 2013-08-30 2016-04-13 富士胶片株式会社 金属填充微细结构体的制造方法
EP3556910A1 (fr) * 2018-04-20 2019-10-23 Murata Manufacturing Co., Ltd. Dispositif semi-conducteur ayant une structure encastrée dans une région poreuse et son procédé de fabrication
CN110914481A (zh) * 2017-07-18 2020-03-24 Imec 非营利协会 固态电池组电池和固态电池组的制造

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5686608B2 (ja) * 2011-01-06 2015-03-18 アイシン軽金属株式会社 陽極酸化皮膜の封孔処理方法
US9212940B2 (en) * 2012-09-07 2015-12-15 Xiang Zheng Tu Vacuum cavity-insulated flow sensors
JP5937937B2 (ja) 2012-09-26 2016-06-22 株式会社神戸製鋼所 アルミニウム陽極酸化皮膜
US9605355B2 (en) 2012-12-10 2017-03-28 Mitsubishi Rayon Co., Ltd. Method for producing anodic porous alumina, method for producing molded article having microscopic pattern on surface, and molded article having microscopic pattern on surface
FR3006304B1 (fr) * 2013-05-28 2015-07-03 Commissariat Energie Atomique Procede de realisation d'une partie suspendue d'une structure microelectronique et/ou nanoelectronique dans une partie monolithique d'un substrat
WO2015098843A1 (fr) * 2013-12-26 2015-07-02 富士フイルム株式会社 Membrane filtrante d'alumine poreuse et son procédé de fabrication
JP2016012609A (ja) * 2014-06-27 2016-01-21 東京エレクトロン株式会社 エッチング方法
US10400322B2 (en) 2015-12-04 2019-09-03 The University Of Florida Research Foundation, Inc. Fabrication of thermally stable nanocavities and particle-in-cavity nanostructures
CN105460887B (zh) * 2015-12-17 2017-10-24 中国科学院苏州纳米技术与纳米仿生研究所 图形化多孔硅的制备方法
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KR102492733B1 (ko) 2017-09-29 2023-01-27 삼성디스플레이 주식회사 구리 플라즈마 식각 방법 및 디스플레이 패널 제조 방법
CN111989426B (zh) * 2018-04-20 2024-05-17 株式会社村田制作所 具有多孔区域嵌入式结构的半导体装置及其制造方法
EP3567645A1 (fr) * 2018-05-11 2019-11-13 Murata Manufacturing Co., Ltd. Structure de région poreuse et son procédé de fabrication
CN112119512A (zh) * 2018-05-11 2020-12-22 株式会社村田制作所 多孔区域结构及其制造方法
US10340143B1 (en) * 2018-06-12 2019-07-02 Lam Research Corporation Anodic aluminum oxide as hard mask for plasma etching
US11462723B2 (en) * 2020-10-28 2022-10-04 GM Global Technology Operations LLC Electrochemical cells with copper-free electrodes and methods for manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5989794A (ja) * 1982-11-13 1984-05-24 Corona Kogyo Kk パタ−ンをもつ陽極酸化アルミニウムプレス成型品の製造法
US5681439A (en) * 1995-10-17 1997-10-28 Lg Electronics, Inc. Configuration of an anode-oxidation preventing portion of a metal line

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3775262A (en) * 1972-02-09 1973-11-27 Ncr Method of making insulated gate field effect transistor
US6740247B1 (en) * 1999-02-05 2004-05-25 Massachusetts Institute Of Technology HF vapor phase wafer cleaning and oxide etching
US7153717B2 (en) * 2000-05-30 2006-12-26 Ic Mechanics Inc. Encapsulation of MEMS devices using pillar-supported caps
US8310053B2 (en) * 2008-04-23 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a device with a cavity

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5989794A (ja) * 1982-11-13 1984-05-24 Corona Kogyo Kk パタ−ンをもつ陽極酸化アルミニウムプレス成型品の製造法
US5681439A (en) * 1995-10-17 1997-10-28 Lg Electronics, Inc. Configuration of an anode-oxidation preventing portion of a metal line

Non-Patent Citations (8)

* Cited by examiner, † Cited by third party
Title
G. D. SULKA ET AL: "Synthesis of Well-Ordered Nanopores by Anodizing Aluminum Foils in Sulfuric Acid", JOURNAL OF THE ELECTROCHEMICAL SOCIETY, vol. 149, no. 7, 1 January 2002 (2002-01-01), pages D97 - D103, XP055013499, ISSN: 0013-4651, DOI: 10.1149/1.1481527 *
HELLIN RICO ET AL., J. ELECTROCHEM. SOC., vol. 154, no. 9, 2007
HELLIN RICO, R. ET AL: "Alumina porous membranes obtained by one-step anodizing process in H2SO4 for MEMS Packaging", MEET. ABSTR. - ELECTROCHEM. SOC. - 210TH ECS MEETING, 1758, 29 October 2006 (2006-10-29) - 3 November 2006 (2006-11-03), XP002664699, Retrieved from the Internet <URL:http://www.ecsdl.org/getpdf/servlet/GetPDFServlet?filetype=pdf&id=MAECES000602000038001758000001&idtype=cvips&prog=normal> [retrieved on 20111130] *
J. ZEKRY ET AL: "Wafer-level thin film vacuum packages for MEMS using nanoporous anodic alumina membranes", 2011 16TH INTERNATIONAL SOLID-STATE SENSORS, ACTUATORS AND MICROSYSTEMS CONFERENCE, 1 June 2011 (2011-06-01), pages 974 - 977, XP055013463, ISBN: 978-1-45-770157-3, DOI: 10.1109/TRANSDUCERS.2011.5969507 *
JOSEPH ZEKRY ET AL: "Thermomechanical design and modeling of porous alumina-based thin film packages for MEMS", 2010 11TH INTERNATIONAL THERMAL, MECHANICAL & MULTI-PHYSICS SIMULATION, AND EXPERIMENTS IN MICROELECTRONICS AND MICROSYSTEMS (EUROSIME), 1 April 2010 (2010-04-01), pages 1 - 7, XP055013465, ISBN: 978-1-42-447026-6, DOI: 10.1109/ESIME.2010.5464584 *
MEI ET AL.: "Formation mechanism of alumina nanotubes and nanowires from highly ordered porous anodic alumina template", JOURNAL OF APPLIED PHYSICS, vol. 97, 2005, pages 034305
R. HELLIN RICO ET AL: "Fabrication of Porous Membranes for MEMS Packaging by One-Step Anodization in Sulfuric Acid", JOURNAL OF THE ELECTROCHEMICAL SOCIETY, vol. 154, no. 9, 1 January 2007 (2007-01-01), pages K74, XP055013469, ISSN: 0013-4651, DOI: 10.1149/1.2752117 *
Y. F. MEI ET AL: "Formation mechanism of alumina nanotubes and nanowires from highly ordered porous anodic alumina template", JOURNAL OF APPLIED PHYSICS, vol. 97, no. 3, 1 January 2005 (2005-01-01), pages 034305, XP055013470, ISSN: 0021-8979, DOI: 10.1063/1.1846137 *

Cited By (5)

* Cited by examiner, † Cited by third party
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CN110914481A (zh) * 2017-07-18 2020-03-24 Imec 非营利协会 固态电池组电池和固态电池组的制造
CN110914481B (zh) * 2017-07-18 2022-05-13 Imec 非营利协会 固态电池组电池和固态电池组的制造
EP3556910A1 (fr) * 2018-04-20 2019-10-23 Murata Manufacturing Co., Ltd. Dispositif semi-conducteur ayant une structure encastrée dans une région poreuse et son procédé de fabrication
WO2019202046A1 (fr) * 2018-04-20 2019-10-24 Murata Manufacturing Co., Ltd Dispositif à semi-conducteur ayant une structure incorporée de région poreuse et procédé de fabrication de celui-ci

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