EP2412008A1 - Procédé de fabrication de cellules solaires à émetteur sélectif - Google Patents

Procédé de fabrication de cellules solaires à émetteur sélectif

Info

Publication number
EP2412008A1
EP2412008A1 EP10711215A EP10711215A EP2412008A1 EP 2412008 A1 EP2412008 A1 EP 2412008A1 EP 10711215 A EP10711215 A EP 10711215A EP 10711215 A EP10711215 A EP 10711215A EP 2412008 A1 EP2412008 A1 EP 2412008A1
Authority
EP
European Patent Office
Prior art keywords
diffusion
wafer
doping source
etching
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP10711215A
Other languages
German (de)
English (en)
Inventor
Tobias Wuetherich
Jan Lossen
Mathias Weiss
Karsten Meyer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Ersol Solar Energy AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ersol Solar Energy AG filed Critical Ersol Solar Energy AG
Publication of EP2412008A1 publication Critical patent/EP2412008A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to a process for the production of solar cells with selective emitter.
  • One way of producing selective emitter structures is first of all to apply a diffusion mask, to open it at the desired locations, for example by printing an etching paste on certain areas or by laser ablation, in order then to carry out a high degree of diffusion into the volume of the wafer. Then the mask is to be removed and over the entire surface to realize a further diffusion with the aim of forming portions of lower doping.
  • a weak diffusion is carried out.
  • AU 570 309 it is known first to perform a weak diffusion on the wafers over the entire surface. Subsequently, a very dense silicon nitride layer is applied by means of an LPCVD step, which serves both as a mask and later takes on the function of the anti-reflection layer. Trenches are then cut into the substrate by means of lasers. In these trenches into a strong doping is then made. The trenches in turn are subsequently metallized by nickel-copper-tin plating.
  • a method for manufacturing a silicon solar cell with a selective emitter is previously known.
  • a planar emitter is produced on a surface of the substrate.
  • This step is followed by an etching of the emitter surface in non-covered by the etching barrier second portions.
  • metal contacts are produced at the first subareas.
  • a porous silicon layer is formed, which is subsequently oxidizable. This oxidized porous silicon layer can subsequently be etched away together with optionally existing phosphorus glass. Using known screen printing and etching techniques, this method is said to be compatible with current industrial manufacturing equipment.
  • the relevant idea is to first produce an emitter on at least one surface of a solar cell substrate with a homogeneous doping concentration high enough that it is suitable for contacting in the later screen printing process is.
  • first subregions of the already existing emitter surface are protected by an etching barrier.
  • the unprotected areas are subject to the Etching step, so that the thickness of the emitter is reduced in the mentioned areas, with the result that in these second partial areas, an emitter is formed with an increased sheet resistance.
  • a planar emitter is produced on a surface of a solar cell substrate. Subsequently, a layer of porous silicon is created, which is then selectively subject to etching back.
  • any desired methods can be used according to DE 10 2007 062 750 A1. For example, it is possible to form the planar emitter by means of a POCl 3 - Gasphase ⁇ diffus ⁇ on by diffusing phosphorus from a hot gas phase in the surface of the substrate.
  • the parameters when generating the flat emitter should be selected so that preferably sets an emitter layer resistance of less than 60 ⁇ / D.
  • An etching barrier is applied to the created first subregions of the front surface of the substrate. The etch barrier protects the underlying first portions of the emitter surface from the etchant.
  • the emitter surface is etched down so strongly in the etching step in the second subregions until a desired high sheet resistance of, for example, more than 60 ⁇ / D is stiffened in the remaining emitter layer.
  • the sheet resistance is checked by measurement in order to be able to cancel the etching process in a targeted manner.
  • an additional step takes place with regard to the production of the mentioned porous silicon layer.
  • This process step takes place after the deposition of the etching barrier at the second partial regions of the emitter surface of the substrate which are not covered by the etching barrier.
  • an etching process which leads to the formation of an at least partially porous silicon layer. This porous Siiizium Mrs is oxidized at a later process step.
  • the photovoltaic cell with two or more selectively diffused regions assumes that the selective regions are produced by means of a single diffusion step.
  • a screen printing of solid-based dopant pastes is assumed in order to then form the diffusion regions with a first high-temperature heat-curing step.
  • a second high-temperature heat treatment step is performed.
  • Homogeneous emitters as they are usually used in industrial manufacturing so far, have relatively poor optical and electronic properties. In order to achieve a sufficiently low contact resistance, much more doping is required than is necessary for a sufficient electrical function per se. The too high doping is noticeable as too high emitter saturation current, which has a negative influence on the open clamping voltage and the filling factor. Due to the low charge carrier lifetime in the highly doped emitter, charge carriers generated there can not be separated, which leads to a reduction in the short-circuit current and ultimately results in a reduced efficiency of the solar cell.
  • the proposed methods for producing selective emitters avoid the abovementioned disadvantages at least occasionally, but are not suitable for cost-effective industrial implementation for various reasons.
  • a mask to open the area to be contacted later is less economical in that more than 80% of the area to be covered with an etching mask, such as an etching varnish, which also leads to high costs.
  • the opening with a screen-applied etching paste or by laser ablation on the one hand entails an increased safety expenditure when using aggressive paste materials and on the other hand a strong damage to the surface during treatment by laser ablation.
  • the solution according to DE 10 2007 035 068 Al reduces the need for Abdecklack.
  • the disadvantage is that the sheet resistance in the low-doped region is produced by back etching.
  • the etching processes outlined there are not self-limiting. Inhomogeneities of the etching bath such as temperature, concentration of the etching medium or the degradation products therefore lead to an inhomogeneity of the sheet resistance, which adversely affects the cell efficiency.
  • the etching solutions necessary there are extremely aggressive, which makes it difficult to choose a suitable masking varnish.
  • the emitter profile produced after etchback still has too high a surface concentration of the dopant, resulting in an undesirably high emitter saturation current.
  • the wafers on their front side can have texturing carried out in a manner known per se. Under front side is here to understand the side that is exposed to the solar cell during later use of the solar cell.
  • the wafer treated in this way is then provided with a full-surface doping source. During the application of the full-area doping source and subsequently thereto, an easy, first introduction of the dopant is achieved until a first sheet resistance region is reached.
  • the doping source is patterned, wherein as a result of the structuring only those areas remain which substantially correspond to the sections to be contacted later on the wafer or by a deliberately predetermined small amount are larger than these contact portions.
  • the doping source preferably comprises phosphosilicate glass (PSG).
  • PSG phosphosilicate glass
  • the first sheet resistance range is after completion of the two diffusions at substantially 100 to 300 ⁇ / D.
  • the second layer resistance region for the emitter section below the later contacts is between 30 ⁇ / D and less than 100 ⁇ / D.
  • the structuring of the doping source takes place in that etching-resistant masking is applied to the areas to be left, with subsequent execution of the etching step.
  • the masking may be formed by screen printing, stencil printing, hot melt screen printing, ink jet printing, dispensing, aerosol printing, hot melt ink jet printing or the like.
  • the etching mask is removed.
  • the etching process can be carried out wet-chemically or under plasma or plasma-assisted, wherein after the etching step the masking layer and any residues are stripped or ashed by creating an oxygen plasma.
  • oxidation of the surface of the wafer is possible in order to bring about a further lowering of the surface concentration as well as an injection of interstitial oxygen atoms into the wafer.
  • the figure shows a basic sequence of steps a) to f) with the aim of forming a selective emitter by structuring the doping source to the front side metallization, wherein the processing of the back can be done by any method of the prior art.
  • a doping source e.g. Phosphosilicate glass (PSG) applied and slightly diffused (Fig. Ia)).
  • PSG Phosphosilicate glass
  • Fig. Ia The silicon wafer is here provided with reference numeral 1 and the full-surface applied diffusion source with the reference numeral 2.
  • the slightly diffused region is indicated by the reference numeral 5.
  • a sheet resistance between 100 and 200 ⁇ / ⁇ is set.
  • This can be done in a combined process step of gas phase diffusion, e.g. Phosphoroxyl chloride (POCb) and heat treatment done, for example in a quartz tube furnace.
  • gas phase diffusion e.g. Phosphoroxyl chloride (POCb)
  • heat treatment done, for example in a quartz tube furnace.
  • the doping source eg PSG
  • APCVD Atmospheric Plasma Chemical Vapor Deposition
  • the applied full-surface diffusion source 2 is structured, so that strip-shaped regions 3 remain, as shown in FIG. Ib) greatly simplified.
  • the structuring of the doping source takes place in such a way that the area which is to be electrically later contacted is still covered by the source material, but all other areas are no longer covered.
  • the source material may also be left slightly above or below this later contact area.
  • the above-mentioned structuring of the doping or diffusion source can be achieved by various methods.
  • etch-resistant layer include, but are not limited to, organic, dry-crosslinking paints, waxy organic materials, UV-curing paints, as well as silicon-oxide-nitride films prepared by annealing starting materials of this type.
  • the masking areas or sections may be realized by screen printing, stencil printing, hot melt screen printing, ink jet printing, hot melt ink jet printing, dispensing, aerosol printing or the like.
  • the diffusion source is removed by etching, wherein here advantageously an etching medium is selected, which etches the diffusion source with a high selectivity with respect to the silicon-based material of the wafer.
  • acids with the same property can be used in a wet-chemical etching.
  • a plasma step in the sense of dry etching can also be used.
  • fluorine ion-based etching processes eg with CF 4 , have a selectivity necessary for the PSG layer removal.
  • the masking layer is removed. This can then be done in the same etching plant in which the diffusion source was removed.
  • Organic layers can be removed wet-chemically by suitable stripper solutions. Silicon oxide-nitride layers can be etched with phosphoric acid.
  • etching pastes in the areas in which the swelling layer is to be removed, or the dry etching by etching masks.
  • the surface passivation can be performed more effectively at a lower doping concentration at the surface.
  • the diffusion may e.g. by temperature treatment in a quartz tube furnace or in a continuous furnace.
  • an additional oxidation of the swelling layer and the Banlsch ⁇ cht-free surface can be done. This allows a further reduction of the surface concentration.
  • the oxidation can also accelerate the diffusion.
  • Fig. Id shows the situation after the removal of the remaining diffusion sources.
  • Fig. Ie symbolically represents an applied antireflection layer 6.
  • the preparation of the antireflection layer 6, the implementation of the edge insulation and the production of the metallization contacts 7 can be carried out by different methods known per se.
  • care must be taken to ensure that the intended contact areas (heavy doping 4) are maintained.
  • the emitter can passivate better. This and the cheaper doping profile reduce the emitter saturation current, which in turn increases the no-load voltage of the solar cell. Finally, the contact resistance of the front side metallization to the emitter can be reduced.
  • the method described is characterized by a particular simplicity and manageable process management. Only a small part of the surface of the wafer needs to be masked, so less masking material is needed.
  • a variety of readily controllable materials comes into question.
  • the etching of e.g. PSG as Dot ⁇ eretti can be carried out with hydrofluoric acid in a very cost-effective manner and easily controlled.
  • the mentioned diffusion processes are relatively short and feasible at moderate temperatures. This saves energy and allows the process to be used on a wide range of silicon feedstock and wafers made from it. This also applies to wafers in which an excessively high temperature budget would lead to a reduction in the service life.

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Photovoltaic Devices (AREA)

Abstract

L'invention concerne un procédé de fabrication de cellules solaires à émetteur sélectif. Tout d'abord, des tranches (1) sans défaut de sciage sont préparées. Ensuite ont lieu une application de source de dopage (2) sur toute la surface de la tranche et une première diffusion légère du dopant jusqu'à ce qu'un premier domaine de résistance de couche soit atteint. Il intervient ensuite une structuration de la source de dopage appliquée, seules restant sur la tranche à la fin de la structuration les zones (4) qui correspondent sensiblement aux segments de contact à appliquer ultérieurement. On réalise une deuxième diffusion dans le volume de la tranche à partir des zones subsistantes de la source de dopage, jusqu'à ce que l'on atteigne un deuxième domaine de résistance de couche pour l'émetteur sélectif (4) et simultanément une répartition du dopant (5) introduit lors de la première diffusion, l'objectif étant de réduire la concentration de dopant dans la zone proche de la surface qui n'est plus recouverte de la source de dopage, étant précisé que les valeurs de résistance de couche du premier domaine de résistance de couche sont supérieures à celles du deuxième domaine de résistance de couche.
EP10711215A 2009-03-27 2010-03-26 Procédé de fabrication de cellules solaires à émetteur sélectif Withdrawn EP2412008A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102009015367 2009-03-27
DE102009041546A DE102009041546A1 (de) 2009-03-27 2009-09-15 Verfahren zur Herstellung von Solarzellen mit selektivem Emitter
PCT/EP2010/053985 WO2010115730A1 (fr) 2009-03-27 2010-03-26 Procédé de fabrication de cellules solaires à émetteur sélectif

Publications (1)

Publication Number Publication Date
EP2412008A1 true EP2412008A1 (fr) 2012-02-01

Family

ID=42733330

Family Applications (1)

Application Number Title Priority Date Filing Date
EP10711215A Withdrawn EP2412008A1 (fr) 2009-03-27 2010-03-26 Procédé de fabrication de cellules solaires à émetteur sélectif

Country Status (5)

Country Link
US (1) US20120167968A1 (fr)
EP (1) EP2412008A1 (fr)
CN (1) CN102449738B (fr)
DE (1) DE102009041546A1 (fr)
WO (1) WO2010115730A1 (fr)

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US8084280B2 (en) 2009-10-05 2011-12-27 Akrion Systems, Llc Method of manufacturing a solar cell using a pre-cleaning step that contributes to homogeneous texture morphology
US20110308614A1 (en) * 2010-06-16 2011-12-22 E. I. Du Pont De Nemours And Company Etching composition and its use in a method of making a photovoltaic cell
FR2964252A1 (fr) * 2010-09-01 2012-03-02 Commissariat Energie Atomique Procede de realisation d'une structure a emetteur selectif
TW201218407A (en) * 2010-10-22 2012-05-01 Wakom Semiconductor Corp Method for fabricating a silicon wafer solar cell
TWI453939B (zh) * 2010-12-30 2014-09-21 Au Optronics Corp 太陽能電池及其製作方法
DE102011002748A1 (de) * 2011-01-17 2012-07-19 Robert Bosch Gmbh Verfahren zur Herstellung einer Silizium-Solarzelle
KR20120111378A (ko) * 2011-03-31 2012-10-10 삼성디스플레이 주식회사 태양 전지 및 이의 제조 방법
DE102011080202A1 (de) 2011-08-01 2013-02-07 Gebr. Schmid Gmbh Vorrichtung und Verfahren zur Herstellung von dünnen Schichten
NL2010116C2 (en) * 2013-01-11 2014-07-15 Stichting Energie Method of providing a boron doped region in a substrate and a solar cell using such a substrate.

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Also Published As

Publication number Publication date
CN102449738B (zh) 2015-09-02
CN102449738A (zh) 2012-05-09
WO2010115730A1 (fr) 2010-10-14
DE102009041546A1 (de) 2010-10-14
US20120167968A1 (en) 2012-07-05

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