Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/26—Bombardment with radiation
  • H01L21/263—Bombardment with radiation with high-energy radiation
  • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
  • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
  • H01L21/2251—Diffusion into or out of group IV semiconductors
  • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E10/00—Energy generation through renewable energy sources
  • Y02E10/50—Photovoltaic [PV] energy
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
  • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

• semiconductors form the basis of modern electronics. Possessing physical properties that can be selectively modified and controlled between conduction and insulation, semiconductors are essential in most modern electrical devices (e.g., computers, cellular phones, photovoltaic cells, etc.).
• Electrons on the p-type side of the junction within the electric field (or built-in potential) may then be attracted to the n-type region (usually doped with phosphorous) and repelled from the p-type region (usually doped with boron), whereas holes within the electric field on the n-type side of the junction may then be attracted to the p-type region and repelled from the n-type region.
• a BSF is generally a region located at the rear of a solar cell which tends to repel minority carriers in the absorber region from high recombination zones at the rear surface and metallized regions of the wafer.
• a BSF may be formed using dopants of the same type as those used in the absorber region, in this case the concentration of dopant atoms in the BSF is selected to be higher than that used to dope the absorber region, thus creating a potential barrier between the bulk of the wafer and the rear surface.
• the rear surface may be passivated by the diffusion of dopant atoms of the opposite type (counter dopant) to those used in the absorber region.
• dopant atoms of the opposite type counter dopant
• a floating junction is established at the rear side of the substrate which has been shown to also provide effective passivation.
• a second diffused region must generally be used to provide ohmic contact to the absorber region of the solar cell.
• the method also includes exposing the substrate to a diffusion gas including phosphorous at a second temperature and for a second time period creating a PSG layer on the first substrate surface and further creating a second diffused region with a second diffusion depth in the substrate beneath the second surface region, wherein the first diffused region is proximate to the second diffused region.
• the method further includes exposing the substrate to a oxidizing gas at a third temperature and for a third time period, wherein a SiO2 layer is formed between the PSG layer and the substrate surface, wherein the first diffusion depth is substantially greater than the second diffusion depth.
• FIG. 4 shows a simplified diagram of a solar cell with a selective emitter and aluminum BSF, in accordance with the invention
• FIGS. 7A-C show a simplified diagram of various electrical characteristics for different regions of a selective emitter, in accordance with the invention.
• a multi-doped junction may be formed on a substrate using a simultaneous diffusion step by incorporating doped Group IV nanoparticles as a high concentration dopant layer and dopant diffusion source.
• the first and second diffused region are the same dopant type (both n- type or both p-type), while in the case of a BSF the diffused regions may be formed using either dopant types (n-type and/or p-type). Both the selective emitter and the BSF may also be formed in a simultaneous diffusion step.
• a nanoparticle is a microscopic particle with at least one dimension less than 100 nm.
• solvents examples include alcohols, aldehydes, ketones, carboxylic acids, esters, amines, organosiloxanes, halogenated hydrocarbons, and other hydrocarbon solvents.
• the solvents may be mixed in order to optimize physical characteristics such as viscosity, density, polarity, etc.
• bulky capping agents suitable for use in the preparation of capped Group IV semiconductor nanoparticles include C4-C8 branched alcohols, cyclic alcohols, aldehydes, and ketones, such as tertiary-butanol, isobutanol, , cyclohexanol, methyl-cyclohexanol, butanal, isobutanal, cyclohexanone, and oraganosiloxanes, such as methoxy(tris(trimethylsilyl)silane)(MTTMSS), tris(trimethylsilyl)silane (TTMSS), decamethyltetrasiloxane (DMTS), and trimethylmethoxysilane (TMOS).
• MTTMSS methoxy(tris(trimethylsilyl)silane)
• TTMSS tris(trimethylsilyl)silane
• DMTS decamethyltetrasiloxane
• TMOS trimethylmethoxysilane
• FIGS IA-F a simplified set of diagrams showing an optimized method for forming a multi-doped junction on a substrate, such as a solar cell with a selective emitter (using the same dopant type) or BSF (using different dopant types), with a simultaneous diffusion step, in accordance with the invention.
• a doped set of nanoparticles 100 is deposited on doped silicon substrate 102 surface using application methods such as roll coating, slot die coating, gravure printing, flexographic drum printing, inkjet printing methods, etc.
• the silicon substrate may be baked in order to remove residual solvents at a baking temperature (preferably from 100 0 C to 500 0 C, more preferably between about 350 0 C and about 450 0 C, and most preferably about 400 0 C).
• This baking may be performed in an air ambient or in an inert ambient such as with a nitrogen gas, argon gas or forming gas.
• doped silicon substrate 102 is positioned in a sintering furnace
• doped set of nanoparticles 100 may be sintered at a sintering temperature (preferably between about 500 0 C and about 1000 0 C, more preferably between about 750 0 C and 850 0 C, and most preferably about 800 0 C) and for a sintering time (preferably between about 5 seconds and about 2 minutes, more preferably between about 5 seconds and about 20 seconds, and most preferably at about 15 seconds with an inert ambient (such as nitrogen, argon, etc)) in order to form a densified thin film.
• a sintering temperature preferably between about 500 0 C and about 1000 0 C, more preferably between about 750 0 C and 850 0 C, and most preferably about 800 0 C
• a sintering time preferably between about 5 seconds and about 2 minutes, more preferably between about 5 seconds and about 20 seconds, and most preferably at about 15 seconds with an inert ambient (such as nitrogen, argon, etc)
• a BSF may be applied to the rear surface of doped silicon substrate in order to repel minority carriers in the absorber region from high recombination zones at the rear surface and metallized regions of the wafer.
• the BSF may be formed using aluminum paste (or other deposited materials) which is generally first screen printed onto the back of a solar cell and then co-fired in a belt furnace along with the front side metal contacts.
• a diffusion temperature preferably between about 700 0 C and about 1000 0 C and between about 5 minutes and about 30 minutes, and more preferably between about 750 0 C and about 850 0 C and for between 10 and 20 minutes, and most preferably about 800 0 C and for about 15 minutes.
• nitrogen is flowed as a carrier gas through a bubbler filled with a low concentration liquid POCI 3 (phosphorus oxychloride), O 2 gas , and N 2 gas to form a processing gas 101.
• POCI 3 phosphorus oxychloride
• PSG phosphorous silicate glass
• P 2 O 5 phosphorus oxide
• Cl 2 gas produced as a byproduct, interacts with and removes metal impurities in doped silicon substrate 102.
• phosphorus diffuses into the silicon wafer to form the second doped (lower dopant concentration) area 104.
• a second oxidizing gas 109 is formed using O 2 and N 2 .
• the furnace chamber is first heated to an oxidizing temperature (preferably between about 800 0 C to about 1100 0 C, more preferably between about 950 0 C and about 1050 0 C, and most preferably about 1000°C).
• SiO 2 (silicon dioxide) layer 107 (about 10 - 50 nm) is then formed (at a N 2 : 0 2 mixture of about 1 : 1 ) as a result of oxygen gas reacting with silicon atoms in doped silicon substrate 102 surface.
• the diffusion depth of final first doped area 112b may be substantially greater than the corresponding diffusion depth of second doped area 104, minimizing the likelihood of shunting caused by the penetration of a front-metal contact (as shown in FIG. 4) into the lightly counter-doped substrate.
• a highly doped n-type nanoparticle layer 200 is deposited on the front surface of a p-doped silicon substrate 202 using application methods such as roll coating, slot die coating, gravure printing, flexographic drum printing, inkjet printing methods, etc.
• the silicon substrate maybe baked in order to remove residual solvents at a first baking temperature (preferably from about 100 0 C to about 500 0 C, more preferably between about 350 0 C and about 45O 0 C, and most preferably about 400 0 C). Baking may be performed in an air ambient or in an inert ambient such as with a nitrogen gas, argon gas or forming gas.
• P-doped silicon substrate 202 is then baked in order to remove residual solvents in highly doped p-type nanoparticle layer 220 at a second baking temperature (preferably from about 100 0 C to about 500 0 C, more preferably between about 350 0 C and about 450 0 C, and most preferably about 400 0 C).
• This baking may be performed in an air ambient or in an inert ambient such as with a nitrogen gas, argon gas or forming gas.
• a furnace e.g. quartz tube furnace, belt furnace, etc.
• an additional heat process may be used to pre-sinter the particles prior to diffusion to improve the formation of a low recombination ohmic contact.
• n-type doped nanoparticles 200 and p-type doped nanoparticles 220 may then be simultaneously sintered with an inert ambient at a sintering temperature in order to each form a densified thin film (preferably between about 500 0 C and about 1000 0 C, more preferably about 750 0 C and about 85O 0 C, and most preferably about 800 0 C) and for a sintering time (preferably about 5 seconds and about 2 minutes, more preferably about 5 seconds to about 20 seconds, and most preferably about 15 seconds) and in an inert ambient (e.g. N 2 , Ar, forming gas).
• a densified thin film preferably between about 500 0 C and about 1000 0 C, more preferably about 750 0 C and about 85O 0 C, and most preferably about 800 0 C
• a sintering time preferably about 5 seconds and about 2 minutes, more preferably about 5 seconds to about 20 seconds, and most preferably about 15 seconds
• an inert ambient e
• n-dopant atoms in the set of n-type doped nanoparticles 200 begin to diffuse into p-doped silicon substrate 202 to form the initial n-doped high concentration area 212a, while p-dopant atoms in the set of p-type doped nanoparticles 220 also begin to diffuse into p-doped silicon substrate 202 to form the initial p-doped high concentration area 222a.
• FIG. 2E As the thermal process as shown in FIG. 2D continues, O 2 molecules react with POCI 3 molecules to form front PSG layer 232 and rear PSG layer 234, both comprising P 2 Os (phosphorus oxide), on p-doped silicon substrate 202.
• Cl 2 gas produced as a byproduct, interacts with and removes metal impurities in p-doped silicon substrate 202.
• phosphorus diffuses into the silicon wafer to form a front n-doped low concentration area 204.
• phosphorus diffuses into the silicon wafer in areas generally without the p-type doped nanoparticles layer 201. Otherwise, a low concentration of phosphorous (n-type) diffuses into BSF layer 220, which has a substantially higher boron (p-type) dopant concentration.
• a second oxidizing gas 236 is formed using O 2 and N 2 .
• the furnace chamber is heated to an oxidation temperature (preferably between about 800 0 C to aboutl 100 0 C, more preferably between about 95O 0 C and 1050 0 C, and most preferably at about 1000 0 C) for between about 5 minutes and 30 minutes.
• an oxidation temperature preferably between about 800 0 C to aboutl 100 0 C, more preferably between about 95O 0 C and 1050 0 C, and most preferably at about 1000 0 C
• the oxygen gas reacts with silicon atoms in p-doped silicon substrate 302, a front SiC> 2 (silicon dioxide) layer 207 and a rear SiO 2 (silicon dioxide) layer 240, each about 10 nm to about 50 nm, are formed within p-doped silicon wafer 202. Once a sufficient SiO 2 thickness has been achieved, the O 2 gas flow is terminated.
• the quartz chamber is then heated to a diffusion temperature of about 900 0 C and 1100 0 C and a diffusion time period (preferably between about 5 minutes and about 60 minutes, more preferably between 15 and 30 minutes, and most preferably for about 22 minutes) in an N 2 ambient in order to drive the dopant atoms (originally in n-type doped nanoparticle layer 200 and p-type doped nanoparticles layer 220), deeper into p-doped silicon substrate 202 to form final n-doped high concentration area 212a and final p-doped high concentration area 222b.
• a diffusion temperature of about 900 0 C and 1100 0 C and a diffusion time period (preferably between about 5 minutes and about 60 minutes, more preferably between 15 and 30 minutes, and most preferably for about 22 minutes) in an N 2 ambient in order to drive the dopant atoms (originally in n-type doped nanoparticle layer 200 and p-type doped nanoparticles layer 220), deeper into p-do
• the diffusion depth of final n-doped high concentration area 212b may be substantially greater than the corresponding diffusion depth of a front n-doped low concentration area 204, minimizing the likelihood of shunting caused by the penetration of a front-metal contact (not shown) into the lightly counter-doped substrate.
• front PSG layer 232 and rear PSG layer 234 may be removed using a batch HF wet bench or other suitable means.
• FIGS 3A-G a simplified set of diagrams showing an optimized method for forming a selective emitter with a reduced area rear electrode contact and passivated rear surface, in a simultaneous diffusion step, in accordance with the invention.
• a highly doped n-type nanoparticles layer 300 is deposited on the front surface of a p-doped silicon substrate 302 using application methods such as roll coating, slot die coating, gravure printing, flexographic drum printing, inkjet printing methods, etc.
• the silicon substrate may be baked in order to remove residual solvents at a first baking temperature (preferably from about 100 0 C to about 500°C, more preferably between about 350°C and about 450 0 C, and most preferably about 400 0 C).
• This baking may be performed in an air ambient or in an inert ambient such as with a nitrogen gas, argon gas or forming gas.
• This set of n-type doped nanoparticles 300 will form the highly doped portion of the selective emitter.
• a highly doped p-type nanoparticles layer 301 is then deposited on the back surface of a p-doped silicon substrate 302 to form the reduced area rear contact.
• the reduced area rear contact is generally deposed to match the rear electrode grid [not shown] (e.g. 120um wide lines spaced at 2mm intervals at right angles to a pair of 500um wide busbar lines) also using application methods such as roll coating, slot die coating, gravure printing, flexographic drum printing, inkjet printing methods, etc.
• the remaining rear surface area 303 must generally be passivated in order to minimize losses due to recombination using SiO 2 , SiN x , or other techniques.
• p-doped silicon substrate 302 may be baked in order to remove residual solvents at a second baking temperature (preferably from about 100 0 C to about 500 0 C, more preferably between about 350 0 C and about 450 0 C, and most preferably about 400 0 C).
• This baking may be performed in an air ambient or in an inert ambient such as with a nitrogen gas, argon gas or forming gas.
• p-doped silicon substrate 302 is positioned in a furnace (e.g. quartz tube furnace, belt furnace, etc.).
• a furnace e.g. quartz tube furnace, belt furnace, etc.
• an additional heat process may be used to pre-sinter the particles prior to diffusion to improve the formation of a low recombination ohmic contact.
• n-type doped nanoparticles 300 and p-type doped nanoparticles 301 may then be simultaneously sintered with an inert ambient at a sintering temperature in order to each form a densified thin film (preferably between about 500 0 C and about 1000 0 C, more preferably about 750°C and about 850 0 C, and most preferably about 800 0 C) and for a sintering time (preferably about 5 seconds and about 2 minutes, more preferably about 5 seconds to about 20 seconds, and most preferably about 15 seconds) and in an inert ambient (e.g. N 2 , Ar, forming gas).
• a densified thin film preferably between about 500 0 C and about 1000 0 C, more preferably about 750°C and about 850 0 C, and most preferably about 800 0 C
• a sintering time preferably about 5 seconds and about 2 minutes, more preferably about 5 seconds to about 20 seconds, and most preferably about 15 seconds
• an inert ambient e.g
• n-dopant atoms in the set of n-type doped nanoparticles 300 begin to diffuse into p-doped silicon substrate 302 to form the initial n-doped high concentration area 312a
• p-dopant atoms in the set of p-type doped nanoparticles 301 also begin to diffuse into p-doped silicon substrate 302 to form the initial p-doped high concentration area 313a.
• a diffusion furnace 302 is loaded into a diffusion furnace and heated to diffusion temperature (preferably between about 700 0 C and about 1000 0 C and between about 5 minutes and about 30 minutes, more preferably between about 75O 0 C and about 85O 0 C and for between 10 and 20 minutes, and most preferably about 800 0 C and for about 15 minutes) during which time, nitrogen is flowed as a carrier gas through a bubbler filled with a low concentration liquid POCI 3 (phosphorus oxychloride), O 2 gas, and N 2 gas in order to form a processing gas 330.
• POCI 3 phosphorus oxychloride
• FIG. 3 E As the thermal process as shown in FIG. 3D continues, O 2 molecules react with POCI 3 molecules to form front PSG layer 332 and rear PSG layer 334, both comprising P 2 Os (phosphorus oxide), on p-doped silicon substrate 302.
• Cl 2 gas produced as a byproduct, interacts with and removes metal impurities in p-doped silicon substrate 302.
• phosphorus diffuses into the silicon wafer to form a front n-doped low concentration area 304 and rear n-doped low concentration area 322.
• low dopant concentration tends to minimize recombination.
• a second oxidizing gas 336 is formed using O 2 and N 2 .
• the furnace chamber is heated to an oxidation temperature (preferably between about 800 0 C to aboutl 100 0 C, more preferably between about 95O 0 C and 1050 0 C, and most preferably at about 1000 0 C) for between about 5 minutes and 30 minutes.
• the quartz chamber is then heated to a diffusion temperature of about 900 0 C and 1100 0 C and a diffusion time period (preferably between about 5 minutes and about 60 minutes, more preferably between 15 and 30 minutes, and most preferably for about 22 minutes) in an N 2 ambient in order to drive the dopant atoms (originally in n-type doped nanoparticle layer 300 and p-type doped nanoparticles layer 301), deeper into p-doped silicon substrate 302 to form final n-doped high concentration area 312b and final p-doped high concentration area 313b.
• a diffusion temperature of about 900 0 C and 1100 0 C and a diffusion time period (preferably between about 5 minutes and about 60 minutes, more preferably between 15 and 30 minutes, and most preferably for about 22 minutes) in an N 2 ambient in order to drive the dopant atoms (originally in n-type doped nanoparticle layer 300 and p-type doped nanoparticles layer 301), deeper into p-do
• dopant atoms in front PSG layer 332 are prevented from further diffusing into p-doped silicon substrate 302 by front SiO 2 layer 307, while dopant atoms in rear PSG layer 334 are prevented from further diffusing into p- doped silicon substrate 302 by rear SiO 2 layer 340.
• front PSG layer 332 and rear PSG layer 334 may be removed using a batch HF wet bench or other suitable means.
• FIG. 4 a simplified diagram of a solar cell with a selective emitter and aluminum BSF, in accordance with the invention.
• n++ (highly doped) nanoparticle densified film 412 and n++ diffused region 414 is formed and sintered on p- (lightly doped) silicon substrate 410.
• N- diffused region 408 is then formed with a POCL 3 process.
• SiO 2 layer 406 is then formed above n- diffused region 408 in order to help passivate the front surface of silicon substrate 410, as well as to control the diffusion of phosphorous atoms during the POCL 3 process.
• SiN x 404 layer is formed on the front surface of SiO 2 layer 406. Like SiO 2 layer 406, SiN x layer 404 helps passivate the surface of silicon substrate 410, minimizing both contamination of the wafer bulk from external sources, as well as reducing minority carrier recombination at the surface of silicon substrate 410. Additionally, SiN x 404 layer may be optimized to reduce the reflectivity of the front surface of the solar cell, substantially improving efficiency and thus performance. Front-metal contact 402 and BSF/ back metal contract 408 are then formed on silicon substrate 410.
• Front-metal contact 402 is generally formed from an Ag paste comprising Ag powder (70 to 80 wt%), lead borosilicate glass PbO-B 2 O 3 -SiO 2 (1 to 10 wt%), and organic components (15 to 30 wt%).
• BSF/ back metal contract 408 is generally formed from aluminum, and is configured to create an electrical field that repels and thus minimize the impact of minority carrier rear surface recombination.
• Ag pads [not shown] are generally applied onto BSF/ back metal contract 408 in order to facilitate soldering for interconnection into modules.
• FIG. 5 a simplified diagram of a solar cell with a selective emitter and a densified film rear contact, in accordance with the invention.
• N++ (highly doped) nanoparticle densified film 512, n++ diffused region 514, p++ nanoparticle densified film rear contact 520, and p++ nanoparticle diffused region 518 are formed and sintered on p- (lightly doped) silicon substrate 510.
• Front n- diffused region 508 and rear n-diffused region 526 are then formed with a POCL 3 process.
• SiO 2 layer 506 is then formed above n- diffused region 508.
• SiN x 504 layer is then formed on the front surface of SiO 2 layer 506.
• Front-metal contact 502 and rear metal contract 408 are then formed on silicon substrate 510 using an Ag paste as previously described.
• FIG. 6 a simplified diagram comparing the reflectivity of a densified nanoparticles film and crystalline silicon on a silicon substrate, in accordance with the invention. Both surfaces are coated with a layer of thermally grown oxide and PECVD deposited nitride as described above. Wavelength in nanometers is shown on horizontal axis 602 and percentage reflectance is shown on vertical axis 604.
• SiN x is often used to reduce the reflectivity of a solar cell, and thus increase its efficiency.
• the percentage of reflectivity is related to the thickness of translucent layers through with the light passes, here principally the SiN x layer, and the absorption characteristics of the underlying surface.
• the thickness of the SiN x layer and the underlying surface for both the lightly doped emitter region and the heavily doped emitter region is crystalline silicon (or crystalline silicon covered with a layer of thin thermally grown oxide) and thus the same.
• the underlying surfaces are different and thus visually distinct.
• lightly doped emitter region 606 has optical properties (i.e. extinction coefficient and refractive index) of crystalline silicon
• densified nanoparticle thin film 608 has different optical properties that are somewhat similar to that of amorphous silicon.
• the reflectivity of lightly doped emitter region 606 has a minimum reflection point around a wavelength of 600nm resulting in a blue appearance, whereas the reflectivity of densified nanoparticle thin film 608 has no distinct minimum resulting in a white appearance. Consequently, since this difference in optical properties tends to make each surface a different color, with a high contrast between the colors, visually aligning the front metal contact on the highly doped region may be more easily done.
• FIGS. 7A-C a simplified diagram showing various electrical characteristics for different regions of a selective emitter, in accordance with the invention.
• a set of nanoparticles substrates were prepared on a lightly boron doped silicon substrate to facilitate 4-point probe measurements of the sheet resistance.
• a phosphorous-doped nanoparticle densified film 704 was formed, and upon a second portion a phosphorous diffused region was formed using PSG 702.
• sheet resistance 706 was measured.
• Sheet resistance is generally a measure of the resistance of a thin film or layer that has a uniform thickness, and is measured in Ohm/sq.
• the substrates were pre-sintered at 1000 c C for 20 seconds and diffused with a phosphorous deposition at 725 0 C for 19 minutes followed by an oxidation at 975°C for 15 minutes and an anneal at 1000 0 C for 30 minutes.
• the regions that contain the nanoparticle densified have a sheet resistance between 10 and 20 Ohm/sq while regions with the PSG are between 120-200 Ohm/sq.
• Solar cell efficiency is generally the percentage of power converted (from absorbed light to electrical energy) and collected, when a solar cell is connected to an electrical circuit, hi general, the losses of a solar cell may be broken down into reflectance losses, thermodynamic efficiency, recombination losses and resistive electrical loss.
• This term is calculated using the ratio of the maximum power point divided by the input light irradiance (in W/m 2 ) under standard test conditions (STC) and the surface area of the solar cell (m 2 ). STC specifies a temperature of 25°C and an irradiance of 1000 W/m 2 with an air mass 1.5 (AMI .5) spectrum. Maximum power is the point that maximizes the product of current (I) and voltage (V). That is I x V.
• the substrates were printed with a nanoparticle ink pattern then sintered at 1000°C for 20 seconds while the other half received no application of nanoparticle ink.
• the substrates were then diffused with a phosphorous deposition at 750°C for 26 minutes followed by an oxidation at 975°C for 15 minutes and an anneal at 1000°C for 30 minutes.
• the phosphorous doping strength in the region without ink was over 100 Ohm/sq and in the regions with ink was below 60 Ohm/sq.
• the regions that contain the nanoparticle densified have efficiency between about 12% and about 14%, while regions with the PSG are between about 2% and about 10%
• fill factor (FF) 710 was measured.
• Fill factor is the ratio of the maximum power divided by the product of the open circuit voltage (V oc ) and the short circuit current (I sc ).
• V oc open circuit voltage
• I sc short circuit current
• half of the substrates were printed with a patterned nanoparticle ink then sintered at 800 0 C for 20 seconds while the other half have no ink.
• the substrates were then diffused with a phosphorous deposition at 750 0 C for 26 minutes followed by an oxidation at 975°C for 15 minutes and an anneal at 1000 0 C for 30 minutes.
• the phosphorous doping strength in the region without ink was over 75 Ohm/sq and in the regions with ink was below 50 Ohm/sq.
• the silicon nanoparticle ink has facilitated the formation of selective doping, with heavily doped regions formed in the areas of ink application.
• the regions that contain the nanoparticle densified have FF between about 75% and about 80%, while regions with the PSG are between about 55% and about 20%.
• FIG. 8 a simplified diagram of a set if I- V curves comparing a solar cell with just a lightly doped emitter to a solar cell with a selective emitter, in accordance with the invention.
• an I-V curve may be plotted as load is varied in a solar cell from near a short circuit (zero resistance) to near the open circuit (infinite resistance).
• V voltage
• J current
• Plot 806 describes a lightly-doped emitter solar cell
• plot 808 describes a heavily-doped nanoparticle densified film selective emitter. While both cells have a front-metal contact and a rear-metal contact as previously described, lightly-doped emitter solar cell 806 has a light uniform dopant concentration throughout the silicon substrate, including the area beneath the front-metal contacts. In contrast, heavily-doped nanoparticle densified film selective emitter 808 has heavily-doped region underneath the front— metal contacts, and lightly-doped regions on substantially the remaining portions of the solar cell.
• heavily-doped nanoparticle densified film selective emitter 808 makes a better ohmic (low resistivity) contact with the front— metal contacts, corresponding to a net greater efficiency. This may be seen by area 810 on the chart, reflecting the net gain in power (and thus efficiency) enabled by the heavily-doped nanoparticle densified film.
• a selective emitter may be formed with a nanoparticle densified thin film, such that substantially high bulk lifetime and good surface recombination current density may be achieved.

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