EP2128984B1 - Gleichrichter - Google Patents

Gleichrichter Download PDF

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Publication number
EP2128984B1
EP2128984B1 EP07849867.2A EP07849867A EP2128984B1 EP 2128984 B1 EP2128984 B1 EP 2128984B1 EP 07849867 A EP07849867 A EP 07849867A EP 2128984 B1 EP2128984 B1 EP 2128984B1
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EP
European Patent Office
Prior art keywords
voltage
rectifier
boosting
mosfet
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Not-in-force
Application number
EP07849867.2A
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English (en)
French (fr)
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EP2128984B2 (de
EP2128984A4 (de
EP2128984A1 (de
Inventor
Miyuki Takeshita
Akihiko Iwata
Ikuro Suga
Shigeki Harada
Kenichi Kawabata
Takashi Kumagai
Kenji Fujiwara
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority claimed from JP2007023849A external-priority patent/JP4811948B2/ja
Priority claimed from JP2007023846A external-priority patent/JP4833101B2/ja
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of EP2128984A1 publication Critical patent/EP2128984A1/de
Publication of EP2128984A4 publication Critical patent/EP2128984A4/de
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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching
    • H03K17/302—Modifications for providing a predetermined threshold before switching in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/74—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of diodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching
    • H03K2017/307—Modifications for providing a predetermined threshold before switching circuits simulating a diode, e.g. threshold zero
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0081—Power supply means, e.g. to the switch driver

Definitions

  • the present invention relates to a rectifier connected between two external terminals, which allows a current to flow in only one direction and which blocks a current in a reverse direction.
  • a diode which is a rectifying device connected between two external terminals, operates such that when a voltage is applied in a forward direction, the diode allows a current to flow in one direction from the anode side to the cathode side, and when a reverse voltage is applied, the diode blocks a current in a reverse direction from flowing.
  • Such a general diode is used for a redundant power supply, rectifier or the like.
  • a forward voltage occurs during conduction, and a relatively large conduction loss occurs in accordance with a product of this voltage and a forward current.
  • a low power consumption diode circuit which is a conventional rectifier with low conduction loss, has an anode wire and a cathode wire, and includes a comparator, a switch and a diode.
  • the comparator has two inputs, and the anode wire is connected to one of the inputs, and the cathode wire is connected to the other input.
  • the comparator outputs a high logic level signal to an output line, and the switch switches so as to allow conduction, whereby the anode wire and the cathode wire are electronically connected (e.g., Patent Document 1).
  • a two-terminal synchronous rectifier which is another example of a conventional rectifier with low conduction loss, includes: a field-effect transistor having its source-drain path in a first arm between the two rectifier terminals; a gate-control circuit, connected to the gate electrode of the transistor, for turning on/off the transistor synchronously in accordance with voltage reversal at the two rectifier terminals; and further, a parallel arm including a charge pump formed thereon, which charge pump is driven by a voltage difference between the two rectifier terminals so as to drive the gate-control circuit.
  • a pn diode is intrinsically formed within the transistor (see, e.g.,
  • Patent Document 2 Japanese Patent Document 1
  • the conventional rectifier described in the above Patent Document 1 uses an N-MOSFET as a switch, for example. Accordingly, the conventional rectifier can reduce conduction loss as compared to a diode.
  • the conventional rectifier requires drive voltage, which causes the switch to operate, to be supplied from outside. Therefore, it is necessary to have a power source terminal in addition to the two terminals at the anode wire side and the cathode wire side. For this reason, there is a difficulty replacing a general two-terminal diode with the conventional rectifier.
  • the conventional rectifier described in the above Patent Document 2 includes the charge pump that generates, based on a voltage difference between the two rectifier terminals, a drive voltage for the gate-control circuit.
  • a capacitor of the charge pump is not charged.
  • the drive voltage for the gate control circuit cannot be retained, and the transistor is turned off.
  • the present invention solves the above problems.
  • the object of the present invention is to enable a rectifier, in which a switching device with reduced conduction loss is connected between two external terminals, to: eliminate the necessity of having an additional terminal and an external power source; readily replace a two-terminal diode; and continuously generate drive voltage when the switching device is ON, thereby allowing the switching device to continuously perform an ON operation.
  • a rectifier of the present invention is a rectifier, external terminals of which are two terminals that are an anode terminal and a cathode terminal.
  • the rectifier includes: a semiconductor switching device connected between the two terminals, which is drive-controlled via a gate electrode thereof; a parallel diode, connected in parallel to the semiconductor switching device, for performing a rectifying operation when the rectifier starts operating; and drive signal generating means for outputting a drive signal to the gate electrode of the semiconductor switching device, the drive signal generatingmeans using, as a power source, a forward voltage that occurs between the two terminals when the two terminals are conductive with each other.
  • the rectifier of the present invention includes the drive signal generating means for outputting a drive signal to the gate electrode of the semiconductor switching device, the drive signal generating means using, as a power source, a forward voltage that occurs between the two terminals when the two terminals are conductive with each other. For this reason, the rectifier does not require an additional terminal and an external power source, and can readily replace a two-terminal diode. Also, the rectifier is capable of continuously generating drive voltage when the semiconductor switching device is ON, thereby allowing the semiconductor switching device to continuously perform an ON operation.
  • FIG. 1 shows a schematic structure of the rectifier according to the first embodiment of the present invention.
  • the rectifier 1 includes: as a semiconductor switching device, a power MOSFET 2 that includes, between the source and drain thereof, a parasitic diode 2a that is a parallel diode (hereinafter, simply referred to as a MOSFET 2); a micro-power converter section 3 that is a boosting circuit; and a self-drive control section 4 that is a drive control circuit.
  • External terminals of the rectifier 1 are two terminals that are an anode terminal 11 and a cathode terminal 12.
  • the MOSFET 2 is an n-channel MOSFET whose source electrode is connected to the anode terminal 11 and whose drain electrode is connected to the cathode terminal 12.
  • micro-power converter section 3 and the self-drive control section 4 constitute drive signal generating means as claimed in claim 1 of the present invention.
  • FIG. 2 shows an operation principle of the rectifier 1 shown in FIG. 1 . Note that, in the description below, components denoted by the same reference numeral have the same function.
  • the micro-power converter section 3 and the self-drive control section 4 are each connected between the source and drain of theMOSFET 2.
  • the micro-power converter section 3 and the self-drive control section 4 Prior to the start of operation of the rectifier 1, the micro-power converter section 3 and the self-drive control section 4 are both in a halt condition, and the MOSFET 2 is nonconductive, that is, in an open state.
  • a forward voltage is applied to the rectifier 1 and a current i flows from the anode terminal 11 to the cathode terminal 12, a forward current flows through the parasitic diode 2a.
  • the rectifier 1 starts operating, and a potential difference of a few hundreds of mV, which is a voltage between both ends of the parasitic diode 2a, occurs between the source and drain of the MOSFET 2 due to a forward voltage characteristic of the parasitic diode 2a.
  • a minute voltage due to the potential difference causes the micro-power converter section 3 to start operating, and the micro-power converter section 3 starts a boosting operation.
  • the micro-power converter section 3 boosts a voltage Vds between the source and drain to a predetermined voltage, which voltage Vds occurs between the anode terminal 11 and the cathode terminal 12 during conduction when the current i flows from the anode terminal 11 to the cathode terminal 12.
  • the voltage generated by this boosting operation is supplied to the self-drive control section 4 as a power source voltage, and the self-drive control section 4 generates a gate drive signal (drive voltage Vg) for the MOSFET 2.
  • Vg gate drive signal
  • the MOSFET 2 When the current i flows through the MOSFET 2, a voltage drop occurs due to the current i and an internal resistance of the MOSFET 2, and the voltage Vds of, for example, 0.3V occurs between the source and drain of the MOSFET 2.
  • the voltage between the source and drain is supplied to the micro-power converter section 3, and the micro-power converter section 3 performs an operation to boost the voltage.
  • the boosted voltage is supplied to the self-drive control section 4 as a power source voltage. Then, the self-drive control section 4 generates the gate drive signal for the MOSFET 2. As a result, the MOSFET 2 becomes conductive.
  • the conduction voltage Vds which occurs between the source and drain when the MOSFET 2 is conductive, is boosted and the boosted voltage is fed to the self-drive control section 4, whereby the MOSFET 2 is driven continuously.
  • the micro-power converter section 3 includes: as a preceding-stage boosting section, a boosting circuit that is formed with an oscillator 31 and a charge pump 32, the oscillator 31 acting as a clock generation circuit; and as a subsequent-stage boosting section, a DC/DC converter 34 that is provided at a subsequent stage to the charge pump 32.
  • denoted by 33 is a charge-discharge capacitor included in the charge pump 32.
  • the charge pump is a switched capacitor that is a combination of a plurality of capacitors and switches.
  • the charge pump is able to start operating with a very small voltage as compared to other boosting means.
  • the DC/DC converter 34 is configured as, e.g., a boosting chopper circuit that is formed with a reactor, a diode and a switch.
  • the self-drive control section 4 includes a terminal-to-terminal voltage detection section 41 and a gate driver 42.
  • the self-drive control section 4 operates by using, as a power source, a voltage supplied from the micro-power converter section 3.
  • the output of the gate driver 42 is connected to the gate electrode of the MOSFET 2.
  • the terminal-to-terminal voltage detection section 41 and the gate driver 42 are each configured as a low-power-consumption current circuit.
  • FIG. 4 shows voltage waveforms at respective components of the rectifier 1, for the description of operations of the rectifier 1.
  • FIG. 4(a) is a waveform of a voltage Vin inputted to the micro-power converter section 3 and the self-drive control section 4.
  • the conduction voltage Vds which occurs between the source and drain of the MOSFET 2 is the voltage Vin.
  • FIG. 4 (b) shows a waveform of a voltage Vst generated by the charge pump 32.
  • FIG. 4(c) shows a waveform of a power source voltage VDD for the DC/DC converter 34.
  • FIG. 4(d) shows a waveform of an output voltage Vout of the DC/DC converter 34.
  • FIG. 4 (e) shows a waveform of an output voltage (a gate drive signal) Von of the gate driver 42.
  • the conduction voltage occurring between the source and drain of the MOSFET 2 is inputted to the micro-power converter section 3 and the self-drive control section 4 as the input voltage Vin.
  • the input voltage Vin is a forward voltage that occurs between both the ends of the parasitic diode 2a when the rectifier 1 starts operating. In practice, the input voltage Vin is slightly higher than the conduction voltage that occurs when the MOSFET 2 is ON.
  • the boosting circuit formed with the oscillator 31 and the charge pump 32 is activated by the input voltage Vin, and the input voltage Vin is boosted so as to output the voltage Vst of, for example, 2V.
  • the DC/DC converter 34 at the subsequent stage is activated by using, as the power source voltage VDD, the voltage Vst boosted by the charge pump 32.
  • the input voltage Vin is also inputted to the DC/DC converter 34.
  • the DC/DC converter 34 boosts the input voltage Vin to a predetermined voltage of, for example, 5V, and outputs the voltage as the voltage Vout.
  • the output voltage Vout of the DC/DC converter 34 is supplied to the self-drive control section 4 as a power source voltage, and at the same time, supplied to the DC/DC converter 34 for the power source voltage VDD. Accordingly, the power source voltage VDD is increased to a higher voltage level, for example, from 2V to 5V.
  • the DC/DC converter 34 is configured such that the output voltage Vout is supplied as a power source voltage for the DC/DC converter 34. Accordingly, after the DC/DC converter 34 is activated by the voltage Vst boosted by the charge pump 32, boosting operations can be repeated continuously.
  • the self-drive control section 4 operates using, as a power source voltage, the output voltage Vout of the DC/DC converter 34, which is an output from the micro-power converter section 3.
  • the input voltage Vin is inputted to the terminal-to-terminal voltage detection section 41 of the self-drive control section 4.
  • the terminal-to-terminal voltage detection section 41 When detecting conduction between the source and drain of the MOSFET 2, the terminal-to-terminal voltage detection section 41 outputs a signal to the gate driver 42, and in response to the signal outputted from the terminal-to-terminal voltage detection section 41, the gate driver 42 outputs the gate drive signal Von.
  • the terminal-to-terminal voltage detection section 41 detects the conduction between the source and drain, similarly to the case where the source and drain become conductive with each other when the MOSFET 2 is turned on.
  • the self-drive control section 4 outputs the gate drive signal Von that turns on the MOSFET 2, in order to maintain the conduction between the source and drain.
  • the micro-power converter section 3 performs a boosting operation by using, as the input voltage Vin, the conduction voltage that occurs when the source and drain are conductive with each other.
  • the DC/DC converter 34 outputs the output voltage Vout to the self-drive control section 4 as a power source voltage, and also to the DC/DC converter 34 as a power source voltage, whereby boosting operations are performed continuously.
  • the micro-power converter section 3 generates necessary voltage and the self-drive control section 4 drives the MOSFET 2, during a period when the conduction voltage is occurring between the source and drain of the MOSFET 2.
  • This series of operations allows the rectifier 1 to maintain continuous conduction while performing self feeding.
  • the rectifier 1 can readily replace a two-terminal diode. As compared to the diode, conduction loss of the rectifier 1 is reduced, and thus the rectifier 1 is more efficient.
  • the micro-power converter section 3 has a two-stage configuration including: the boosting circuit mainly formed with the oscillator 31 and the charge pump 32; and the DC/DC converter 34 provided at a subsequent stage to the charge pump 32.
  • the DC/DC converter 34 uses the output voltage Vout also for the power source voltage for the DC/DC converter 34. Accordingly, the DC/DC converter 34 is able to: generate necessary power source voltage for the DC/DC converter 34 by performing boosting operations; efficiently and stably perform continuous boosting operations; and supply the self-drive control section 4 with a power source voltage that is used as a drive voltage.
  • the oscillator 31 and the charge pump 32 are each configured to operate with a minute conduction voltage of approximately 0.3V. For this reason, the minute conduction voltage can activate the boosting operation, and the DC/DC converter 34 can be activated by the voltage boosted by the charge pump 32.
  • the rectifier 1 according to the above first embodiment can readily replace a widely used conventional two-terminal diode.
  • conduction loss of the rectifier 1 will be described in comparison to conduction loss of a two-terminal diode.
  • a conduction loss Pon which occurs when a current flows between the two terminals 11 and 12 of the rectifier 1, can be represented by a product of: the voltage Vds that occurs between the source and drain of the MOSFET 2; and a current id flowing between the source and drain.
  • the conduction loss Pon decreases in accordance with a decrease in the value of the on-resistance Rdson of the MOSFET 2.
  • the on-resistance Rdson of the MOSFET 2 ranges from a few tens of m ⁇ to approximately 2 ⁇ .
  • FIG. 5(a) shows a comparison between a voltage of the rectifier 1 during conduction and a voltage of a conventional diode during conduction.
  • the rectifier 1 which uses the MOSFET 2 having a withstand voltage of 300V-class, is compared below with a diode having the same withstand voltage of 300V-class.
  • the forward voltage of the diode is approximately 0.8V when the forward current of approximately 10A flows through the diode.
  • the voltage Vds that occurs between the source and drain of the MOSFET 2 is approximately 0. 6V
  • this conduction voltage of the rectifier 1 is lower by 0.2V than the conduction voltage of approximately 0.8V of the diode.
  • the conduction loss Pon (6W) of the rectifier 1 is reduced by 25% from the conduction loss Pon-d (8W) of the diode.
  • FIG. 5(b) shows measurement data that shows a comparison between the conduction voltage of the rectifier 1, which uses the MOSFET 2 having the withstand voltage of 300V-class, and the conduction voltage of a diode having a withstand voltage of 400V-class. This case also shows that the conduction voltage of the rectifier 1 is lower than that of the diode, and the conduction loss of the rectifier 1 is reduced from that of the diode.
  • the present invention has a configuration in which the power for the micro-power converter section 3 and the self-drive control section 4 to drive the MOSFET 2 is supplied from both the terminals 11 and 12 of the main circuit.
  • the conduction voltage of the MOSFET 2 as shown in FIG. 5 represents a voltage in such a manner as to include a loss that occurs in the above micro-power converter section 3 and in the self-drive control section 4.
  • FIG. 6 shows comparison results in the same manner.
  • FIGS. 6(a) and 6(b) respectively show measurement data measured in cases where the conduction voltage of the rectifier 1 is approximately half of that of the diode. These cases both show that when an instance where the forward current of approximately 10A flows through the rectifier 1 and an instance where the forward current of approximately 10A flows through the diode are compared, the conduction voltage of the rectifier 1 is approximately half of that of the diode, and the conduction loss Pon of the rectifier 1 is reduced, approximately by half, from the conduction loss Pon-d of the diode.
  • the conduction voltage Vds that occurs between the source and drain of the MOSFET 2 is a product of the current Id and the on-resistance Rdson, the conduction voltage Vds can be reduced in accordance with a decrease in the on-resistance Rdson, and also, the conduction loss can be reduced.
  • the MOSFET 2 whose on-resistance Rdson is sufficiently small is to be used.
  • the above first embodiment describes that the DC/DC converter 34 is included in the micro-power converter section 3.
  • a rectifier in which the micro-power converter section having a different configuration is used, will be described with reference to FIG. 7 .
  • components other than the micro-power converter section and operations performed by these components are the same as those described in the above first embodiment.
  • a micro-power converter section 3a includes the same boosting circuit as that described in the above first embodiment, which is formed with the oscillator 31 and the charge pump 32. Further, another charge pump 32a is provided at a subsequent stage to the charge pump 32.
  • the boosting circuit formed with the oscillator 31 and the charge pump 32 is activated by the input voltage Vin, and the input voltage Vin is boosted to output the voltage Vst of, for example, 2V.
  • the charge pump 32a provided at the subsequent stage performs a boosting operation on the voltage Vst boosted by the charge pump 32, and outputs a predetermined voltage, for example, the voltage Vout of 5V, to the self-drive control section 4.
  • the self-drive control section 4 drives the MOSFET 2.
  • a conduction voltage occurs between the source and drain of the MOSFET 2. This conduction voltage is inputted as the input voltage Vin to the micro-power converter section 3a and the self-drive control section 4, whereby the operations continue.
  • multi-stage charge pumps e.g., charge pumps provided at three stages or more
  • the output voltage Vout of, for example, 5V can be generated from a minute conduction voltage between the source and drain, and the generated output voltage Vout can be outputted to the self-drive control section 4 as a power source voltage.
  • the micro-power converter section 3a generates necessary voltage and the self-drive control section 4 drives the MOSFET 2, during a period when the conductive voltage is occurring between the source and drain of the MOSFET 2.
  • This series of operations allows the rectifier to maintain continuous conduction while performing self feeding.
  • the rectifier can readily replace a two-terminal diode. As compared to the diode, conduction loss of the rectifier is reduced, and thus the rectifier is more efficient.
  • a micro-power converter section 3b which includes the oscillator 31 and a single charge pump 32b, may be formed as shown in 7(b).
  • 33b is a charge-discharge capacitor included in the charge pump 32b.
  • the charge pump 32b has to be a high-performance charge pump that is able to generate the output voltage Vout of, for example, 5V from a minute conduction voltage between the source and drain.
  • the MOSFET 2 can be turned on based on the conduction voltage without using the boosting circuit. Also in this case, the effect, in which the rectifier can maintain the continuous conduction while performing self feeding, is provided.
  • the n-channel power MOSFET 2 including the parasitic diode 2a is used in the rectifier as a semiconductor switching device.
  • a p-channel power MOSFET may be used instead.
  • other semiconductor switching device such as a SiC transistor that is drive-controlled via the gate electrode may be used instead.
  • the same operation can be performed and the same effect can be obtained by connecting, along a forward direction, a parallel diode to the semiconductor switching device.
  • FIG. 8 is a block diagram showing a brief configuration of a rectifier according to the fourth embodiment of the present invention.
  • the rectifier includes reverse voltage protection circuits that protect, when a reverse voltage is applied between two terminals, i.e., A and K terminals, of the rectifier, a boosting circuit and a drive control circuit from the application of the reverse voltage.
  • the rectifier includes: an n-channel power MOSFET S1 including a parasitic diode between the source and drain thereof (hereinafter, referred to as a MOSFET S1); a gate control circuit 51 that acts as a drive control circuit for drive-controlling the MOSFET S1; a boosting circuit 52 for generating a power source voltage for the gate control circuit 51; a power source switching circuit 53; protection circuits 54 to 57 that act as reverse voltage protection circuits; and a power supply control switch S3 that acts as a control switching device for controlling a supplying, as a power source, of an output of the boosting circuit 52 to the gate control circuit 51.
  • a MOSFET S1 n-channel power MOSFET S1 including a parasitic diode between the source and drain thereof
  • External terminals of the rectifier are two terminals that are an anode terminal A and a cathode terminal K.
  • the source electrode and the drain electrode of the MOSFET S1 are connected to the anode terminal A and the cathode terminal K, respectively.
  • C1 is a boosting capacitor included in the boosting circuit 52.
  • the gate control circuit 51 and the boosting circuit 52 are both in a halt condition, and the MOSFET S1 is in the OFF state.
  • a forward voltage is applied to the rectifier and a current flows from the anode terminal A to the cathode terminal K, a forward current flows through the parasitic diode, whereby a forward voltage of the parasitic diode occurs between the source and drain.
  • This voltage is a positive voltage for which the drain electrode is a reference of potential.
  • This voltage is supplied to the boosting circuit 52 to activate the boosting circuit 52.
  • the boosting circuit 52 boosts the voltage that occurs between the source and drain when the current flows from the anode terminal A to the cathode terminal K.
  • the boosting circuit 52 boosts the forward voltage of the parasitic diode, and a predetermined voltage is accumulated at the boosting capacitor C1.
  • the voltage of the boosting capacitor C1 is supplied via the power supply control switch S3 to the gate control circuit 51 as a power source voltage (a drive voltage), and the gate control circuit 51 generates a gate drive signal for the MOSFET S1.
  • the gate control circuit 51 detects that the voltage between the source and drain of the MOSFET S1 is a positive voltage for which the drain electrode is a reference of potential. That is, the gate control circuit 51 detects conduction between the source and drain, and generates the gate drive signal so as to drive the gate electrode. Accordingly, the MOSFET S1 is turned on.
  • the power source switching circuit 53 operates in response thereto.
  • the voltage of the boosting capacitor C1 is supplied to the boosting circuit 52 as a power source voltage.
  • the MOSFET S1 When the MOSFET S1 is turned on, a current flows from the anode terminal A to the cathode terminal K through the MOSFET S1. Then, a voltage drop occurs due to the current and the on-resistance of the MOSFET S1, and a voltage occurs between the source and drain.
  • the voltage between the source and drain is a positive voltage for which the drain electrode is a reference of potential.
  • the voltage is inputted to the boosting circuit 52.
  • the boosting circuit 52 performs a boosting operation on the voltage, and the boosted voltage is supplied to both the boosting circuit 52 and the gate control circuit 51 as a power source voltage. Then, the gate control circuit 51 generates a gate drive signal for the MOSFET S1. As a result, the MOSFET S1 is turned on.
  • the voltage which occurs between the source and drain when the MOSFET S1 is conductive, is boosted, and the boosted voltage is fed to both the boosting circuit 52 and the gate control circuit 51, whereby the MOSFET S1 is driven continuously.
  • the protection circuit 54 blocks the reverse voltage from being applied to the gate control circuit 51, and the protection circuit 56 blocks the reverse voltage from being applied to the boosting circuit 52. Further, the protection circuits 55 and 57 are provided. In this manner, paths, through which a current flows in such a reverse voltage state from the cathode terminal K toward the anode terminal A, can be blocked. Thus, since the protection circuits 54 to 57 for reverse voltage protection are provided, destruction of the boosting circuit 52 and the gate control circuit 51 can be prevented.
  • the voltage occurring between the source and drain when the MOSFET S1 is conductive is boosted, and the boosted voltage is fed to both the boosting circuit 52, and the gate control circuit 51, whereby the MOSFET S1 is continuously driven.
  • a drive voltage of, for example, 5V for driving the gate electrode of the MOSFET S1 it is not necessary to supply, from outside, a drive voltage of, for example, 5V for driving the gate electrode of the MOSFET S1, and the gate control circuit 51 is able to continuously drive-control the MOSFET S1.
  • the rectifier can readily replace a two-terminal diode.
  • the on-resistance of MOSFETs vary depending on the performance of each MOSFET such as the withstand voltage, shape or the like. In cases of, for example, low on-resistance values, there exist devices whose on-resistance is approximately a few tens of m ⁇ . Assuming that the on-resistance of the MOSFET S1 is 20m ⁇ , when the value of a current flowing from the anode terminal A to the cathode terminal K is, for example, 10A, the drop voltage is 0.2V.
  • a forward voltage of an SBD (Schottky Diode) having a low withstand voltage is 0.6 to 1.0V
  • a forward voltage of an FRD (Fast Recovery Diode) having a high withstand voltage is 1.0V to 3.0V.
  • the drop voltage of the MOSFET S1 is substantially small, that is, low loss. Therefore, the rectifier according to the present embodiment can readily replace a two-terminal diode. As compared to the diode, conduction loss of the rectifier is reduced, and thus the rectifier is more efficient.
  • the boosting circuit 52 is activated by a forward voltage that occurs between the source and drain when a forward current flows through the parasitic diode. Thereafter, the power source switching circuit 53 performs switching such that an output from the boosting circuit 52 is used as a power source for the boosting circuit 52. Accordingly, the boosting circuit 52 is able to start operating without power supply from the outside, and efficiently continue to perform stable boosting operations.
  • a conventional MOSFET circuit is configured such that the source electrode thereof is used as a reference of potential, and the MOSFET is driven by a drive voltage applied between the source and gate.
  • the MOSFET S1 is configured as an n-channel circuit such that the drain electrode thereof is used as a reference of potential, and a positive drive voltage is applied between the drain and gate.
  • a voltage between the source and drain which is an input voltage of the boosting circuit 52, is a positive voltage for which the drain electrode is a reference of potential, and the positive voltage is boosted to, for example, approximately 5V so as to be used as a positive drive voltage.
  • the gate control circuit 51 directly uses the boosted voltage as a power source voltage (a drive voltage). For this reason, the boosting circuit 52 and the gate control circuit 51 can be readily configured, and this realizes a small-sized and simplified configuration of the rectifier.
  • the gate control circuit 51 performs control so as to cause the MOSFET S1 to continuously perform an ON operation.
  • the value of the drop voltage between the source and drain when the MOSFET S1 is ON is small in the first place.
  • the drive voltage, for which the drain electrode is a reference of potential can be used as a voltage that is at substantially the same level as a voltage for which the source electrode is a reference of potential.
  • FIG. 9 shows a circuit configuration of the rectifier, according to the fifth embodiment of the present invention.
  • a comparator 61 is used as the gate control circuit 51 of FIG. 8
  • the boosting circuit 52 is formed with a boost converter 62, a boosting coil L1, the boosting capacitor C1, a boosting switch S2 and a boosting diode D1.
  • the power source switching circuit 53 is formed with a power source switching diode D2 and a power source switching resistor R2.
  • a reverse voltage protection device DZ1 and a reverse current prevention device DS3 are provided as control circuit protection devices to be included in the protection circuit 54.
  • boosting circuit protection devices DZ2 and D3 are provided as reverse voltage protection devices to be included in the protection circuit 56.
  • a reverse current prevention device DS1 is provided as a reverse current prevention device to be included in the protection circuit 55
  • a reverse current prevention switch DS2 is provided as a reverse current prevention device to be included in a protection circuit 57.
  • the power supply control switch S3 is provided as a semiconductor switching device for controlling power supply to the comparator 61.
  • R1 is a voltage detection resistor
  • R3 is an erroneous operation prevention resistor for preventing erroneous operations of the MOSFET S1
  • R4 and R5 are control resistors of the power supply control switch S3.
  • the comparator 61 and the boost converter 62 are both in a halt condition, and the MOSFET S1 is in the OFF state.
  • a current flows from the anode terminal A to the cathode terminal K, a forward current flows through the parasitic diode of the MOSFET S1, whereby a forward voltage of the parasitic diode occurs between the source and drain.
  • This voltage is a positive voltage for which the drain electrode is a reference of potential and which is supplied to the boost converter 62.
  • a difference voltage between the forward voltage of the parasitic diode of the MOSFET S1 and a forward voltage of the reverse current prevention device DS1 is set to be equal to or higher than a voltage that activates the boost converter 62, and the difference voltage activates the boost converter 62.
  • the forward voltage of the parasitic diode of the MOSFET S1 is required to be greater than the forward voltage of the reverse current prevention device DS1.
  • the former current is substantially greater than the latter, and as shown in FIG. 5 previously referred to, a forward voltage of a diode, i.e., a voltage that occurs when a current is applied, increases in accordance with an increase in the applied current. Therefore, there is no particular difficulty satisfying the above requirement.
  • the reverse current prevention switch DS2 is controlled based on a drive signal of the comparator 61.
  • a forward voltage of a parasitic diode (parallel diode) of the reverse current prevention switch DS2 is set to be lower than the forward voltage of the parasitic diode of the MOSFET S1. There is also no difficulty satisfying such setting for the same reason as that described above in relation to the forward voltage of the reverse current prevention device DS1.
  • the MOSFET S1 and the reverse current prevention switch DS2 are both controlled based on the drive signal of the comparator 61, a MOSFET alone having the same or higher performance than the MOSFET S1, or such a MOSFET and a diode which are in parallel to each other, are disposed as the reverse current prevention switch DS2, and the reverse current prevention switch DS2 performs an ON operation as fast as, or faster than, the MOSFET S1. Accordingly, a drop voltage at a boosting path of the boosting circuit can be reduced. At the ON operation of the MOSFET S1 as well as after the MOSFET S1 is turned on, a positive voltage is inputted to the boosting coil L1, whereby a boosting operation is enabled.
  • the boost converter 62 When activated, the boost converter 62 boosts a voltage that is inputted to the boosting coil L1 through the forward voltage of the parasitic diode of the MOSFET S1 (the difference voltage between the forward voltage of the parasitic diode of the MOSFET S1 and the forward voltage of the parasitic diode of the reverse current prevention switch DS2). Accordingly, a predetermined voltage of, for example, 5V is accumulated at the boosting capacitor C1. When the predetermined voltage is accumulated at the boosting capacitor C1, the power supply control switch S3 is turned on, and the voltage of 5V is supplied to the comparator 61 as a power source voltage (a drive voltage).
  • the comparator 61 detects that a voltage between the source and drain of the MOSFET S1 is a positive voltage for which the drain electrode is a reference of potential, i.e., the comparator 61 detects conduction between the source and drain. Then, the comparator 61 applies, to the gate electrode, a Hi signal that is a gate drive signal, thereby turning on the MOSFET S1.
  • the value of the voltage is 2 to 4V. Accordingly, outputting the Hi signal, which is the same as the power source voltage of 5V, between the drain and gate of the MOSFET S1 is sufficient for the comparator 61 to turn on the MOSFET S1.
  • the voltage of the boosting capacitor C1 is supplied, using the power source switching diode D2 and the power source switching resistor R2, to the boost converter 62 as a power source voltage. For this reason, a potential difference between the source and drain decreases after the MOSFET S1 is turned on. As a result, even if the voltage inputted to the boost converter 62 through the reverse current prevention device DS1 is decreased, a boosting operation can be stably performed by using the power source voltage that is provided via the power source switching diode D2 and the power source switching resistor R2. As a result of this operation, the power source voltage is also stably supplied to the comparator 61.
  • the MOSFET S1 When the MOSFET S1 is turned on, a current flows from the anode terminal A to the cathode terminal K through the MOSFET S1. Then, a voltage drop occurs due to the current and the on-resistance of the MOSFET S1, and a voltage occurs between the source and drain.
  • the voltage between the source and drain is a positive voltage for which the drain electrode is a reference of potential.
  • the positive voltage is inputted to the boosting coil L1, and the boost converter 62 drives the boosting switch S2 to accumulate voltage at the boosting capacitor C1.
  • the voltage accumulated at the boosting capacitor C1 is supplied to both the boost converter 62 and the comparator 61 as a power source voltage. Then, the comparator 61 generates the gate drive signal for the MOSFET S1, and the MOSFET S1 is turned on, accordingly.
  • the voltage which occurs between the source and drain when the MOSFET S1 is conductive, is boosted, and the boosted voltage is fed to both the boost converter 62 and the comparator 61, whereby the MOSFET S1 is driven continuously.
  • the control circuit protection device DZ1 blocks a reverse voltage to the input voltage of the comparator 61.
  • the boosting circuit protection device DZ2 blocks a reverse voltage from being applied to the boost converter 62.
  • the boosting circuit protection device D3 blocks a reverse voltage frombeing applied to the boosting switch S2.
  • the power supply control switch S3 is turned off if the voltage of the boosting capacitor C1 decreases at a timing of switching from the positive characteristic to the inverse characteristic in which the potential of the cathode terminal K is higher than that of the anode terminal A. Accordingly, the power supply to the comparator 61 is cut off. In this manner, the drive control of the MOSFET S1 by the comparator 61 is completely ceased during such an inverse characteristic period, without causing the MOSFET S1 to be turned on due to a control delay or erroneous operation. This assuredly prevents a current from flowing in the reverse voltage state from the cathode terminal K to the anode terminal A.
  • a p-channel MOSFET is used as the power supply control switch S3, and the resistors R4 and R5 are used for ON/OFF control.
  • the same effects can be obtained by using ICs for the ON/OFF control, instead.
  • the same control can still be performed by using an operational amplifier.
  • the gate drive capability thereof is improved.
  • control as to cause the reverse current prevention switch DS2 to perform an ON operation at an earlier timing than the MOSFET S1, can be performed.
  • the MOSFET S1 can be formed with multiple MOSFETs.
  • boost converter 62 is used as the boosting circuit 52, a different boosting circuit such as a charge pump or the like may be applied to obtain the same effects.
  • the above-described reverse voltage protection circuits are provided in order to protect, when a reverse voltage is applied between the two terminals, i.e., the A and K terminals, of the rectifier, the boosting circuit and the drive control circuit from the application of the reverse voltage.
  • the necessity of additionally providing the reverse voltage protection circuits is eliminated when the boosting circuit and the drive control circuit have necessary voltage-withstanding characteristics.
  • the rectifier according to the present invention does not require power supply from outside and can stably continue to perform operations in the ON state. For this reason, the rectifier can readily replace a two-terminal diode. As compared to the diode, conduction loss of the rectifier is reduced, and thus the rectifier improves efficiency. Therefore, the present invention is expected to provide substantial advantages by being applied to a wide range of electrical equipments including diodes.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Power Conversion In General (AREA)
  • Rectifiers (AREA)

Claims (14)

  1. Gleichrichter (1), welcher externe Anschlüsse enthält, von denen zwei Anschlüsse ein Anoden-Anschluss (11) und ein Kathoden-Anschluss (12) sind, wobei der Gleichrichter (1) enthält:
    eine Halbleiter-Umschaltvorrichtung (2), welche zwischen den zwei Anschlüssen verbunden ist, welche über eine Gate-Elektrode hiervon antriebsmäßig gesteuert wird;
    eine parallele Diode (2a), welche parallel zur Halbleiter-Umschaltvorrichtung (2) verbunden ist, um eine Gleichrichtungs-Operation durchzuführen, wenn der Gleichrichter (1) mit seiner Operation beginnt; und
    ein Antriebssignal-Erzeugungselement zum Ausgeben eines Antriebssignals an die Gate-Elektrode von der Halbleiter-Umschaltvorrichtung (2),
    dadurch gekennzeichnet, dass
    das Antriebssignal-Erzeugungselement als Energiequelle eine Durchlassspannung verwendet, welche zwischen den zwei Anschlüssen anliegt, wenn die zwei Anschlüsse zueinander leitend sind.
  2. Gleichrichter (1) nach Anspruch 1, bei welchem das Antriebssignal-Erzeugungselement enthält:
    eine Verstärkungsschaltung (3) zum Verstärken der Durchlassspannung, welche zwischen den zwei Anschlüssen anliegt, wenn die zwei Anschlüsse zueinander leitend sind, auf eine vorbestimmte Spannung; und
    eine Antriebssteuerschaltung (4) zum Ausgeben des Antriebssignals an die Gate-Elektrode von der Halbleiter-Umschaltvorrichtung (2), wobei die Antriebssteuerschaltung (4) eine Ausgabe der Verstärkungsschaltung (3) als eine Energiequelle verwendet.
  3. Gleichrichter (1) nach Anspruch 2, bei welchem die Antriebssteuerschaltung (4) das Antriebssignal in Übereinstimmung mit der Durchlassspannung, welche zwischen den zwei Anschlüssen anliegt, ausgibt.
  4. Gleichrichter (1) nach Anspruch 2, bei welchem:
    die Verstärkungsschaltung (3) ihre Ausgabe als eine Spannung-Stromquelle verwendet, um den Betrieb der Verstärkungsschaltung (3) zu veranlassen; und
    zu Beginn der Operation von der Verstärkungsschaltung (3), die Verstärkungsschaltung (3) basierend auf der Durchlassspannung operiert, welche zwischen beiden Enden von der parallelen Diode (2a) anliegt.
  5. Gleichrichter (1) nach Anspruch 4, bei welchem:
    die Verstärkungsschaltung (3) mit einer Vorstufen-Verstärkungssektion (31-33) und einer Nachstufen-Verstärkungssektion (34) ausgebildet ist; und
    die Nachstufen-Verstärkungssektion (34) durch eine Spannung aktiviert wird, welche durch die Vorstufen-Verstärkungssektion (31-33) verstärkt ist, und die Durchlassspannung, welche zwischen den zwei Anschlüssen anliegt, auf die vorbestimmte Spannung verstärkt und die vorbestimmte Spannung ausgibt, und die ausgegebene vorbestimmte Spannung als eine Spannung-Stromquelle verwendet, um die Operation der Nachstufen-Verstärkungssektion (34) zu veranlassen.
  6. Gleichrichter (1) nach Anspruch 5, bei welchem die Vorstufen-Verstärkungssektion eine Ladungspumpe (32) enthält, und die Nachstufen-Verstärkungssektion einen DC/DC-Umwandler (34) enthält.
  7. Gleichrichter (1) nach Anspruch 4, bei welchem die Verstärkungsschaltung (52) eine Stromquelle-Umschaltschaltung (53) zum Umschalten einer Stromquelle-Verbindung von der Verstärkungsschaltung (52) enthält, so dass die Verstärkungsschaltung (52) zu Beginn ihrer Operation basierend auf der Durchlassspannung, welche zwischen den zwei Anschlüssen anliegt, operiert, und, nach dem Beginn der Operation, eine Ausgangsspannung von der Verstärkungsschaltung (52) als eine Stromquelle für die Verstärkungsschaltung (52) verwendet.
  8. Gleichrichter (1) nach Anspruch 7, bei welchem:
    die Verstärkungsschaltung einen Kondensator (C1) zum Akkumulieren einer verstärkten Spannung enthält;
    und die Stromquelle-Umschaltschaltung (53) die Umschaltung derart durchführt, dass die Verstärkungsschaltung (52) zu Beginn ihrer Operation basierend auf der Durchlassspannung operiert, welche zwischen den zwei Anschlüssen anliegt, und nach dem Beginn der Operation die Spannung von dem Kondensator (C1) als Stromquelle für die Verstärkungsschaltung (52) verwendet.
  9. Gleichrichter (1) nach Anspruch 2, bei welchem die Halbleiter-Umschaltschaltung (2) ein Leistungs-MOSFET ist, welcher eine parasitäre Diode (2a) zwischen Source und Drain hiervon enthält, und wobei die parasitäre Diode (2a) die parallele Diode ist.
  10. Gleichrichter (1) nach Anspruch 9, bei welchem:
    der Leistungs-MOSFET (S1) ein n-Kanal-MOSFET ist, wobei eine Drain-Elektrode hiervon mit dem Kathoden-Anschluss (K) verbunden ist, und eine Source-Elektrode hiervon mit dem Anoden-Anschluss (A) verbunden ist, und wobei die Verstärkungsschaltung (52) als eine Eingangs-/Ausgangs-Spannung hiervon eine positive Spannung verwendet, für welche die Drain-Elektrode von dem MOSFET (S1) eine Potentialreferenz ist, und wobei der MOSFET (S1) in Übereinstimmung mit dem Antriebssignal operiert, welches auf der positiven Spannung basiert, für welche die Drain-Elektrode eine Potentialreferenz ist.
  11. Gleichrichter (1) nach Anspruch 2, welcher ferner eine Sperrspannung-Schutzschaltung (54-57) enthält, um, wenn eine Sperrspannung zwischen den zwei Anschlüssen anliegt, die Verstärkungsschaltung (52) und die Antriebssteuerschaltung (51) gegen ein Anliegen der Sperrspannung zu schützen.
  12. Gleichrichter (1) nach Anspruch 11, bei welchem die Sperrspannung-Schutzschaltung enthält:
    eine Sperrspannung-Schutzvorrichtung (54, 56), um gegen das Anlegen der Sperrspannung zu schützen; und
    eine Sperrstrom-Schutzvorrichtung (55, 57), um dagegen zu schützen, dass ein Sperrstrom vom Kathoden-Anschluss (K) über die Sperrspannung-Schutzvorrichtung (54, 56) an den Anoden-Anschluss (A) fließt.
  13. Gleichrichter (1) nach Anspruch 12, bei welchem eine Umschaltvorrichtung (DS2), welche basierend auf dem Antriebssignal, welches von der Antriebssteuerschaltung (51) ausgegeben wird, gesteuert wird, als die Sperrstrom-Schutzvorrichtung verwendet wird.
  14. Gleichrichter (1) nach Anspruch 2, welcher ferner eine Steuerumschaltvorrichtung (S3) enthält, um eine Versorgung, als eine Stromquelle, von einer Ausgabe von der Verstärkungsschaltung (62) an die Antriebssteuerschaltung (61) zu steuern, wobei,
    wenn eine Sperrspannung zwischen den zwei Anschlüssen anliegt, die Steuerumschaltvorrichtung (S3) ausgeschaltet wird, und hierdurch die Halbleiter-Umschaltvorrichtung (S1) ausgeschaltet wird, wodurch verhindert wird, dass ein Sperrstrom vom Kathoden-Anschluss (K) über die Halbleiter-Umschaltvorrichtung (S1) an den Anoden-Anschluss (A) fließt.
EP07849867.2A 2007-02-02 2007-12-20 Gleichrichter Not-in-force EP2128984B2 (de)

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Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5398912B2 (ja) * 2009-07-09 2014-01-29 マイクロセミ コーポレィション 低電圧降下閉ループ単方向電子バルブ
CN102694370A (zh) * 2011-03-22 2012-09-26 飞毛腿(福建)电子有限公司 一种电源正端关断保护的方法
DE102011083234A1 (de) * 2011-09-22 2013-03-28 Robert Bosch Gmbh Verfahren zum Ansteuern eines MOSFET im Rückwärtsbetrieb
JP5728350B2 (ja) * 2011-09-27 2015-06-03 新電元工業株式会社 スイッチ素子駆動回路
US8508898B2 (en) 2012-01-11 2013-08-13 Robert Bosch Gmbh Diagnosable reverse-voltage protection for high power loads
WO2013112157A1 (en) * 2012-01-26 2013-08-01 Georgia Tech Research Corporation Self-sustained synchronous rectifier
US9225253B2 (en) * 2012-10-23 2015-12-29 Microchip Technology Inc. High voltage switching linear amplifier and method therefor
US8884684B2 (en) * 2012-10-29 2014-11-11 System General Corporation Charge pump circuits having frequency synchronization with switching frequency of power converters
KR101502153B1 (ko) * 2013-04-30 2015-03-12 주식회사 맵스 능동 다이오드 드라이버
KR101440120B1 (ko) * 2013-06-03 2014-09-12 주식회사 맵스 트랜지스터 턴 오프 제어 방식이 개선된 능동 다이오드
KR101462610B1 (ko) * 2013-06-27 2014-11-20 주식회사 맵스 트랜지스터 턴 오프 제어 방식이 개선된 능동 다이오드
US9306464B2 (en) * 2013-09-04 2016-04-05 System General Corporation Synchronous rectifier control circuits of power converters
DE102015011718A1 (de) 2014-09-10 2016-03-10 Infineon Technologies Ag Gleichrichtervorrichtung und Anordnung von Gleichrichtern
US10128833B2 (en) 2015-07-31 2018-11-13 Texas Instruments Incorporated Millivolt power harvesting FET controller
US20170033793A1 (en) * 2015-07-31 2017-02-02 Texas Instruments Incorporated Millivolt power harvesting fet controller
DE102016124611A1 (de) * 2016-12-16 2018-06-21 Infineon Technologies Ag Schaltervorrichtung und -verfahren
FR3068847B1 (fr) * 2017-07-06 2020-12-18 Alstom Transp Tech Dispositif de commutation pour transistor sic ou gan mosfet avec circuit de protection contre les surtensions et procede associe
US10756616B2 (en) * 2018-06-22 2020-08-25 Semiconductor Components Industries, Llc Methods and systems of a rectifier circuit
CN111181536B (zh) * 2018-11-13 2024-01-02 市光法雷奥（佛山）汽车照明系统有限公司 开关电路
TWI678876B (zh) * 2019-01-08 2019-12-01 朋程科技股份有限公司 交流發電機以及整流裝置
US11664799B2 (en) * 2021-03-18 2023-05-30 Richtek Technology Corporation Analog switch circuit and control circuit and control method thereof
TWI764795B (zh) * 2021-04-09 2022-05-11 立錡科技股份有限公司 返馳式電源轉換器與其中之切換式電容轉換電路
EP4145702B1 (de) * 2021-09-06 2024-04-24 Axis AB Normalerweise geschlossenes festkörperrelais unter verwendung von normalerweise offenen komponenten

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5627460A (en) 1994-12-28 1997-05-06 Unitrode Corporation DC/DC converter having a bootstrapped high side driver
US6060943A (en) 1998-04-14 2000-05-09 Nmb (Usa) Inc. Circuit simulating a diode
US20030042938A1 (en) 2001-09-06 2003-03-06 Shvarts Emanuil Y. Equivalent shottky or emanuil shvarts diode (ESD)
US6747880B2 (en) 2001-03-28 2004-06-08 Koninklijke Philips Electronics N.V. Self-powered synchronous rectifiers
WO2007083008A2 (fr) 2006-01-23 2007-07-26 Valeo Equipements Electriques Moteur Dispositif de commande d'un transistor mos
JP2008193283A (ja) 2007-02-02 2008-08-21 Mitsubishi Electric Corp 整流装置
JP2008193282A (ja) 2007-02-02 2008-08-21 Mitsubishi Electric Corp 整流装置
EP2092643B1 (de) 2006-11-16 2014-03-12 Valeo Equipements Electriques Moteur Glied für eine synchron-gleichrichterbrücke, diesbezügliche synchron-gleichrichterbrücke und verwendung dafür

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5506527A (en) 1994-04-15 1996-04-09 Hewlett-Packard Compnay Low power diode
EP0843404A4 (de) * 1996-06-05 2001-05-16 Ntt Data Corp Elektrische schaltung
JPH11146640A (ja) * 1997-11-10 1999-05-28 Nec Corp スイッチング電源用整流回路およびこの整流回路を用いたスイッチング電源
US6469564B1 (en) 1998-04-14 2002-10-22 Minebea Co., Ltd. Circuit simulating a diode
US6747441B2 (en) * 2002-08-20 2004-06-08 Texas Instruments Incorporated Non-synchronous switching regulator with improved output regulation at light or low loads
US7034602B2 (en) * 2004-03-29 2006-04-25 Semiconductor Components Industries, L.L.C. Method of forming a floating charge pump and structure therefor
US7199636B2 (en) 2004-03-31 2007-04-03 Matsushita Electric Industrial Co., Ltd. Active diode
DE112005000026T5 (de) * 2004-07-01 2006-07-27 Murata Mfg. Co., Ltd., Nagaokakyo Gleichspannungswandler und Wandlervorrichtung

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5627460A (en) 1994-12-28 1997-05-06 Unitrode Corporation DC/DC converter having a bootstrapped high side driver
US6060943A (en) 1998-04-14 2000-05-09 Nmb (Usa) Inc. Circuit simulating a diode
US6747880B2 (en) 2001-03-28 2004-06-08 Koninklijke Philips Electronics N.V. Self-powered synchronous rectifiers
US20030042938A1 (en) 2001-09-06 2003-03-06 Shvarts Emanuil Y. Equivalent shottky or emanuil shvarts diode (ESD)
WO2007083008A2 (fr) 2006-01-23 2007-07-26 Valeo Equipements Electriques Moteur Dispositif de commande d'un transistor mos
EP2092643B1 (de) 2006-11-16 2014-03-12 Valeo Equipements Electriques Moteur Glied für eine synchron-gleichrichterbrücke, diesbezügliche synchron-gleichrichterbrücke und verwendung dafür
JP2008193283A (ja) 2007-02-02 2008-08-21 Mitsubishi Electric Corp 整流装置
JP2008193282A (ja) 2007-02-02 2008-08-21 Mitsubishi Electric Corp 整流装置

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JONATHAN DODGE: "Power MOSFET Tutorial", APPLICATION NOTE APT-0403 REV B, 2 March 2006 (2006-03-02), pages 1 - 12, XP055251257
M CORREVON: "Electronique de puissance", HES-SO, article "Chapitre 7: Les semiconducteurs de puissance - Deuxieme partie: LE MOSFET", pages: 1 - 38, XP055375375

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US20100073082A1 (en) 2010-03-25
EP2128984A4 (de) 2013-01-16
EP2128984A1 (de) 2009-12-02
WO2008096393A1 (ja) 2008-08-14
US8232830B2 (en) 2012-07-31

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