Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C5/00—Details of stores covered by group G11C11/00
  • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
  • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Definitions

• the present invention relates to a method for detecting a supply interruption in a volatile data memory and for restoring the content of such a memory in the event that a supply interruption is detected.
• Such a method is applicable to volatile data storage of any kind;
• a preferred field of application are data memories of programmed control devices, in particular for motor vehicle applications.
• Modern control devices of this type often work with adaptive algorithms whose parameters they individually over time to the machine to be controlled, z. B. adapt the engine of a motor vehicle. This requires that the controller be able to store the optimized parameters of these algorithms over time.
• As memory for such data in particular EEPROMs or SRAMs are used. Due to the long writing times required for EEPROMs, predominantly SRAMs (static buffered RAM) are used.
• SRAMs require a continuous supply voltage. After an interruption of the supply voltage, the contents of these memories may be corrupted, and a control based on incorrect parameter values can not be correct
• a first approach is the direct, continuous monitoring of the supply voltage by comparing it with a minimum voltage, which may be dependent on the type of data memory used, below which a loss or at least a high probability of falsification of the data can be assumed.
• a minimum voltage which may be dependent on the type of data memory used, below which a loss or at least a high probability of falsification of the data can be assumed.
• such monitoring is only possible if the circuit used for monitoring itself still operates reliably at the minimum voltage. At voltages of modern controllers of 1.5 V and below, this requirement is no longer easy to meet.
• Another approach is to store predetermined test patterns in a defined area of the memory and to compare them with the specification from time to time in order to detect a power failure in the event of a deviation from the specification.
• the disadvantage here is that the memory area used for the test pattern is not available for other purposes.
• the invention as defined in claim 1 provides a method for detecting a power interruption which can be executed in a short time, the execution of which does not or at least substantially impairs the processing power of a processor accessing the monitored data memory and which is realized with minimum cost. is lisierbar. To carry out the method, no more circuit components are required, as are also needed anyway for the detection of radiation-induced bit flips. Since the payload units accessing the method are arbitrary, there is no need to read any payload units specifically for the purposes of the method according to the invention, but read operations can be used which are within the scope of carrying out any task different from the method according to the invention were carried out. The method therefore does not delay the processing of such a task.
• the method uses the fact that the radiation-induced bit flips occur at random times and with each other uncorrelated.
• the time span between two consecutive radiation-induced bit flips therefore follows an exponential distribution.
• the probability that one or more further bit flips are detected after the detection of a first bit flip in a given time period or over a given number of consecutive read accesses in this time period can be determined by appropriate selection of the time span or the number of read accesses be made arbitrarily small. If, in the given number of read accesses, a read payload unit is nevertheless found to be corrupted, the likelihood that this is due to ionizing radiation is correspondingly low, and it can be assumed that such an error cluster is not radiation-induced, but goes back to a supply interruption.
• the check information unit used to determine a corruption can be a parity bit assigned to each payload unit.
• the test information unit belonging to a payload unit can be obtained from the payload unit according to an error correction coding method known per se, such as Reed-Solomon or Hamming coding, so that in the case of one it does not serious corruption of the payload unit makes it possible to correct the latter.
• error correction coding method known per se, such as Reed-Solomon or Hamming coding
• payload units which are derived from measured data obtained in an iterative control process, can often be restored with little effort by a recalculation on the basis of current measured data.
• the useful information units restored in the course of the method may also include those to which no check information is assigned.
• Fig. 1 is a block diagram of a system including a controller and a controlled machine to which the method of the invention is applicable;
• the control device shown schematically in FIG. 1 comprises a microprocessor 1, an SRAM 2, a read-only memory or ROM 3 as well as a plurality of sensors and actuators mounted on the controlled machine designated 4 and interconnected via an address bus 5 and a data bus 6 communicate.
• Other components such as a dynamic random access memory may be present, but are in the figure not shown, as they are not essential to the understanding of the invention.
• the SRAM 2 receives an operating voltage from a power source 7 under no-fault conditions even when the microprocessor 1 and the engine 4 are turned off, so that parameter values stored in the SRAM 2 are maintained even when turned off.
• the SRAM 2 is divided into memory cells each of which contains a data word having a width corresponding to the width of the data bus 6 and a parity bit.
• a parity circuit 8 Connected to the data bus 6 is a parity circuit 8 which, upon a write operation to the SRAM 2, generates and outputs to the SRAM 2 a parity bit to the data present on the data bus 6 so that the data is stored therein along with its parity bit.
• the parity circuit 8 receives the parity bit stored there to the read data value and compares this with a parity bit calculated from the data word 6 output on the data bus. If the parity bits match, the data word is accepted as error-free. If the parity bits do not match, the parity circuit 8 outputs a warning signal to the microprocessor 1, in particular to an interrupt input 9 of the microprocessor 1.
• Fig. 2 shows in the form of a flow chart an embodiment of a method which can be carried out by the microprocessor 1 upon the arrival of the warning signal.
• the step of receiving the warning signal is denoted by S1.
• S2 is followed by a step S2, in which it is checked whether a timer is set or not.
• the timer may be a circuit implemented outside the microprocessor 1; but it may also be a register of the microprocessor 1 or an external memory location, which is regarded as set as long as its content is different from and its contents regularly, for example, controlled by a microprocessor 1 also controlling Clock signal, or each time the microprocessor accesses the SRAM 2, is decremented until it reaches 0.
• step S3 the method branches to step S3, in which the memory cell is identified whose error has triggered the warning signal. Based on a given table, it is decided in step S4 which of several possible classes the defective memory cell belongs to.
• the classes reflect the technical meaning of the variables stored in the respective memory cell. For example, one of these classes includes variables that are recalculated during normal, undisturbed operation of the microprocessor 1 in short cycles based on signals from the sensors placed on the machine.
• Another class of variables are maps containing a plurality of parameterized, numerically similar values.
• an error correction may be based on reading values of the characteristic curve for parameter values adjacent to those of the value stored in the defective memory cell in step S7 and a value close to the lost value with high probability by interpolating the same to calculate read values and write to the memory cell that caused the error.
• step S8 method for restoring defective memory contents are collectively referred to as step S8.
• the parity circuit 8 is provided by an error correction coding and decoding circuit is replaced and the SRAM stores for each data word several bits of a suitable correction code
• the recovery of a defective data value can also be done by applying the error correction code.
• step S2 the timer is deemed to have been set if and only if the process of FIG. 2 has already been carried out once not too long ago. If one does not set too long the time period in which the timer remains set, the probability that two consecutive parity errors are radiation-induced can be made arbitrarily small. Therefore, if a parity error is detected when the timer is set, it can be considered that the cause is an interruption of the power supply voltage. In this case, the process goes from step S2 to S9. In this step, the content of SRAM 2 is completely discarded, and at least part of its content is replaced by a set of default values by copying it from ROM 3 to SRAM 2.
• step S10 Other variables which are newly determined in normal operation at high frequency based on detection results of the sensors are also rewritten in step S10 on the basis of current detection results of the sensors.
• steps S9, SlO a complete content of the SRAM 2 having parity error-free values is available which, although not necessarily identical bit-by-bit to the values stored before the occurrence of the error, but which enable an at least usable control of the machine 4.
• the ROM 3 is electrically programmable.
• Such an EEPROM may have much longer write access times than the SRAM 2; however, it should also be less sensitive than this for radiation-induced bit flips.
• a characteristic curve which is stored during operation in the SRAM 2, and where it undergoes an optimization specific to the controlled machine 4 over time, written back to the EEPROM each time the machine 4 is switched off, and copied back into the SRAM 2 when it is switched on again.
• the actuality of the characteristic curve which is copied back into the SRAM 2 after detection of a power failure in step S9, always corresponds to the respectively immediately preceding connection time.
• the characteristic curve can be saved in the EEPROM from time to time when the machine is switched on.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Theoretical Computer Science (AREA)
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• Power Engineering (AREA)
• Quality & Reliability (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Techniques For Improving Reliability Of Storages (AREA)
• For Increasing The Reliability Of Semiconductor Memories (AREA)

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• 2005
  • 2005-12-20 DE DE102005060901A patent/DE102005060901A1/de active Pending
• 2006
  • 2006-12-12 JP JP2008546376A patent/JP4950214B2/ja active Active
  • 2006-12-12 US US12/097,324 patent/US8074120B2/en active Active
  • 2006-12-12 EP EP06819943A patent/EP1966696A1/de not_active Withdrawn
  • 2006-12-12 CN CNA2006800480943A patent/CN101341469A/zh active Pending
  • 2006-12-12 WO PCT/EP2006/069576 patent/WO2007071590A1/de active Application Filing
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