Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
  • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
  • H01L27/0802—Resistors only
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
  • H01L28/20—Resistors

Definitions

• the present invention relates to a resistor and more particularly to a resistor of an integrated circuit.
• resistor commonly used in integrated circuits is a resistor in the form of a strip of polycrystalline silicon or metal (TaN) placed above a silicon wafer and insulated from the latter by an insulating layer.
• TaN polycrystalline silicon or metal
• Another example of known resistance consists of a portion of P or N type doped silicon formed in the upper part of a silicon wafer.
• a disadvantage of these resistances is that the wafer surfaces used can be very large.
• An object of the present invention is to provide a resistance structure occupying a small area of a silicon wafer.
• the present invention further provides a method of manufacturing such a resistance.
• the present invention provides a resistive element comprising two vertical resistive parts. shims placed in two holes formed in the upper part of a substrate and a horizontal resistive part placed in a buried cavity connecting the bottoms of the holes.
• the present invention further provides a resistor comprising several resistive elements such as those described above connected to each other by resistive strips placed on the substrate.
• the substrate is a silicon wafer, said resistive layer being separated from the substrate by an insulating layer such as a layer of silicon oxide.
• the conduit is filled with a filling material such as polycrystalline silicon.
• the resistive layer and the filling material are separated by an insulating layer such as a layer of silicon oxide.
• the resistive layer consists of polycrystalline silicon or of a metal.
• the present invention further provides a method of forming a resistive element in a substrate comprising the following steps: forming, by anisotropic etching, two holes in the upper part of a substrate; forming, by isotropic etching at the bottom of the holes, a cavity connecting the bottom of the two holes, the holes and the cavity constituting a conduit; and carry out a conformal deposition of a resistive layer against the walls of the duct.
• the method comprises, prior to the conformal deposition of the resistive layer, a step of conformally depositing a first insulating layer, and further comprises a deposition step of conforming a second insulating layer covering said resistive layer, as well as a step of filling the conduit with a filling material such as polycrystalline silicon.
• the method further comprising a step of etching the layer resistive on the surface of the substrate to form resistive strips.
• FIGS. 1A, 2, 3, 4A and 5 are sectional views and FIGS. 1B and 4B are views from above of structures obtained during successive stages of a method of forming a resistance according to the present invention
• Figure 6 is a sectional view of another example of resistance obtained according to a variant of the method described in connection with Figures 1 to 5;
• Figure 7 is a top view of an example of resistance according to the present invention.
• a resistor according to the present invention can be qualified as a three-dimensional resistor, "3D".
• the resistor consists of a set of elementary resistive elements formed in the upper part of a substrate, such as a silicon wafer.
• a resistive element comprises two "vertical” resistive parts, placed in two holes formed in the upper part of the substrate and a small “horizontal” resistive part placed in a buried cavity connecting the bottoms of the two holes.
• an anisotropic etching of a substrate 1 is carried out to form pairs of holes 2a / 2b and 3a / 3b in the upper part of the substrate 1.
• the substrate 1 is for example a silicon wafer.
• the etching can be carried out according to a “deep” plasma etching process, better known under the English name Deep Reactive Ion Etching (DRIE).
• DRIE Deep Reactive Ion Etching
• the substrate 1 is polarized so that the attack of the substrate by ionized gas molecules takes place "vertically".
• the gas mixture used may comprise a "passivating" gas which reacts with the substrate to form a thin insulating layer.
• etching gas such as SFg
• passivating gas such as C4F8
• a thin insulating layer forms on the walls of the holes as they are formed.
• Isotropic etching of the substrate 1 is then carried out, at the bottom of the holes 2a / 2b and 3a / 3b, to form "buried" cavities at the bottom of each of the holes.
• the two holes of each pair are placed close enough so that the buried cavities formed at the bottom of each of the holes meet to form a single buried cavity.
• the holes 2a and 2b are connected by a buried cavity 5 and the holes 3a and 3b are connected by a buried cavity 6.
• This isotropic etching can be carried out according to a plasma etching process substantially identical to that used to form the holes, except that the substrate 1 is no longer polarized and that the amount of passivating gas is possibly less.
• 3a and 3b in this example have a substantially cylindrical shape.
• the holes 2a, 2b and the buried cavity 5 constitute a conduit 10.
• the holes 3a, 3b and the buried cavity 6 constitute a conduit 11.
• the insulating layers 20 and 22 can be obtained by a conventional thermal oxidation process or by a low pressure chemical vapor deposition process, better known by the acronym LPCVD.
• the insulating layers 20 and 22 are for example made of silicon oxide.
• the resistive layer 21 may consist of polycrystalline silicon, doped or undoped, or of a metal such as tantalum nitride.
• Such resistive layers can be deposited according to an LPCVD process or according to a chemical vapor deposition process by atomic layers, better known by the English acronym of ALCVD.
• the conduits 10 and 11 are filled with a filling material 30 such as polycrystalline silicon.
• the filling material 30 also covers the surface of the substrate 1.
• each strip A, B and C consists of a stack of a portion A21, B21, C21 of the resistive layer 21, of a portion A22, B22, C22 of the insulating layer 22 and of a portion A30, B30 , C30 of the filling material 30.
• the ends of the central strip B cover the holes 2b and 3a of the conduits 10 and 11.
• One end of the external strip A covers the hole 2a of the duct 10 and one end of the external strip B covers the hole 3b of the conduit 11.
• the strips A, B and C are in this example aligned in top view.
• a partial etching of the outer bands A and C is carried out on the side opposite the holes 2a and 3b.
• An etching of the filling material 30 and of the insulating layer 21 is carried out successively in order to allow access to the ends of the resistive portions A21 and C21 of the strips A and C.
• the resistance shown in FIG. 5 comprises two resistive elements R1 and R2 formed respectively in the conduits 10 and 11.
• the substantially cylindrical portions of the resistive layer 21 placed in the holes 2a / 2b and 3a / 3b constitute vertical resistive parts Rla / Rlb and R2a / R2b.
• the oblong portions of the resistive layer 21 placed in the buried cavities 5 and 6 constitute "horizontal" resistive parts RIc and R2c.
• the insulating layer 20 is not necessary.
• FIG. 6 illustrates a resistance obtained according to an alternative embodiment of the method described above and more particularly according to an alternative embodiment of the initial etching steps used to form the conduits 10 and 11.
• the substrate used is a wafer SOI type, from the English word Silicon On Insulator, comprising a thick layer of silicon 50 covered with a thin insulating layer 51 itself covered with a layer of silicon 52.
• the formation of the conduits consists, in this embodiment , to etch holes over the entire thickness of the silicon layer 52 according to an anisotropic etching process and then to extend this etching, once the holes are formed, to form buried connecting cavities between the bottom of the holes.
• the etching of buried cavities is carried out by promoting a normally parasitic phenomenon of lateral etching by "ricochet" on the thin insulating layer 51, this phenomenon being known by the English term "notching".
• Figure 7 is a top view of an example of resistance according to the present invention comprising a set of resistive elements formed in the upper part of a substrate, such as those described above.
• the resistive elements are connected to each other by conductive strips placed on the substrate.
• the conductive strips are shown in solid lines, the hole entries are represented by dotted circles placed under the ends of the conductive strips and the buried cavities are represented by dotted ovals surrounding two hole entries.
• the resistive elements are arranged in rows L1 to L6 which comprise 5 resistive elements each, the row L1 being shown at the bottom of the figure.
• the resistive elements of the same row are aligned, that is to say that the entries of the holes and the buried cavities in which the resistive elements are formed, are aligned with respect to each other.
• the conductive strips connecting together resistive elements of the same row are aligned and have a substantially rectangular shape.
• the elements of a row are connected to those of a neighboring row by a resistive connecting strip, U-shaped in this example.
• Three resistive connecting strips connect rows L1 / L2, L3 / L4 and L5 / L6 on the left of the latter and two resistive connecting bands connect the rows L2 / L3 and L4 / L5 on the right of the latter.
• the resistance thus has a top view in the form of a coil.
• the straight ends of the rightmost resistive strips of the rows L1 and L6 are the ends of the coil and constitute contact pads P1 and P2 of the resistor.
• the resistance shown in Figure 7 consists of resistive elements each having the following characteristics:
• the surface occupied by a resistance according to the present invention is much smaller, 5 to 10 times smaller, than that occupied by a conventional resistance formed on the surface of a wafer. silicon.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Semiconductor Integrated Circuits (AREA)
• Non-Adjustable Resistors (AREA)

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• 2006
  • 2006-12-05 CN CN200680046209.5A patent/CN101326639B/zh not_active Expired - Fee Related
  • 2006-12-05 EP EP06842091A patent/EP1958258A1/de not_active Withdrawn
  • 2006-12-05 US US12/096,272 patent/US7902605B2/en not_active Expired - Fee Related
  • 2006-12-05 WO PCT/FR2006/051280 patent/WO2007066037A1/fr active Application Filing
• 2011
  • 2011-01-14 US US13/007,044 patent/US8232169B2/en active Active

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