EP1958258A1 - Resistance in an integrated circuit - Google Patents

Resistance in an integrated circuit

Info

Publication number
EP1958258A1
EP1958258A1 EP06842091A EP06842091A EP1958258A1 EP 1958258 A1 EP1958258 A1 EP 1958258A1 EP 06842091 A EP06842091 A EP 06842091A EP 06842091 A EP06842091 A EP 06842091A EP 1958258 A1 EP1958258 A1 EP 1958258A1
Authority
EP
European Patent Office
Prior art keywords
resistive
holes
layer
substrate
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06842091A
Other languages
German (de)
French (fr)
Inventor
Christine Anceau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of EP1958258A1 publication Critical patent/EP1958258A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802—Resistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors

Definitions

  • the present invention relates to a resistor and more particularly to a resistor of an integrated circuit.
  • resistor commonly used in integrated circuits is a resistor in the form of a strip of polycrystalline silicon or metal (TaN) placed above a silicon wafer and insulated from the latter by an insulating layer.
  • TaN polycrystalline silicon or metal
  • Another example of known resistance consists of a portion of P or N type doped silicon formed in the upper part of a silicon wafer.
  • a disadvantage of these resistances is that the wafer surfaces used can be very large.
  • An object of the present invention is to provide a resistance structure occupying a small area of a silicon wafer.
  • the present invention further provides a method of manufacturing such a resistance.
  • the present invention provides a resistive element comprising two vertical resistive parts. shims placed in two holes formed in the upper part of a substrate and a horizontal resistive part placed in a buried cavity connecting the bottoms of the holes.
  • the present invention further provides a resistor comprising several resistive elements such as those described above connected to each other by resistive strips placed on the substrate.
  • the substrate is a silicon wafer, said resistive layer being separated from the substrate by an insulating layer such as a layer of silicon oxide.
  • the conduit is filled with a filling material such as polycrystalline silicon.
  • the resistive layer and the filling material are separated by an insulating layer such as a layer of silicon oxide.
  • the resistive layer consists of polycrystalline silicon or of a metal.
  • the present invention further provides a method of forming a resistive element in a substrate comprising the following steps: forming, by anisotropic etching, two holes in the upper part of a substrate; forming, by isotropic etching at the bottom of the holes, a cavity connecting the bottom of the two holes, the holes and the cavity constituting a conduit; and carry out a conformal deposition of a resistive layer against the walls of the duct.
  • the method comprises, prior to the conformal deposition of the resistive layer, a step of conformally depositing a first insulating layer, and further comprises a deposition step of conforming a second insulating layer covering said resistive layer, as well as a step of filling the conduit with a filling material such as polycrystalline silicon.
  • the method further comprising a step of etching the layer resistive on the surface of the substrate to form resistive strips.
  • FIGS. 1A, 2, 3, 4A and 5 are sectional views and FIGS. 1B and 4B are views from above of structures obtained during successive stages of a method of forming a resistance according to the present invention
  • Figure 6 is a sectional view of another example of resistance obtained according to a variant of the method described in connection with Figures 1 to 5;
  • Figure 7 is a top view of an example of resistance according to the present invention.
  • a resistor according to the present invention can be qualified as a three-dimensional resistor, "3D".
  • the resistor consists of a set of elementary resistive elements formed in the upper part of a substrate, such as a silicon wafer.
  • a resistive element comprises two "vertical” resistive parts, placed in two holes formed in the upper part of the substrate and a small “horizontal” resistive part placed in a buried cavity connecting the bottoms of the two holes.
  • an anisotropic etching of a substrate 1 is carried out to form pairs of holes 2a / 2b and 3a / 3b in the upper part of the substrate 1.
  • the substrate 1 is for example a silicon wafer.
  • the etching can be carried out according to a “deep” plasma etching process, better known under the English name Deep Reactive Ion Etching (DRIE).
  • DRIE Deep Reactive Ion Etching
  • the substrate 1 is polarized so that the attack of the substrate by ionized gas molecules takes place "vertically".
  • the gas mixture used may comprise a "passivating" gas which reacts with the substrate to form a thin insulating layer.
  • etching gas such as SFg
  • passivating gas such as C4F8
  • a thin insulating layer forms on the walls of the holes as they are formed.
  • Isotropic etching of the substrate 1 is then carried out, at the bottom of the holes 2a / 2b and 3a / 3b, to form "buried" cavities at the bottom of each of the holes.
  • the two holes of each pair are placed close enough so that the buried cavities formed at the bottom of each of the holes meet to form a single buried cavity.
  • the holes 2a and 2b are connected by a buried cavity 5 and the holes 3a and 3b are connected by a buried cavity 6.
  • This isotropic etching can be carried out according to a plasma etching process substantially identical to that used to form the holes, except that the substrate 1 is no longer polarized and that the amount of passivating gas is possibly less.
  • 3a and 3b in this example have a substantially cylindrical shape.
  • the holes 2a, 2b and the buried cavity 5 constitute a conduit 10.
  • the holes 3a, 3b and the buried cavity 6 constitute a conduit 11.
  • the insulating layers 20 and 22 can be obtained by a conventional thermal oxidation process or by a low pressure chemical vapor deposition process, better known by the acronym LPCVD.
  • the insulating layers 20 and 22 are for example made of silicon oxide.
  • the resistive layer 21 may consist of polycrystalline silicon, doped or undoped, or of a metal such as tantalum nitride.
  • Such resistive layers can be deposited according to an LPCVD process or according to a chemical vapor deposition process by atomic layers, better known by the English acronym of ALCVD.
  • the conduits 10 and 11 are filled with a filling material 30 such as polycrystalline silicon.
  • the filling material 30 also covers the surface of the substrate 1.
  • each strip A, B and C consists of a stack of a portion A21, B21, C21 of the resistive layer 21, of a portion A22, B22, C22 of the insulating layer 22 and of a portion A30, B30 , C30 of the filling material 30.
  • the ends of the central strip B cover the holes 2b and 3a of the conduits 10 and 11.
  • One end of the external strip A covers the hole 2a of the duct 10 and one end of the external strip B covers the hole 3b of the conduit 11.
  • the strips A, B and C are in this example aligned in top view.
  • a partial etching of the outer bands A and C is carried out on the side opposite the holes 2a and 3b.
  • An etching of the filling material 30 and of the insulating layer 21 is carried out successively in order to allow access to the ends of the resistive portions A21 and C21 of the strips A and C.
  • the resistance shown in FIG. 5 comprises two resistive elements R1 and R2 formed respectively in the conduits 10 and 11.
  • the substantially cylindrical portions of the resistive layer 21 placed in the holes 2a / 2b and 3a / 3b constitute vertical resistive parts Rla / Rlb and R2a / R2b.
  • the oblong portions of the resistive layer 21 placed in the buried cavities 5 and 6 constitute "horizontal" resistive parts RIc and R2c.
  • the insulating layer 20 is not necessary.
  • FIG. 6 illustrates a resistance obtained according to an alternative embodiment of the method described above and more particularly according to an alternative embodiment of the initial etching steps used to form the conduits 10 and 11.
  • the substrate used is a wafer SOI type, from the English word Silicon On Insulator, comprising a thick layer of silicon 50 covered with a thin insulating layer 51 itself covered with a layer of silicon 52.
  • the formation of the conduits consists, in this embodiment , to etch holes over the entire thickness of the silicon layer 52 according to an anisotropic etching process and then to extend this etching, once the holes are formed, to form buried connecting cavities between the bottom of the holes.
  • the etching of buried cavities is carried out by promoting a normally parasitic phenomenon of lateral etching by "ricochet" on the thin insulating layer 51, this phenomenon being known by the English term "notching".
  • Figure 7 is a top view of an example of resistance according to the present invention comprising a set of resistive elements formed in the upper part of a substrate, such as those described above.
  • the resistive elements are connected to each other by conductive strips placed on the substrate.
  • the conductive strips are shown in solid lines, the hole entries are represented by dotted circles placed under the ends of the conductive strips and the buried cavities are represented by dotted ovals surrounding two hole entries.
  • the resistive elements are arranged in rows L1 to L6 which comprise 5 resistive elements each, the row L1 being shown at the bottom of the figure.
  • the resistive elements of the same row are aligned, that is to say that the entries of the holes and the buried cavities in which the resistive elements are formed, are aligned with respect to each other.
  • the conductive strips connecting together resistive elements of the same row are aligned and have a substantially rectangular shape.
  • the elements of a row are connected to those of a neighboring row by a resistive connecting strip, U-shaped in this example.
  • Three resistive connecting strips connect rows L1 / L2, L3 / L4 and L5 / L6 on the left of the latter and two resistive connecting bands connect the rows L2 / L3 and L4 / L5 on the right of the latter.
  • the resistance thus has a top view in the form of a coil.
  • the straight ends of the rightmost resistive strips of the rows L1 and L6 are the ends of the coil and constitute contact pads P1 and P2 of the resistor.
  • the resistance shown in Figure 7 consists of resistive elements each having the following characteristics:
  • the surface occupied by a resistance according to the present invention is much smaller, 5 to 10 times smaller, than that occupied by a conventional resistance formed on the surface of a wafer. silicon.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Non-Adjustable Resistors (AREA)

Abstract

The invention relates to a resistive element comprising two vertical resistive parts (R1a, R1b) placed in two holes formed in the upper part of a substrate (1) and a horizontal resistive part (RIc) formed in a buried cavity connecting the bottoms of the holes.

Description

RESISTANCE DANS UN CIRCUIT INTEGRE  RESISTANCE IN AN INTEGRATED CIRCUIT
Domaine de l' invention Field of the invention
La présente invention concerne une résistance et plus particulièrement une résistance d'un circuit intégré.  The present invention relates to a resistor and more particularly to a resistor of an integrated circuit.
Exposé de l'art antérieur Presentation of the prior art
Un exemple de résistance couramment utilisée dans les circuits intégrés est une résistance ayant la forme d'une bande de silicium polycristallin ou de métal (TaN) placée au-dessus d'une plaquette de silicium et isolée de cette dernière par une couche isolante.  An example of a resistor commonly used in integrated circuits is a resistor in the form of a strip of polycrystalline silicon or metal (TaN) placed above a silicon wafer and insulated from the latter by an insulating layer.
Un autre exemple de résistance connue est constitué d'une portion de silicium dopée de type P ou N formée dans la partie supérieure d'une plaquette de silicium.  Another example of known resistance consists of a portion of P or N type doped silicon formed in the upper part of a silicon wafer.
Un inconvénient de ces résistances est que les surfaces de plaquette utilisées peuvent être très importantes.  A disadvantage of these resistances is that the wafer surfaces used can be very large.
Résumé de l'invention Summary of the invention
Un objet de la présente invention est de prévoir une structure de résistance occupant une faible surface d'une plaquette de silicium.  An object of the present invention is to provide a resistance structure occupying a small area of a silicon wafer.
La présente invention prévoit en outre un procédé de fabrication d'une telle résistance.  The present invention further provides a method of manufacturing such a resistance.
Pour atteindre ces objets, la présente invention prévoit un élément résistif comprenant deux parties résistives verti- cales placées dans deux trous formés dans la partie supérieure d'un substrat et une partie résistive horizontale placée dans une cavité enterrée reliant les fonds des trous . To achieve these objects, the present invention provides a resistive element comprising two vertical resistive parts. shims placed in two holes formed in the upper part of a substrate and a horizontal resistive part placed in a buried cavity connecting the bottoms of the holes.
La présente invention prévoit en outre une résistance comprenant plusieurs éléments résistifs tels que ceux décrits ci-dessus reliés les uns aux autres par des bandes résistives placées sur le substrat .  The present invention further provides a resistor comprising several resistive elements such as those described above connected to each other by resistive strips placed on the substrate.
Selon un mode de réalisation d'un élément résistif tel que celui décrit ci-dessus, les deux trous reliés par la cavité enterrée constituent un conduit, les parties résistives verti¬ cales et horizontale étant formées par une couche résistive isolée recouvrant les parois du conduit . According to an embodiment of a resistive element such as that described above, the two holes connected by the buried cavity constituting a conduit, the resistive portions verti ¬ wedges and horizontal being formed by an insulated resistive layer overlying the channel walls .
Selon un mode de réalisation d'un élément résistif tel que celui susmentionné, le substrat est une plaquette de sili- cium, ladite couche résistive étant séparée du substrat par une couche isolante telle qu'une couche d'oxyde de silicium.  According to an embodiment of a resistive element such as that mentioned above, the substrate is a silicon wafer, said resistive layer being separated from the substrate by an insulating layer such as a layer of silicon oxide.
Selon un mode de réalisation d'un élément résistif tel que celui susmentionné, le conduit est rempli d'un matériau de remplissage tel que du silicium polycristallin.  According to an embodiment of a resistive element such as that mentioned above, the conduit is filled with a filling material such as polycrystalline silicon.
Selon un mode de réalisation d'un élément résistif tel que celui susmentionné, la couche résistive et le matériau de remplissage sont séparés par une couche isolante telle qu'une couche d'oxyde de silicium.  According to an embodiment of a resistive element such as that mentioned above, the resistive layer and the filling material are separated by an insulating layer such as a layer of silicon oxide.
Selon un mode de réalisation d'un élément résistif tel que celui décrit ci-dessus, la couche résistive est constituée de silicium polycristallin ou d'un métal.  According to an embodiment of a resistive element such as that described above, the resistive layer consists of polycrystalline silicon or of a metal.
La présente invention prévoit en outre un procédé de formation d'un élément résistif dans un substrat comprenant les étapes suivantes : former, par gravure anisotrope, deux trous dans la partie supérieure d'un substrat ; former, par gravure isotrope au fond des trous, une cavité reliant le fond des deux trous, les trous et la cavité constituant un conduit ; et effectuer un dépôt conforme d'une couche résistive contre les parois du conduit . Selon un mode de mise en oeuvre du procédé susmen¬ tionné, le procédé comprend, préalablement au dépôt conforme de la couche résistive, une étape de dépôt conforme d'une première couche isolante, et comprend en outre une étape de dépôt conforme d'une seconde couche isolante recouvrant ladite couche résistive, ainsi qu'une étape de remplissage du conduit avec un matériau de remplissage tel que du silicium polycristallin. The present invention further provides a method of forming a resistive element in a substrate comprising the following steps: forming, by anisotropic etching, two holes in the upper part of a substrate; forming, by isotropic etching at the bottom of the holes, a cavity connecting the bottom of the two holes, the holes and the cavity constituting a conduit; and carry out a conformal deposition of a resistive layer against the walls of the duct. According to an embodiment of the method above- ¬ tioned, the method comprises, prior to the conformal deposition of the resistive layer, a step of conformally depositing a first insulating layer, and further comprises a deposition step of conforming a second insulating layer covering said resistive layer, as well as a step of filling the conduit with a filling material such as polycrystalline silicon.
Selon un mode de mise en oeuvre du procédé susmen¬ tionné, lors de la formation de la couche résistive contre les parois du conduit, il se forme une couche résistive en surface du substrat, le procédé comprenant en outre une étape de gravure de la couche résistive en surface du substrat pour former des bandes résistives . According to an embodiment of the method above- ¬ tioned, during the formation of the resistive layer against the channel walls, forms a resistive layer on the surface of the substrate, the method further comprising a step of etching the layer resistive on the surface of the substrate to form resistive strips.
Brève description des dessins Brief description of the drawings
Ces objets, caractéristiques et avantages, ainsi que d' autres de la présente invention seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi lesquelles :  These objects, characteristics and advantages, as well as others of the present invention will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which:
les figures IA, 2, 3, 4A et 5 sont des vues en coupe et les figures IB et 4B des vues de dessus de structures obtenues lors d'étapes successives d'un procédé de formation d'une résistance selon la présente invention ;  FIGS. 1A, 2, 3, 4A and 5 are sectional views and FIGS. 1B and 4B are views from above of structures obtained during successive stages of a method of forming a resistance according to the present invention;
la figure 6 est une vue en coupe d'un autre exemple de résistance obtenue selon une variante du procédé décrit en relation avec les figures 1 à 5 ; et  Figure 6 is a sectional view of another example of resistance obtained according to a variant of the method described in connection with Figures 1 to 5; and
la figure 7 est une vue de dessus d'un exemple de résistance selon la présente invention.  Figure 7 is a top view of an example of resistance according to the present invention.
Description détaillée detailed description
Par souci de clarté, de mêmes éléments ont été dési¬ gnés par de mêmes références aux différentes figures et, de plus, comme cela est habituel dans la représentation des composants semiconducteurs, les diverses figures ne sont pas tracées à l'échelle. Une résistance selon la présente invention peut être qualifiée de résistance en trois dimensions, "3D". La résistance est constituée d'un ensemble d'éléments résistifs élémentaires formés dans la partie supérieure d'un substrat, tel qu'une plaquette de silicium. Un élément résistif comprend deux parties résistives "verticales", placées dans deux trous formés dans la partie supérieure du substrat et une petite partie résistive "horizontale" placée dans une cavité enterrée reliant les fonds des deux trous . For clarity, the same elements have been desig ¬ nated with same references in the different drawings and, further, as usual in the representation of semiconductor components, the various drawings are not drawn to scale. A resistor according to the present invention can be qualified as a three-dimensional resistor, "3D". The resistor consists of a set of elementary resistive elements formed in the upper part of a substrate, such as a silicon wafer. A resistive element comprises two "vertical" resistive parts, placed in two holes formed in the upper part of the substrate and a small "horizontal" resistive part placed in a buried cavity connecting the bottoms of the two holes.
Un procédé de réalisation d'une telle résistance est décrit ci-après en relation avec les figures 1 à 6.  A method of producing such a resistance is described below in relation to FIGS. 1 to 6.
Dans une étape initiale, illustrée en figures IA et IB, on effectue une gravure anisotrope d'un substrat 1 pour former des paires de trous 2a/2b et 3a/3b dans la partie supérieure du substrat 1. Le substrat 1 est par exemple une plaquette de silicium. La gravure peut être réalisée selon un procédé de gravure plasma "profond", plus connu sous le nom anglais Deep Reactive Ion Etching (DRIE) . Le substrat 1 est polarisé de façon que l'attaque du substrat par des molécules gazeuses ionisées se fasse "verticalement". Le mélange gazeux utilisé peut comprendre un gaz "passivant" qui réagit avec le substrat pour former une fine couche isolante. On utilise par exemple un mélange d'un gaz "gravant" tel que SFg et d'un gaz passivant tel que C4F8. Lorsqu'on utilise un mélange gazeux comprenant un gaz passivant, il se forme une fine couche isolante sur les parois des trous au fur et à mesure de leur formation.  In an initial step, illustrated in FIGS. 1A and 1B, an anisotropic etching of a substrate 1 is carried out to form pairs of holes 2a / 2b and 3a / 3b in the upper part of the substrate 1. The substrate 1 is for example a silicon wafer. The etching can be carried out according to a “deep” plasma etching process, better known under the English name Deep Reactive Ion Etching (DRIE). The substrate 1 is polarized so that the attack of the substrate by ionized gas molecules takes place "vertically". The gas mixture used may comprise a "passivating" gas which reacts with the substrate to form a thin insulating layer. For example, a mixture of an "etching" gas such as SFg and a passivating gas such as C4F8 is used. When a gas mixture comprising a passivating gas is used, a thin insulating layer forms on the walls of the holes as they are formed.
On effectue ensuite une gravure isotrope du substrat 1, au fond des trous 2a/2b et 3a/3b, pour former des cavités "enterrées" au fond de chacun des trous. Les deux trous de chaque paire sont placés suffisamment proches de façon que les cavités enterrées formées au fond de chacun des trous se rejoignent pour former une unique cavité enterrée. Ainsi, les trous 2a et 2b sont reliés par une cavité enterrée 5 et les trous 3a et 3b sont reliés par une cavité enterrée 6. Cette gravure isotrope peut être réalisée selon un procédé de gravure plasma sensiblement identique à celui utilisé pour former les trous, excepté que le substrat 1 n'est plus polarisé et que la quantité de gaz passivant est éventuellement moindre. Isotropic etching of the substrate 1 is then carried out, at the bottom of the holes 2a / 2b and 3a / 3b, to form "buried" cavities at the bottom of each of the holes. The two holes of each pair are placed close enough so that the buried cavities formed at the bottom of each of the holes meet to form a single buried cavity. Thus, the holes 2a and 2b are connected by a buried cavity 5 and the holes 3a and 3b are connected by a buried cavity 6. This isotropic etching can be carried out according to a plasma etching process substantially identical to that used to form the holes, except that the substrate 1 is no longer polarized and that the amount of passivating gas is possibly less.
Comme cela est visible en figure IB, les trous 2a, 2b, As can be seen in FIG. 1B, the holes 2a, 2b,
3a et 3b ont dans cet exemple une forme sensiblement cylindrique. Les cavités enterrées 5 et 6, ayant une forme sensiblement ovale en vue de dessus, sont représentées en pointillés autour des paires de trous 2a/2b et 3a/3b. 3a and 3b in this example have a substantially cylindrical shape. The buried cavities 5 and 6, having a substantially oval shape when viewed from above, are shown in dotted lines around the pairs of holes 2a / 2b and 3a / 3b.
On considère par la suite que les trous 2a, 2b et la cavité enterrée 5 constituent un conduit 10. De même, les trous 3a, 3b et la cavité enterrée 6 constituent un conduit 11.  It is subsequently considered that the holes 2a, 2b and the buried cavity 5 constitute a conduit 10. Similarly, the holes 3a, 3b and the buried cavity 6 constitute a conduit 11.
A l'étape suivante, illustrée en figure 2, on effectue successivement plusieurs dépôts conformes d'une fine couche isolante 20, d'une couche résistive 21 puis d'une couche isolante 22 sur la structure précédemment obtenue. Ces trois fines couches superposées recouvrent les parois des conduits 10 et 11 ainsi que la surface supérieure du substrat 1.  In the next step, illustrated in FIG. 2, several conformal deposits are made successively with a thin insulating layer 20, a resistive layer 21 and then an insulating layer 22 on the structure previously obtained. These three thin superimposed layers cover the walls of the conduits 10 and 11 as well as the upper surface of the substrate 1.
Les couches isolantes 20 et 22 peuvent être obtenues par un procédé classique d'oxydation thermique ou par un procédé de dépôt chimique en phase vapeur à basse pression, plus connu par l'acronyme anglais de LPCVD. Les couches isolantes 20 et 22 sont par exemple constituées d'oxyde de silicium.  The insulating layers 20 and 22 can be obtained by a conventional thermal oxidation process or by a low pressure chemical vapor deposition process, better known by the acronym LPCVD. The insulating layers 20 and 22 are for example made of silicon oxide.
La couche résistive 21 peut être constituée de silicium polycristallin, dopée ou non dopée, ou d'un métal tel que du nitrure de tantale. De telles couches résistives peuvent être déposées selon un procédé LPCVD ou selon un procédé de dépôt chimique en phase vapeur par couches atomiques, plus connu par l ' acronyme anglais de ALCVD .  The resistive layer 21 may consist of polycrystalline silicon, doped or undoped, or of a metal such as tantalum nitride. Such resistive layers can be deposited according to an LPCVD process or according to a chemical vapor deposition process by atomic layers, better known by the English acronym of ALCVD.
A l'étape suivante, illustrée en figure 3, on remplit les conduits 10 et 11 avec un matériau de remplissage 30 tel que du silicium polycristallin. Dans cet exemple, le matériau de remplissage 30 recouvre également la surface du substrat 1.  In the next step, illustrated in FIG. 3, the conduits 10 and 11 are filled with a filling material 30 such as polycrystalline silicon. In this example, the filling material 30 also covers the surface of the substrate 1.
A l'étape suivante, illustrée en figures 4A et 4B, on effectue successivement une gravure du matériau de remplissage 30, de la couche isolante 22 et de la couche résistive 21 de façon à découvrir la surface de la couche isolante 20, tout en conservant des bandes A, B et C de ces divers matériaux. Les bandes sont ainsi isolées électriquement les unes des autres . Chaque bande A, B et C est constituée d'un empilement d'une portion A21, B21, C21 de la couche résistive 21, d'une portion A22, B22, C22 de la couche isolante 22 et d'une portion A30, B30, C30 du matériau de remplissage 30. Les extrémités de la bande centrale B recouvrent les trous 2b et 3a des conduits 10 et 11. Une extrémité de la bande extérieure A recouvre le trou 2a du conduit 10 et une extrémité de la bande extérieure B recouvre le trou 3b du conduit 11. Les bandes A, B et C sont dans cet exemple alignées en vue de dessus. In the next step, illustrated in FIGS. 4A and 4B, an etching of the filling material is carried out successively 30, the insulating layer 22 and the resistive layer 21 so as to uncover the surface of the insulating layer 20, while retaining strips A, B and C of these various materials. The strips are thus electrically isolated from each other. Each strip A, B and C consists of a stack of a portion A21, B21, C21 of the resistive layer 21, of a portion A22, B22, C22 of the insulating layer 22 and of a portion A30, B30 , C30 of the filling material 30. The ends of the central strip B cover the holes 2b and 3a of the conduits 10 and 11. One end of the external strip A covers the hole 2a of the duct 10 and one end of the external strip B covers the hole 3b of the conduit 11. The strips A, B and C are in this example aligned in top view.
A l'étape suivante, illustrée en figure 5, on effectue une gravure partielle des bandes extérieures A et C du côté opposé aux trous 2a et 3b. On effectue successivement une gravure du matériau de remplissage 30 et de la couche isolante 21 afin de permettre un accès aux extrémités des portions résistives A21 et C21 des bandes A et C.  In the next step, illustrated in FIG. 5, a partial etching of the outer bands A and C is carried out on the side opposite the holes 2a and 3b. An etching of the filling material 30 and of the insulating layer 21 is carried out successively in order to allow access to the ends of the resistive portions A21 and C21 of the strips A and C.
La résistance représentée en figure 5 comprend deux éléments résistifs Rl et R2 formés respectivement dans les conduits 10 et 11. Les portions sensiblement cylindriques de la couche résistive 21 placées dans les trous 2a/2b et 3a/3b constituent des parties résistives verticales Rla/Rlb et R2a/R2b. Les portions oblongues de la couche résistive 21 placées dans les cavités enterrées 5 et 6 constituent des parties résistives "horizontales" RIc et R2c.  The resistance shown in FIG. 5 comprises two resistive elements R1 and R2 formed respectively in the conduits 10 and 11. The substantially cylindrical portions of the resistive layer 21 placed in the holes 2a / 2b and 3a / 3b constitute vertical resistive parts Rla / Rlb and R2a / R2b. The oblong portions of the resistive layer 21 placed in the buried cavities 5 and 6 constitute "horizontal" resistive parts RIc and R2c.
On notera que dans le cas où le substrat 1 est constitué d'un matériau isolant tel que du verre, la couche isolante 20 n'est pas nécessaire.  Note that in the case where the substrate 1 is made of an insulating material such as glass, the insulating layer 20 is not necessary.
La figure 6 illustre une résistance obtenue selon une variante de réalisation du procédé précédemment décrit et plus particulièrement selon une variante de réalisation des étapes initiales de gravure mises en oeuvre pour former les conduits 10 et 11. Dans cet exemple, le substrat utilisé est une plaquette de type SOI, de l'anglais Silicon On Insulator, comprenant une couche épaisse de silicium 50 recouverte d'une fine couche isolante 51 elle-même recouverte d'une couche de silicium 52. La formation des conduits consiste, dans ce mode de réalisation, à graver des trous sur toute l'épaisseur de la couche de silicium 52 selon un procédé de gravure anisotrope puis à prolonger cette même gravure, une fois les trous formés, pour former des cavités enterrées de liaison entre le fond des trous . La gravure des cavités enterrées s'effectue en favorisant un phénomène, normalement parasite, de gravure latérale par "ricochet" sur la fine couche isolante 51, ce phénomène étant connu sous le terme anglais de "notching" . FIG. 6 illustrates a resistance obtained according to an alternative embodiment of the method described above and more particularly according to an alternative embodiment of the initial etching steps used to form the conduits 10 and 11. In this example, the substrate used is a wafer SOI type, from the English word Silicon On Insulator, comprising a thick layer of silicon 50 covered with a thin insulating layer 51 itself covered with a layer of silicon 52. The formation of the conduits consists, in this embodiment , to etch holes over the entire thickness of the silicon layer 52 according to an anisotropic etching process and then to extend this etching, once the holes are formed, to form buried connecting cavities between the bottom of the holes. The etching of buried cavities is carried out by promoting a normally parasitic phenomenon of lateral etching by "ricochet" on the thin insulating layer 51, this phenomenon being known by the English term "notching".
La figure 7 est une vue de dessus d'un exemple de résistance selon la présente invention comprenant un ensemble d'éléments résistifs formés dans la partie supérieure d'un substrat, tels que ceux décrits précédemment. Les éléments résistifs sont reliés les uns aux autres par des bandes conductrices placés sur le substrat. Les bandes conductrices, sont représentées en traits pleins, les entrées de trous sont représentées par des ronds en pointillés placés sous les extrémités des bandes conductrices et les cavités enterrées sont représentées par des ovales en pointillés entourant deux entrées de trous.  Figure 7 is a top view of an example of resistance according to the present invention comprising a set of resistive elements formed in the upper part of a substrate, such as those described above. The resistive elements are connected to each other by conductive strips placed on the substrate. The conductive strips are shown in solid lines, the hole entries are represented by dotted circles placed under the ends of the conductive strips and the buried cavities are represented by dotted ovals surrounding two hole entries.
Les éléments résistifs sont agencés en rangées Ll à L6 qui comprennent 5 éléments résistifs chacune, la rangée Ll étant représentée sur le bas de la figure. Les éléments résistifs d'une même rangée sont alignés, c'est-à-dire que les entrées des trous et les cavités enterrées dans lesquelles sont formés les éléments résistifs, sont alignées les unes par rapport aux autres. De même, les bandes conductrices reliant entre eux des éléments résistifs d'une même rangée sont alignées et ont une forme sensiblement rectangulaire. Les éléments d'une rangée sont reliés à ceux d'une rangée voisine par une bande résistive de liaison, en forme de U dans cet exemple. Trois bandes résistives de liaison relient les rangées L1/L2, L3/L4 et L5/L6 sur la gauche de ces dernières et deux bandes résistives de liaison relient les rangées L2/L3 et L4/L5 sur la droite de ces dernières. La résistance a ainsi en vue de dessus la forme d'un serpentin. Les extrémités droites des bandes résistives les plus à droite des rangées Ll et L6 sont les extrémités du serpentin et constituent des plots de contact Pl et P2 de la résistance. The resistive elements are arranged in rows L1 to L6 which comprise 5 resistive elements each, the row L1 being shown at the bottom of the figure. The resistive elements of the same row are aligned, that is to say that the entries of the holes and the buried cavities in which the resistive elements are formed, are aligned with respect to each other. Similarly, the conductive strips connecting together resistive elements of the same row are aligned and have a substantially rectangular shape. The elements of a row are connected to those of a neighboring row by a resistive connecting strip, U-shaped in this example. Three resistive connecting strips connect rows L1 / L2, L3 / L4 and L5 / L6 on the left of the latter and two resistive connecting bands connect the rows L2 / L3 and L4 / L5 on the right of the latter. The resistance thus has a top view in the form of a coil. The straight ends of the rightmost resistive strips of the rows L1 and L6 are the ends of the coil and constitute contact pads P1 and P2 of the resistor.
A titre indicatif, et non limitatif, la résistance représentée en figure 7 est constituée d'éléments résistifs présentant chacun les caractéristiques suivantes :  For information, and not limitation, the resistance shown in Figure 7 consists of resistive elements each having the following characteristics:
diamètre des trous : 1 μm ;  hole diameter: 1 μm;
profondeur des trous : 50 μm ;  hole depth: 50 μm;
espace entre deux trous : 2 μm ;  space between two holes: 2 μm;
diamètre maximal de la cavité enterrée : 3,5 μm ;  maximum diameter of the buried cavity: 3.5 μm;
largeur maximale des bandes résistives : 2 μm ; et les éléments résistifs sont positionnés les uns par rapport aux autres de la façon suivante :  maximum width of the resistive strips: 2 μm; and the resistive elements are positioned in relation to each other as follows:
espace entre les trous d'éléments résistifs de rangées voisines : 4 μm ;  space between the holes of resistive elements of neighboring rows: 4 μm;
espace entre deux trous voisins de deux éléments résistifs successifs d'une même rangée : 4 μm .  space between two neighboring holes of two successive resistive elements of the same row: 4 μm.
Par ailleurs, on notera que pour une valeur de résistance donnée, la surface occupée par une résistance selon la présente invention est beaucoup plus faible, 5 à 10 fois plus faible, que celle occupée par une résistance classique formée en surface d'une plaquette de silicium.  Furthermore, it will be noted that for a given resistance value, the surface occupied by a resistance according to the present invention is much smaller, 5 to 10 times smaller, than that occupied by a conventional resistance formed on the surface of a wafer. silicon.
Bien entendu, la présente invention est susceptible de diverses variantes et modifications qui apparaîtront à l'homme de l'art. En particulier, l'homme de l'art pourra imaginer diverses formes de résistances constituées d'éléments résistifs élémentaires agencés différemment.  Of course, the present invention is susceptible of various variants and modifications which will appear to those skilled in the art. In particular, those skilled in the art will be able to imagine various forms of resistance made up of elementary resistive elements arranged differently.
De plus, l'homme de l'art pourra imaginer d'autres procédés de formation d'un élément résistif selon la présente invention. On pourra par exemple remplir complètement des conduits préalablement formés et isolés d'un matériau résistif tel que du silicium polycristallin.  In addition, those skilled in the art can imagine other methods of forming a resistive element according to the present invention. We can for example completely fill conduits previously formed and isolated with a resistive material such as polycrystalline silicon.

Claims

REVENDICATIONS
1. Elément résistif comprenant deux parties résistives verticales (RIa, RIb) placées dans deux trous (2a, 2b) formés dans la partie supérieure d'un substrat (1) et une partie résistive horizontale (RIc) formée dans une cavité enterrée reliant les fonds des trous, les parties résistives verticales et horizontale étant formées par une couche résistive isolée (21) recouvrant les parois des trous et la cavité. 1. Resistive element comprising two vertical resistive parts (RIa, RIb) placed in two holes (2a, 2b) formed in the upper part of a substrate (1) and a horizontal resistive part (RIc) formed in a buried cavity connecting the bottom of the holes, the vertical and horizontal resistive parts being formed by an insulated resistive layer (21) covering the walls of the holes and the cavity.
2. Résistance comprenant plusieurs éléments résistifs (Rl, R2) selon la revendication 1 reliés les uns aux autres par des bandes résistives placées sur le substrat et formées à partir de portions de ladite couche résistive.  2. Resistor comprising several resistive elements (Rl, R2) according to claim 1 connected to each other by resistive strips placed on the substrate and formed from portions of said resistive layer.
3. Elément résistif selon la revendication 1, dans lequel le substrat (1) est une plaquette de silicium, ladite couche résistive (21) étant séparée du substrat par une couche isolante (20) telle qu'une couche d'oxyde de silicium.  3. Resistive element according to claim 1, in which the substrate (1) is a silicon wafer, said resistive layer (21) being separated from the substrate by an insulating layer (20) such as a layer of silicon oxide.
4. Elément résistif selon la revendication 1, dans lequel les trous et la cavité sont remplis d'un matériau de remplissage (30) tel que du silicium polycristallin.  4. A resistive element according to claim 1, in which the holes and the cavity are filled with a filling material (30) such as polycrystalline silicon.
5. Elément résistif selon la revendication 4, dans lequel la couche résistive (21) et le matériau de remplissage 5. Resistive element according to claim 4, in which the resistive layer (21) and the filling material
(30) sont séparés par une couche isolante (22) telle qu'une couche d'oxyde de silicium. (30) are separated by an insulating layer (22) such as a layer of silicon oxide.
6. Elément résistif selon la revendication 1, dans lequel la couche résistive (21) est constituée de silicium polycristallin ou d'un métal.  6. Resistive element according to claim 1, in which the resistive layer (21) consists of polycrystalline silicon or of a metal.
7. Procédé de formation d'un élément résistif dans un substrat (1) comprenant les étapes suivantes :  7. A method of forming a resistive element in a substrate (1) comprising the following steps:
former, par gravure anisotrope, deux trous (2a, 2b) dans la partie supérieure d'un substrat ;  forming, by anisotropic etching, two holes (2a, 2b) in the upper part of a substrate;
former, par gravure isotrope au fond des trous, une cavité (5) reliant le fond des deux trous, les trous et la cavité constituant un conduit (10) ; et  forming, by isotropic etching at the bottom of the holes, a cavity (5) connecting the bottom of the two holes, the holes and the cavity constituting a conduit (10); and
effectuer un dépôt conforme d'une couche résistive (21) contre les parois du conduit. perform a conformal deposition of a resistive layer (21) against the walls of the duct.
8. Procédé selon la revendication 7, comprenant, préalablement au dépôt conforme de la couche résistive (21) , une étape de dépôt conforme d'une première couche isolante (20), et comprenant en outre une étape de dépôt conforme d'une seconde couche isolante (22) recouvrant ladite couche résistive, ainsi qu'une étape de remplissage du conduit avec un matériau de remplissage (30) tel que du silicium polycristallin. 8. The method of claim 7, comprising, prior to the conformal deposition of the resistive layer (21), a conformal deposition step of a first insulating layer (20), and further comprising a conformal deposition step of a second insulating layer (22) covering said resistive layer, as well as a step of filling the conduit with a filling material (30) such as polycrystalline silicon.
9. Procédé selon la revendication 7, dans lequel, lors de la formation de la couche résistive (21) contre les parois du conduit (10) il se forme une couche résistive en surface du substrat, et comprenant en outre une étape de gravure de la couche résistive en surface du substrat pour former des bandes résistives (A21, B21) .  9. The method of claim 7, wherein, during the formation of the resistive layer (21) against the walls of the conduit (10) a resistive layer is formed on the surface of the substrate, and further comprising an etching step of the resistive layer on the surface of the substrate to form resistive bands (A21, B21).
EP06842091A 2005-12-06 2006-12-05 Resistance in an integrated circuit Withdrawn EP1958258A1 (en)

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US8232169B2 (en) 2012-07-31
US7902605B2 (en) 2011-03-08
CN101326639A (en) 2008-12-17
WO2007066037A1 (en) 2007-06-14
US20090127658A1 (en) 2009-05-21
US20110115053A1 (en) 2011-05-19

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