EP1943718A1 - Circuit de commande de commutation de convertisseurs de puissance commandee du cote primaire - Google Patents

Circuit de commande de commutation de convertisseurs de puissance commandee du cote primaire

Info

Publication number
EP1943718A1
EP1943718A1 EP05795427A EP05795427A EP1943718A1 EP 1943718 A1 EP1943718 A1 EP 1943718A1 EP 05795427 A EP05795427 A EP 05795427A EP 05795427 A EP05795427 A EP 05795427A EP 1943718 A1 EP1943718 A1 EP 1943718A1
Authority
EP
European Patent Office
Prior art keywords
signal
current
voltage
switching
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05795427A
Other languages
German (de)
English (en)
Other versions
EP1943718A4 (fr
Inventor
Ta-Yung Yang
Guo-Kiang Hung
Jenn-Yu G. Lin
Chuh-Ching Li
Shao-Wei Chiu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Taiwan Corp
Original Assignee
System General Corp Taiwan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by System General Corp Taiwan filed Critical System General Corp Taiwan
Publication of EP1943718A1 publication Critical patent/EP1943718A1/fr
Publication of EP1943718A4 publication Critical patent/EP1943718A4/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters

Definitions

  • the present invention relates to a control circuit for a power converter, and more specifically, to a switching control circuit for switching mode power converters.
  • the object of the present invention is to provide a switching control circuit for controlling the output voltage and the output current of a power converter at the primary side without the optical-coupler and secondary-side regulator. Furthermore, frequency hopping is developed for spreading the switching frequency of the switching signal and reducing the EMI (electric and magnetic interference). Therefore, the size and the cost of the power converter can be effectively reduced.
  • a switching control circuit for a primary-side-controlled power converter comprises a switching device to switch a transformer.
  • a switching signal drives
  • a controller is coupled to the transformer and a current-sense device to generate a voltage-feedback signal and a current-feedback signal by sampling a voltage signal and a discharge time of the transformer during the off-time of the switching signal, and measuring a current signal of the transformer during the on-time of the switching signal.
  • the switching signal is generated in response to the voltage-feedback signal and the current-feedback signal.
  • the controller further comprises a voltage-waveform detector for multi-sampling the voltage signal and producing the voltage-feedback signal and a discharge-time signal.
  • the voltage-waveform detector is connected to an auxiliary winding of a transformer through a resistor of a voltage divider.
  • the discharge-time signal represents the discharge time of the transformer and stands for the discharge time of a secondary-side switching current.
  • a current- waveform detector generates a current- waveform signal by measuring the current signal.
  • An oscillator generates an oscillation signal for determining a switching frequency of the switching signal.
  • An integrator is used for generating the current-feedback signal by integrating the current-waveform signal with the discharge time.
  • a first operational amplifier and a first reference voltage develop a voltage-loop error amplifier to amplify the voltage-feedback signal and provide a loop gain for output voltage control.
  • a second operational amplifier and a second reference voltage form a current-loop error amplifier to amplify the current-feedback signal and provide a loop gain for output current control.
  • a PWM circuit associates with a first comparator and a second comparator to control the pulse width of the switching signal in response to the output of the voltage-loop error amplifier and the output of the current-loop error amplifier.
  • a programmable current source is connected to the input of the voltage-waveform detector for temperature compensation. The programmable current source produces a programmable current in response to the temperature of the controller, which compensates the temperature deviation of the power converter.
  • a pattern generator generates a digital pattern code.
  • a first programmable capacitor is coupled to the oscillator and the pattern generator for modulating the switching frequency in response to the digital pattern code.
  • a second programmable capacitor is coupled to the integrator and the pattern generator for correlating a time constant of the integrator with the switching frequency.
  • the current-feedback signal is therefore proportional to the output current of the power converter.
  • the capacitance of the first programmable capacitor and the second programmable capacitor are controlled by the digital pattern code.
  • FIG. 1 shows a schematic diagram of a power converter having a switching control circuit.
  • FIG. 2 shows key waveforms of the power converter and the switching control circuit.
  • FIG. 3 shows an embodiment of a controller according to the present invention.
  • FIG. 4 shows an embodiment of a voltage- waveform detector according to the present invention.
  • FIG. 5 shows an embodiment of an oscillator according to the present invention.
  • FIG. 6 shows an embodiment of a current- waveform detector according to the present invention.
  • FIG. 7 shows an embodiment of an integrator according to the present invention.
  • FIG. 8 shows an embodiment of a PWM circuit according to the present invention.
  • FIG. 9 shows an embodiment of an adder according to the present invention.
  • FIG. 10 shows an embodiment of a pattern generator according to the present invention.
  • FIG. 11 shows an embodiment of a programmable capacitor according to the present invention.
  • FIG. 1 shows a power converter.
  • the power converter includes a transformer 10 having an auxiliary winding N A , a primary winding Np, and a secondary winding Ns.
  • the primary winding Np is supplied with an input voltage Vi N of the power converter.
  • a controller 70 In order to regulate an output voltage Vo and an output current I 0 of the power converter, a controller 70 generates a switching signal V PWM , which controls a switching device, such as a transistor 20, to switch the transformer 10.
  • a current-sense resistor 30 serves as a current-sense device.
  • FIG. 2 shows various signal waveforms of the power converter in FIG. 1.
  • a primary-side switching current Ip will be generated accordingly.
  • a peak value I P i of a primary-side switching current Ip can be given by,
  • a peak value I S i of a secondary-side switching current I s can be expressed by, kl J ⁇ l ⁇ x ⁇ (2)
  • V 0 is the output voltage of the power converter; Vp is a forward voltage drop of the rectifier 40; Ls is the inductance of the secondary winding Ns of the transformer 10; T DS is a discharge time of the secondary-side switching current Is.
  • a voltage signal V A ux is generated at the auxiliary winding N A of the transformer 10.
  • a voltage level V AU ⁇ i of the voltage signal V A ux is shown as,
  • T NA and T NS are respectively the winding turns of the auxiliary winding N A and the secondary winding N s of the transformer 10.
  • the voltage signal V AUX starts to decrease as the secondary-side switching current Is drops to zero. This also indicates that the energy of the transformer 10 is fully released at this moment. Therefore, as shown in FIG. 2, the discharge time T D s in equation (2) can be measured from a falling edge of the switching signal V PWM to a point that the voltage signal V AUX starts to fall.
  • the secondary-side switching current 1$ is determined by the primary-side switching current I P and the winding turns of the transformer 10.
  • the secondary-side switching current Is can be expressed by,
  • T NP is the winding turns of the primary winding Np of the transformer 10.
  • the controller 70 comprises a supply terminal VCC and a ground terminal GND for receiving power.
  • a resistor 50 and a resistor 51 are connected in series to form a voltage divider, which is connected between the auxiliary winding N A of the transformer 10 and a ground reference level.
  • a detection terminal DET of the controller 70 is connected to a joint of the resistor 50 and the resistor 51.
  • a voltage V DET generated at the detection terminal DET can be given by,
  • R 50 and R 51 are respectively the resistance of resistors 50 and 51.
  • the voltage signal V A ux further charges a capacitor 65 via a rectifier 60 for powering the controller 70.
  • the current-sense resistor 30 is connected from a source of the transistor 20 to the ground reference level for converting the primary-side switching current I P to a current signal V C s- A sense terminal CS of the controller 70 is connected to the current-sense resistor 30 for detecting the current signal Vcs-
  • An output terminal OUT of the controller 70 generates the switching signal V PWM to switch the transformer 10.
  • a compensation network is connected to a voltage-compensation terminal COMV of the controller 70 for voltage-loop frequency compensation.
  • the compensation network can be a capacitor connected to the ground reference level, such as a capacitor 31.
  • Another compensation network is connected to a current-compensation terminal COMI of the controller 70 for current-loop frequency compensation.
  • the compensation network can also be a capacitor connected to the ground reference level, such as a capacitor 32.
  • FIG. 3 shows an embodiment of the controller 70.
  • a voltage-waveform detector 100 produces a voltage-feedback signal V v and a discharge-time signal S DS by multi-sampling the voltage V DET -
  • the discharge-time signal S DS represents the discharge time T DS of the secondary-side switching current Is-
  • a current-waveform detector 300 generates a current-waveform signal Vw by measuring the current signal Vcs-
  • An oscillator 200 generates an oscillation signal PLS for determining a switching frequency of the switching signal
  • V PWM - An integrator 400 produces a current-feedback signal Vi by integrating the current- waveform signal V w with the discharge time T D s-
  • An operational amplifier 71 and a reference voltage V REFI develop a voltage-loop error amplifier for amplifying the voltage-feedback signal V v and providing a loop gain for output voltage control.
  • An operational amplifier 72 and a reference voltage V REF2 develop a current-loop error amplifier for amplifying the current-feedback signal Vi and providing a loop gain for output current control.
  • a switching circuit 500 associates with comparators 73 and 75 to control the pulse width of the switching signal V PWM in response to the outputs of the voltage-loop error amplifier and the current-loop error amplifier.
  • Both operational amplifiers 71 and 72 have trans-conductance output.
  • An output of the operational amplifier 71 is connected to the voltage-compensation terminal COMV and a positive input of the comparator 73.
  • An output of the operational amplifier 72 is connected to the current-compensation terminal COMI and a positive input of the comparator 75.
  • a negative input of the comparator 73 is connected to an output of an adder 600.
  • a negative input of the comparator 75 is supplied with a ramp signal RMP that is produced from the oscillator 200.
  • the adder 600 generates a slope signal V SLP by adding the current signal Vcs with the ramp signal RMP, which forms a slope compensation for the voltage-loop.
  • a positive input of a comparator 74 is supplied with a reference voltage V REF3 -
  • a negative input of the comparator 74 is connected to the sense terminal CS for achieving a cycle-by-cycle current limit.
  • Three inputs of a NAND gate 79 are respectively connected to the outputs of comparators 73, 74 and 75. An output of the NAND gate 79 generates a reset signal RST.
  • the reset signal is applied to the PWM circuit 500 for controlling the duty cycle of the switching signal V PWM -
  • a current control loop is formed from the detection of the primary-side switching current I P to the pulse width modulation of the switching signal Vpw M for controlling the magnitude of the primary-side switching current I P in response to the reference voltage V REF2 -
  • the secondary-side switching current Is is a ratio of the primary-side switching current Ip as shown in equation (4). According to the signal waveforms in FIG. 2, the output current I 0 of the power converter is the average of the secondary-side switching current Is- It can be expressed by,
  • the current-waveform detector 300 detects the current signal V C s and generates the current-waveform signal Vw
  • the integrator 400 further produces the current-feedback signal Vi by integrating the current-waveform signal V w with the discharge time T D s-
  • the current-feedback signal Vi is thus designed as,
  • Ti is a time constant of the integrator 400.
  • the current-feedback signal V 1 is proportional to the output current I 0 of the power converter.
  • the current-feedback signal Vi is increased as the output current Io increases.
  • a maximum value of the current-feedback signal V 1 is limited to the value of the reference voltage V REF2 through the regulation of the current control loop. Under feedback control of the current control loop, a maximum output current Io( ma ⁇ ) is given by,
  • K is a constant equal to T/T
  • G A is the gain of the current-loop error amplifier
  • Gsw is the gain of the switching circuit.
  • the maximum output current Io( ma ⁇ ) of the power converter is thus regulated as a constant current in response to the reference voltage V REF2 .
  • a voltage control loop is developed from the voltage signal V AUX sampling to the pulse width modulation of the switching signal V PWM , which controls the magnitude of the voltage signal V A u ⁇ in response to the reference voltage V REFI .
  • the voltage signal V Al j ⁇ is a ratio of the output voltage Vo as shown in equation (3).
  • the voltage signal V A ux is further attenuated to the voltage V DET as shown in equation (5).
  • the voltage-waveform detector 100 generates the voltage-feedback signal Vy through multi-sampling the voltage V DET -
  • the value of the voltage-feedback signal Vy is controlled in response to the value of the reference voltage V REFI through the regulation of the voltage control loop.
  • the voltage-loop error amplifier and the switching circuit provide the loop gain for the voltage control loop. Therefore the output voltage Vo can be briefly defined as,
  • the voltage signal V A ux is multi-sampled by the voltage-waveform detector 100.
  • the voltage is sampled and measured instantly before the secondary-side switching current I s drops to zero. Therefore the variation of the secondary-side switching current Is does not affect the value of the forward voltage drop Vp of the rectifier 40.
  • the voltage drop Vp of the rectifier 40 varies when temperature changes.
  • a programmable current source 80 is connected to an input of the voltage- waveform detector 100 for temperature compensation.
  • the programmable current source 80 produces a programmable current I ⁇ in response to the temperature of the controller 70.
  • the programmable current I ⁇ associates with the resistors 50, 51 to generate a voltage V ⁇ to compensate the temperature variation of the forward voltage drop V F of the rectifier 40.
  • a pattern generator 900 generates a digital pattern code P N " P I -
  • a first programmable capacitor 910 is coupled to the oscillator 200 and the pattern generator 900 for modulating the switching frequency of the switching signal V PWM in response to the digital pattern code P N " P I .
  • a second programmable capacitor 930 is coupled to the integrator 400 and the pattern generator 900 for correlating the time constant T 1 of the integrator 400 with the switching frequency. The capacitance of the first programmable capacitor 910 and the second programmable capacitor 930 are controlled by the digital pattern code P N " P I .
  • FIG 10 shows an embodiment of the pattern generator 900 according to the present invention.
  • a clock generator 951 generates a clock signal CK.
  • a plurality of registers 971, 972 • • 975 and a XOR gate 952 develop a linear shift register for generating a linear code in response to the clock signal CK.
  • the inputs of the XOR gate 952 determine the polynomials of the linear shift register and decide the output of the linear shift register.
  • the digital pattern code P N • • Pi can be obtained from the part of the linear code to optimize the application.
  • FIG 4 shows an embodiment of the voltage- waveform detector 100 according to the present invention.
  • a sample-pulse generator 190 produces a sample-pulse signal for multi-sampling operation.
  • a threshold voltage 156 adds to the voltage signal V AUX to produce a level-shift signal.
  • a first signal generator includes a D flip-flop 171, two AND gates 165, 166 for producing a first sample signal Vspi and a second sample signal V SP2 -
  • a second signal generator comprises a D flip-flop 170, a NAND gate 163, an AND gate 164 and a comparator 155 for producing the discharge-time signal S DS -
  • a time-delay circuit includes an inverter 162, a current source 180, a transistor 181 and a capacitor 182 for generating a delay time T d as the switching signal V PWM is disabled.
  • An input of an inverter 161 is supplied with the switching signal V PWM -
  • An output of the inverter 161 is connected to an input of the inverter 162, a first input of the AND gate 164 and a clock-input of the D flip-flop 170.
  • An output of the inverter 162 turns on/off the transistor 181.
  • the capacitor 182 is connected in parallel with the transistor 181.
  • the current source 180 is applied to charge the capacitor 182. Therefore the current of the current source 180 and the capacitance of the capacitor 182 decide the delay time T d of the time-delay circuit.
  • the capacitor 182 is the output of the time-delay circuit.
  • a D-input of the D flip-flop 170 is pulled high by a supply voltage Vcc-
  • An output of the D flip-flop 170 is connected to a second input of the AND gate 164.
  • the AND gate 164 outputs the discharge-time signal S DS .
  • the discharge-time signal S DS is thus enabled as the switching signal V PWM is disabled.
  • the output of the NAND gate 163 is connected to a reset-input of the D flip-flop 170.
  • the inputs of the NAND gate 163 are connected to the output of the time-delay circuit and an output of the comparator 155. A negative input of the comparator 155 is supplied with the level-shift signal.
  • a positive input of the comparator 155 is supplied with the voltage-feedback signal Vy- Therefore, after the delay time T d , the discharge-time signal S D s can be disable once the level-shift signal is lower than the voltage-feedback signal V v . Besides, the discharge-time signal S DS can also be disabled as long as the switching signal VPWM is enabled.
  • the sample-pulse signal is supplied to a clock-input of the D flip-flop 171 and third inputs of AND gates 165 and 166.
  • a D-input and an inverse output of the D flip-flop 171 are connected together to form a divided-by-two counter.
  • An output and the inverse output of the D flip-flop 171 are respectively connected to second inputs of AND gates 165 and 166.
  • First inputs of AND gates 165 and 166 are both supplied with the discharge-time signal S DS .
  • Fourth inputs of AND gates 165 and 166 are connected to the output of the time-delay circuit. Therefore the first sample signal V SP i and the second sample signal V S p 2 are generated in response to the sample-pulse signal.
  • the first sample signal Vspi and the second sample signal V S p 2 are alternately produced during an enabled period of the discharge-time signal S DS .
  • the delay time T d is inserted at the beginning of the discharge-time signal S DS to inhibit the first sample signal V S pi and the second sample signal Vsp 2 -
  • the first sample signal V SPI and the second sample signal V SP2 are thus disabled during the period of the delay time T d .
  • the first sample signal V SPI and the second sample signal V SP2 are used for alternately sampling the voltage signal V A ux via the detection terminal DET and the divider.
  • the first sample signal V SP i and the second sample signal V SP2 control a switch 121 and a switch 122 for obtaining a first hold voltage and a second hold voltage across a capacitor 110 and a capacitor 111 respectively.
  • a switch 123 is connected in parallel with the capacitor 110 to discharge the capacitor 110.
  • a switch 124 is connected in parallel with the capacitor 111 to discharge the capacitor 111.
  • a buffer amplifier includes operational amplifiers 150 and 151, diodes 130, 131, a current source 135 for generating a hold voltage. The positive inputs of operational amplifiers 150 and 151 are connected to the capacitor 110 and capacitor 111 respectively.
  • the negative inputs of the operational amplifiers 150 and 151 are connected to an output of the buffer amplifier.
  • the diode 130 is connected from an output of the operational amplifier 150 to the output of the buffer amplifier.
  • the diode 131 is connected from an output of the operational amplifier 151 to the output of the buffer amplifier.
  • the hold voltage is thus obtained from the higher voltage of the first hold voltage and the second hold voltage.
  • the current source 135 is used for the termination.
  • a switch 125 periodically conducts the hold voltage to a capacitor 115 for producing the voltage-feedback signal V v .
  • the switch 125 is turned on/off by the oscillation signal PLS.
  • the first sample signal V S pi and the second sample signal V SP2 start to produce the first hold voltage and the second hold voltage after the delay time T d , which eliminates the spike interference of the voltage signal V A ux-
  • the spike of the voltage signal V A ux would be generated when the switching signal V PWM is disabled and the transistor 20 is turned off.
  • the voltage signal V AU ⁇ starts to decrease as the secondary-side switching current I 8 drops to zero, which is detected by the comparator 155 to disable the discharge-time signal S DS -
  • the pulse width of the discharge-time signal S DS is therefore correlated to the discharge time T DS of the secondary-side switching current I s.
  • the hold voltage generated at the output of the buffer amplifier represents an end voltage.
  • the end voltage is thus correlated to the voltage signal V AUX that is sampled just before the secondary-side switching current I 8 dropping to zero.
  • the hold voltage is obtained from the higher voltage of the first hold voltage and the second hold voltage, which will ignore the voltage that is sampled when the voltage signal V AU ⁇ starts to decrease.
  • FIG. 5 shows an embodiment of the oscillator 200 according to the present invention.
  • An operational amplifier 201, a resistor 210 and a transistor 250 form a first V-to-I converter.
  • the first V-to-I converter generates a reference current I250 in response to a reference voltage V REF .
  • a plurality of transistors, such as 251, 252, 253, 254, 255 form current mirrors for generating an oscillator charge current I 253 and an oscillator discharge current I 255 in response to the reference current I ⁇ so-
  • a drain of the transistor 253 generates the oscillator charge current I 253 .
  • a drain of the transistor 255 generates the oscillator discharge current I 255 .
  • a switch 230 is connected between the drain of the transistor 253 and a capacitor 215.
  • a switch 231 is connected between the drain of the transistor 255 and the capacitor 215.
  • the ramp signal RMP is obtained across the capacitor 215.
  • a comparator 205 has a positive input connected to the capacitor 215.
  • the comparator 205 outputs the oscillation signal PLS.
  • the oscillation signal PLS determines the switching frequency.
  • a first terminal of a switch 232 is supplied with a high threshold voltage V H .
  • a first terminal of a switch 233 is supplied with a low threshold voltage V L -
  • a second terminal of the switch 232 and a second terminal of the switch 233 are both connected to a negative input of the comparator 205.
  • An input of an inverter 260 is connected to an output of the comparator 205 for producing an inverse oscillation signal /PLS.
  • the oscillation signal PLS turns on/off the switch 231 and the switch 233.
  • the inverse oscillation signal /PLS turns on/off the switch 230 and the switch 232.
  • the first programmable capacitor 910 in FIG. 3 is connected in parallel with the capacitor 215 for modulating the switching frequency in response to the digital pattern code P N " P I .
  • the resistance R 2 io of the resistor 210, the capacitance C 215 of the capacitor 215 and the capacitance C 910 of the first programmable capacitor 910 determine the switching period T of the switching frequency.
  • the switching period T is given by,
  • FIG. 6 shows an embodiment of the current- waveform detector 300 according to the present invention.
  • a peak detector includes a comparator 310, a current source 320, switches 330, 340, and a capacitor 361.
  • the peak value of the current signal V C s is sampled for generating a peak-current signal.
  • a positive input of the comparator 310 is supplied with the current signal Vcs-
  • a negative input of the comparator 310 is connected to the capacitor 361.
  • the switch 330 is connected between the current source 320 and the capacitor 361.
  • the output of the comparator 310 turns on/off the switch 330.
  • the switch 340 is connected in parallel with the capacitor 361 for discharging the capacitor 361.
  • a switch 350 periodically conducts the peak-current signal to a capacitor 362 for producing the current-waveform signal Vw-
  • the switch 350 is turned on/off by the oscillation signal PLS.
  • FIG. 7 shows an embodiment of the integrator 400 according to the present invention.
  • a second V-to-I converter comprises an operational amplifier 410, a resistor 450 and transistors 420, 421, and 422.
  • a positive input of the operational amplifier 410 is supplied with the current- waveform signal Vw
  • a negative input of the operational amplifier 410 is connected to the resistor 450.
  • An output of the operational amplifier 410 drives a gate of the transistor 420.
  • a source of the transistor 420 is coupled to the resistor 450.
  • the second V-to-I converter generates a current I 4 ⁇ o via a drain of the transistor 420 in response to the current-waveform signal V w .
  • Transistors 421 and 422 form a current mirror having a 2: 1 ratio. The current mirror is driven by the current I 420 to produce a programmable charge current I PRG via a drain of the transistor 422.
  • the programmable charge current I PRG can be expressed by,
  • a capacitor 471 is used to produce an integrated signal.
  • a switch 460 is connected between the drain of the transistor 422 and the capacitor 471. The switch 460 is turned on/off by the discharge-time signal S D s .
  • a switch 462 is connected in parallel with the capacitor 471 for discharging the capacitor 471.
  • the second programmable capacitor 930 in FIG. 3 is connected in parallel with the capacitor 471 at a Cx terminal of the integrator 400 for correlating the time constant Ti of the integrator 400 with the switching frequency.
  • the capacitance C 930 of the second programmable capacitor 930 varies in response to the variation of the digital pattern code P N " P I .
  • a switch 461 periodically conducts the integrated signal to a capacitor 472 for producing the current-feedback signal Vi.
  • the switch 461 is turned on/off by the oscillation signal PLS.
  • the current-feedback signal V 1 is therefore obtained across the capacitor 472.
  • equation (9) can be rewritten as,
  • m is a constant which is determined by
  • the resistance R 450 of the resistor 450 is correlated to the resistance R2 10 of the resistor 210.
  • the capacitance C 47I of the capacitor 471 and the capacitance C 930 of the capacitor 930 are correlated to the capacitance C 215 of the capacitor 215 and the capacitance C 910 of the capacitor 910. Therefore, the current-feedback signal Vi is proportional to the output current I 0 of the power converter.
  • FIG. 8 shows a schematic diagram of the PWM circuit 500 according to the present invention.
  • the PWM circuit 500 includes a NAND gate 511, a D flip-flop 515, an AND gate 519, a blanking circuit 520 and inverters 512 and
  • a D-input of the D flip-flop 515 is pulled high by the supply voltage V C c-
  • the oscillation signal PLS drives an input of the inverter 512.
  • An output of the inverter 512 is connected to a clock-input of the D flip-flop 515 for enabling the switching signal V PWM -
  • An output of the D flip-flop 515 is connected to a first input of the AND gate 519.
  • a second input of the AND gate 519 is coupled to the output of the inverter 512.
  • the AND gate 519 outputs the switching signal V PWM -
  • a reset-input of the D flip-flop 515 is driven by an output of the NAND gate 511.
  • a first input of the NAND gate 511 is supplied with the reset signal RST for cycle-by-cycle disabling the switching signal V PWM -
  • the second input of the NAND gate 511 is connected to an output of the blanking circuit 520 for ensuring a minimum on-time of the switching signal V PWM once the switching signal V PWM is enabled.
  • the minimum on-time of the switching signal V PWM will secure a minimum value of the discharge time T DS , which will ensure a proper multi-sampling operation for sampling voltage signal V A ux in the voltage-waveform detector 100.
  • the discharge time T DS is related to the on-period of the switching signal V PWM - Referring to equations (1), (2), (4) and the secondary inductance Ls, which is given by equation (20), the discharge time T DS can be expressed as equation
  • T ON is the on-time of the switching signal V PWM -
  • the blanking circuit 520 comprises a NAND gate 523, a current source 525, a capacitor 527, a transistor 526 and inverters 521 and 522.
  • the switching signal V P ⁇ VM is supplied to an input of the inverter 521 and a first input of the NAND gate 523.
  • the current source 525 is applied to charge the capacitor 527.
  • the capacitor 527 is connected between a drain and a source of the transistor 526.
  • An output of the inverter 521 turns on/off the transistor 526.
  • An input of the inverter 522 is coupled to the capacitor 527.
  • An output of the inverter 522 is connected to a second input of the NAND gate 523.
  • An output of the NAND gate 523 generates the blanking signal V BLK -
  • the current of the current source 525 and the capacitance of the capacitor 527 determine the pulse width of the blanking signal V BLK -
  • the input of an inverter 518 is connected to the output of the NAND gate 523.
  • An output of the inverter 518 generates a clear signal CLR to turn on/off switches 123, 124, 340 and 462.
  • FIG. 9 shows a schematic diagram of the adder 600 according to the present invention.
  • An operational amplifier 610, transistors 620, 621, 622 and a resistor 650 develop a third V-to-I converter for generating a current 1 622 in response to the ramp signal RMP.
  • V SLP is generated at the drain of the transistor 622. The slope signal V SLP is therefore correlated to the ramp signal RMP and the current signal V C s-
  • FIG. 11 shows an embodiment of a programmable capacitor, such as the first programmable capacitor 910 and the second programmable capacitor 930.
  • the programmable capacitor comprises switching-capacitor sets connected to each other in parallel.
  • the switching-capacitor sets are respectively formed by capacitors Ci, C 2 , “ ,C N and switches Si,S 2 , “ S N -
  • the switch Si and the capacitor Ci are connected in series.
  • the switch S 2 and the capacitor C 2 are connected in series.
  • the switch S N and the resistor C N are connected in series.
  • the digital pattern code P N " Pi controls switches Si, S 2 , " S N . Therefore, the capacitance of the programmable capacitor can be changed.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

La présente invention concerne un circuit de commande de commutation de convertisseur de puissance commandé du côté primaire. Un détecteur de forme d'onde de tension produit un signal de retour de tension et un signal de temps de décharge. Un détecteur de forme d'onde de courant génère un signal de forme d'onde de courant en mesurant le courant de commutation côté primaire. Un intégrateur génère un signal de retour de courant en intégrant le signal de forme d'onde de courant avec le temps de décharge. Une constante de temps de l'intégrateur est corrélée avec la fréquence de commutation, le signal de retour de courant étant ainsi proportionnel à un courant de sortie du convertisseur de puissance. Un circuit PWM commande la largeur d'impulsion du signal de commutation en réponse aux sorties d'un amplificateur d'erreur de circuit de tension et d'un amplificateur d'erreur de circuit de courant. La tension de sortie et le courant de sortie maximum du convertisseur de puissance sont ainsi régulés.
EP05795427A 2005-10-09 2005-10-09 Circuit de commande de commutation de convertisseurs de puissance commandee du cote primaire Withdrawn EP1943718A4 (fr)

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JP5732214B2 (ja) * 2010-08-26 2015-06-10 ローム株式会社 同期動作回路および通信機器
CN102386793A (zh) * 2010-08-31 2012-03-21 刘建坤 阶层式能量控制器及电源供应器
JP5483755B2 (ja) * 2011-03-16 2014-05-07 株式会社 ハイヂィープ 電流制御電源供給装置
JP5400833B2 (ja) * 2011-06-06 2014-01-29 シャープ株式会社 スイッチング電源回路、半導体装置、ｌｅｄ照明装置
JP2013090441A (ja) * 2011-10-18 2013-05-13 Hoa Chon Co Ltd 力率改善のための回路
JP6136173B2 (ja) 2012-10-03 2017-05-31 サンケン電気株式会社 直流電源装置
KR101375138B1 (ko) * 2013-02-19 2014-03-17 옵티멀파워디자인 주식회사 Ｐｓｒ 시스템에서 지연신호에 의한 전압 감지 회로 및 방법

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Publication number Publication date
JP2009512404A (ja) 2009-03-19
WO2007041894A1 (fr) 2007-04-19
JP4724229B2 (ja) 2011-07-13
EP1943718A4 (fr) 2011-10-12
KR100982169B1 (ko) 2010-09-15
KR20080066001A (ko) 2008-07-15

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