Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
  • G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
  • G11C11/5628—Programming or writing circuits; Data input circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
  • G11C11/5628—Programming or writing circuits; Data input circuits
  • G11C11/5635—Erasing circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/10—Programming or data input circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/10—Programming or data input circuits
  • G11C16/12—Programming voltage switching circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/3436—Arrangements for verifying correct programming or erasure
  • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
  • G11C16/345—Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/3436—Arrangements for verifying correct programming or erasure
  • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/3436—Arrangements for verifying correct programming or erasure
  • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/3436—Arrangements for verifying correct programming or erasure
  • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
  • G11C16/3472—Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/3436—Arrangements for verifying correct programming or erasure
  • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
  • G11C16/3477—Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/10—Programming or data input circuits
  • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
  • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
  • G11C2211/562—Multilevel memory programming aspects
  • G11C2211/5621—Multilevel programming verification
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
  • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
  • G11C2216/18—Flash erasure of all the cells in an array, sector or block simultaneously

Definitions

• the present invention relates generally to semiconductor technology for erasing non-volatile memory devices.
• Non- volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices.
• Electrical Erasable Programmable Read Only Memory (EEPROM), including flash EEPROM, and Electronically Programmable Read Only Memory (EPROM) are among the most popular non-volatile semiconductor memories.
• EEPROM Electrical Erasable Programmable Read Only Memory
• EPROM Electronically Programmable Read Only Memory
• NAND structure which includes arranging multiple transistors in series, sandwiched between two select gates. The transistors in series and the select gates are referred to as a NAND string.
• Figure 1 is a top view showing one NAND string.
• Figure 2 is an equivalent circuit thereof.
• the NAND string depicted in Figures 1 and 2 includes four transistors 100, 102, 104 and 106 in series and sandwiched between a first select gate 120 and a second select gate 122.
• Select gate 120 connects the NAND string to bit line 126.
• Select gate 122 connects the NAND string to source line 128.
• Select gate 120 is controlled by applying appropriate voltages to control gate 120CG via selection line SGD.
• Select gate 122 is controlled by applying the appropriate voltages to control gate 122CG via selection line SGS.
• Each of the transistors 100, 102, 104 and 106 includes a control gate and a floating gate, forming the gate elements of a memory cell.
• transistor 100 has control gate IOOCG and floating gate 100FG.
• Transistor 102 includes control gate 102CG and a floating gate 102FG.
• Transistor 104 includes control gate 104CG and floating gate 104FG.
• Transistor 106 includes a control gate 106CG and a floating gate 106FG.
• Control gate IOOCG is connected to word line WL3
• control gate 102CG is connected to word line WL2
• control gate 104CG is connected to word line WLl
• control gate 106CG is connected to word line WLO.
• Figures 1 and 2 show four memory cells in the NAND string, the use of four transistors is only provided as an example.
• a NAND string can have less than four memory cells or more than four memory cells.
• some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string.
• a typical architecture for a flash memory system using a NAND structure will include several NAND strings.
• Figure 3 shows three NAND strings 202, 204 and 206 of a memory array having many more NAND strings.
• Each of the NAND strings of Figure 3 includes two select transistors or gates and four memory cells.
• NAND string 202 includes select transistors 220 and 230, and memory cells 222, 224, 226 and 228.
• NAND string 204 includes select transistors 240 and 250, and memory cells 242, 244, 246 and 248.
• Each string is connected to the source line by one select gate (e.g. select gate 230 and select gate 250).
• a selection line SGS is used to control the source side select gates.
• the various NAND strings are connected to respective bit lines by select gates 220, 240, etc., which are controlled by select line SGD. In other embodiments, the select lines do not necessarily need to be in common.
• Word line WL3 is connected to the control gates for memory cell 222 and memory cell 242.
• Word line WL2 is connected to the control gates for memory cell 224 and memory cell 244.
• Word line WLl is connected to the control gates for memory cell 226 and memory cell 246.
• Word line WLO is connected to the control gates for memory cell 228 and memory cell 248.
• a bit line and respective NAND string comprise a column of the array of memory cells.
• the word lines (WL3, WL2, WLl and WLO) comprise the rows of the array. Each word line connects the control gates of each memory cell in the row.
• word line WL2 is connected to the control gates for memory cells 224, 244 and 252.
• Each memory cell can store data (analog or digital).
• the range of possible threshold voltages of the memory cell is divided into two ranges which are assigned logical data "1" and "0.”
• the threshold voltage is negative after the memory cell is erased, and defined as logic "1.”
• the threshold voltage after a program operation is positive and defined as logic "0.”
• the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell will turn on to indicate logic one is being stored.
• the threshold voltage is positive and a read operation is attempted by applying 0 volts to the control gate, the memory cell will not turn on, which indicates that logic zero is stored.
• a memory cell can also store multiple levels of information, for example, multiple bits of digital data.
• the range of possible threshold voltages is divided into the number of levels of data. For example, if four levels of information are stored, there will be four threshold voltage ranges assigned to the data values "11", “10", “01”, and "00.”
• the threshold voltage after an erase operation is negative and defined as "11.” Three different positive threshold voltages are used for the states of "10", "01", and "00.”
• a program voltage is applied to the control gate (via a selected word line) and the bit line is grounded. Electrons from the p-well are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the cell is raised. The floating gate charge and threshold voltage of the cell can be indicative of a particular state corresponding to stored data.
• Typical erase operations using prior art techniques can lead to differing erase rates amongst memory cells in a NAND string. Some memory cells may reach a target threshold voltage level for an erased state faster or slower than others. This can lead to over-erasure of faster erasing memory cells because they will continue to be subjected to erase voltages that are applied to sufficiently erase the slower memory cells of the NAND string. Thus, the different erase rates can result in a shorter cycling life of a memory cell or NAND string.
• Typical erase operations can also lead to disparate threshold voltages among memory cells of a NAND string. That is, one or more memory cells of the NAND string may have a different threshold voltage after application of one or more erase voltage pulses when compared to other memory cells of the string or device.
• Soft programming includes applying a relatively low program voltage - lower than used for actual programming - to one or more memory cells.
• Soft programming typically includes applying a program voltage as a series of pulses that are increased by a step size in between each application of the program voltage pulses.
• Soft programming raises the memory cells' threshold voltages in order to narrow and/or raise the threshold voltage distribution of the population of erased memory cells. Soft programming, however, may increase program and erase times.
• Technology described herein pertains to technology for erasing and/or soft programming non-volatile memory devices in a manner that provides a more consistent erased threshold voltage.
• a system is provided that considers the individual characteristics, erase behavior, and soft programming behavior of one or more memory cells during erase and soft programming operations.
• a set of non- volatile storage elements can be divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements.
• the entire set of elements is erased until a first subset of the set of elements is verified as erased.
• the first subset can include the faster erasing elements.
• Verifying the first subset includes excluding a second subset from verification. After the first subset is verified as erased, they are inhibited from erasing while the second subset is further erased. The set of elements is verified as erased when the second subset is verified as erased.
• Verifying that the set of elements is erased can include excluding the first subset from verification or verifying both the first and second subsets together. Different step sizes can be used, depending on which subset is being erased and verified, in order to more efficiently and accurately erase the set of elements.
• a set of non- volatile storage elements can be divided into subsets for soft programming in order to more fully soft-program slower soft programming elements.
• the entire set of elements is soft programmed until verified as soft programmed (or until a first subset of elements is verified as soft programmed while excluding a second subset from verification).
• a first subset of elements is inhibited from further soft programming while additional soft programming is carried out on a second subset of elements.
• the second subset can include slower soft programming elements.
• the second subset can then undergo soft programming verification while excluding the first subset from verification.
• Soft programming and verifying for the second subset can continue until it is verified as soft programmed. Different step sizes can be used for increasing the size of the soft programming signal, depending on which subset is being soft programmed and verified.
• soft programming according to the techniques described herein is performed subsequent to erasing in accordance with the techniques described herein.
• a method of erasing non-volatile memory includes enabling erasing of a set of non- volatile storage elements.
• a first and second subset of the set of non- volatile storage elements are enabled for erasing.
• One or more erase voltage pulses are then applied to the set while the first and second subset of non-volatile storage elements are enabled for erasing. The pulses are applied until the first subset is verified as erased. After the first subset is verified as erased, the first subset is inhibited from further erasing while the second subset is again enabled for erasing.
• One or more additional erase voltage pulses are then applied to the set while the first subset is inhibited and the second subset is enabled. The additional pulses are applied until the second subset is verified as erased.
• a non-volatile memory system includes a set of non-volatile storage elements and managing circuitry in communication with the set of non- volatile storage elements.
• the set includes a first subset and a second subset of non- volatile storage elements.
• the managing circuitry erases the set using a technique that includes applying an erase voltage to the set while each non- volatile storage element in the set is enabled for erase, verifying whether the first subset is erased while excluding the second subset from verification, and repeating the applying and verifying until the first subset is verified as erased.
• the managing circuitry inhibits erasing of the first subset and enables erasing of the second subset.
• the managing circuitry then applies an erase voltage to the set while the second subset is enabled for erase and the first subset is inhibited from erase, and verifies whether the set of non-volatile storage elements is erased by verifying whether the second subset is erased.
• a method of soft programming non-volatile memory comprises applying one or more soft programming pulses to a set of non- volatile storage elements until the set is verified as soft programmed. After verifying the set as soft programmed, a first subset of the set of non- volatile storage elements is inhibited from soft programming and one or more additional soft programming pulses are applied to a second subset of the set of non-volatile storage elements while inhibiting soft programming of the first subset. In one embodiment, the soft programming is performed subsequent to erasing as described above.
• a non-volatile memory system includes a set of non-volatile storage elements and managing circuitry in communication with the set of non-volatile storage elements.
• the set includes a first subset of non- volatile storage elements and a second subset of non-volatile storage elements.
• the managing circuitry soft- programs the set of non-volatile storage elements by applying a soft programming voltage to each non-volatile storage element in the set and verifying whether the set is soft programmed.
• the managing circuitry repeats the applying and verifying until the set of non-volatile storage elements is verified as soft programmed.
• the managing circuitry After verifying that the set is soft programmed, the managing circuitry applies the soft programming voltage to each nonvolatile storage element in the first subset of non- volatile storage elements and verifies whether the first subset of non-volatile storage elements is soft programmed while excluding the second subset from verification.
• Figure 1 is a top view of a NAND string.
• Figure 2 is an equivalent circuit diagram of the NAND string depicted in Figure 1.
• Figure 3 is a circuit diagram depicting three NAND strings.
• Figure 4 is a block diagram of one embodiment of a non-volatile memory system in which the various aspects of the present invention can be implemented.
• Figure 5 illustrates an exemplary organization of a memory array.
• Figure 6 depicts an exemplary program/verify voltage signal that can be applied to a selected word line in accordance with embodiments.
• Figure 7 is an exemplary flowchart for performing a program operation.
• Figure 8 depicts exemplary threshold distributions of a group of memory cells.
• Figure 9 depicts exemplary threshold distributions of a group of memory cells storing two bits of data.
• Figure 10 is a table depicting exemplary bias conditions for performing an erase operation according to prior art techniques.
• Figure 11 is a graph depicting voltages at various portions of a NAND string during an ideal erase operation.
• Figure 12 is a cross sectional view of a NAND string depicting various capacitively coupled voltages within the NAND string.
• Figure 13 is a graph depicting various voltages of the end memory cells of a NAND string during an erase operation.
• Figures 14A and 14B depict exemplary individual threshold voltage distributions for the end and interior memory cells of a NAND string after completing an erase operation.
• Figure 15 is a flowchart for erasing a set of non- volatile storage elements in accordance with one embodiment.
• Figure 16 is a table depicting bias conditions for erasing and verifying erasure of a set of non-volatile storage elements according to one embodiment.
• Figures 17A-17C depict the threshold voltage distributions of the end memory cells and interior memory cells of a NAND string at various points during an erase operation according to one embodiment.
• Figures 18A-18B are graphs depicting erase voltage signals in accordance with one embodiment.
• Figure 19 is a flowchart for performing step 456 of Figure 15 in accordance with one embodiment.
• Figure 20 depicts exemplary threshold voltage distributions of the end memory cells and interior memory cells of a NAND string after soft programming according to the prior art.
• Figure 21 is a flowchart for soft programming a set of non- volatile storage elements in accordance with one embodiment.
• Figure 22 is a table depicting bias conditions for soft programming and verifying soft programming of a set of non-volatile storage elements according to one embodiment.
• Figure 23 depicts exemplary threshold voltage distributions of the end memory cells and interior memory cells of a NAND string after soft programming according to one embodiment.
• Figure 4 is a block diagram of one embodiment of a flash memory system that can be used to implement one or more embodiments of the present disclosure. Other systems and implementations can be used.
• Memory cell array 302 is controlled by column control circuit 304, row control circuit 306, c- source control circuit 310 and p-well control circuit 308.
• Column control circuit 304 is connected to the bit lines of memory cell array 302 for reading data stored in the memory cells, for determining a state of the memory cells during a program operation, and for controlling potential levels of the bit lines to promote or inhibit programming and erasing.
• Row control circuit 306 is connected to the word lines to select one of the word lines, to apply read voltages, to apply program voltages combined with the bit line potential levels controlled by column control circuit 304, and to apply an erase voltage.
• C- source control circuit 310 controls a common source line (labeled as "C-source” in Fig. 6) connected to the memory cells.
• P-well control circuit 308 controls the p-well voltage.
• the data stored in the memory cells are read out by the column control circuit 304 and are output to external I/O lines via data input/output buffer 312.
• Program data to be stored in the memory cells are input to the data input/output buffer 312 via the external I/O lines, and transferred to the column control circuit 304.
• the external I/O lines are connected to controller 318.
• Command data for controlling the flash memory device is input to controller 318.
• the command data informs the flash memory of what operation is requested.
• the input command is transferred to state machine 316 which is part of control circuitry 315.
• State machine 316 controls column control circuit 304, row control circuit 306, c-source control 310, p-well control circuit 308 and data input/output buffer 312.
• State machine 316 can also output status data of the flash memory such as READY/BUSY or PASS/FAIL.
• Controller 318 is connected to or connectable with a host system such as a personal computer, a digital camera, or personal digital assistant, etc. It communicates with the host that initiates commands, such as to store or read data to or from the memory array 302, and provides or receives such data. Controller 318 converts such commands into command signals that can be interpreted and executed by command circuits 314 which are part of control circuitry 315. Command circuits 314 are in communication with state machine 316. Controller 318 typically contains buffer memory for the user data being written to or read from the memory array.
• One exemplary memory system comprises one integrated circuit that includes controller 318, and one or more integrated circuit chips that each contain a memory array and associated control, input/output and state machine circuits.
• the memory system may be embedded as part of the host system, or may be included in a memory card (or other package) that is removably inserted into the host systems.
• a memory card may include the entire memory system (e.g. including the controller) or just the memory array (s) with associated peripheral circuits (with the controller or control function being embedded in the host).
• the controller can be embedded in the host or included within the removable memory system.
• a NAND flash EEPROM is described that is partitioned into 1,024 blocks.
• the data stored in each block can be simultaneously erased.
• the block is the minimum unit of cells that are simultaneously erased.
• Each block is typically divided into a number of pages which can be a unit of programming. Other units of data for programming are also possible and contemplated.
• individual pages may be divided into segments and the segments may contain the fewest number of cells that are written at one time as a basic programming operation.
• One or more pages of data are typically stored in one row of memory cells.
• each block of the example in Figure 5 there are 8,512 columns that are divided into even columns and odd columns.
• the bit lines are divided into even bit lines (BLe) and odd bit lines (BLo).
• bit lines are divided into even bit lines (BLe) and odd bit lines (BLo).
• BLe even bit lines
• BLo odd bit lines
• FIG 5 shows four memory cells connected in series to form a NAND string. Although four cells are shown to be included in each NAND string, more or less than four can be used (e.g., 16, 32, or another number).
• One terminal of the NAND string is connected to a corresponding bit line via a first select transistor or gate (connected to select gate dram line SGD), and another terminal is connected to c-source via a second select transistor (connected to select gate source line SGS).
• bit lines are not divided into odd and even bit lines.
• Such architectures are commonly referred to as all bit line architectures.
• all bit lines of a block are simultaneously selected during read and program operations. Memory cells along a common word line and connected to any bit line are programmed at the same time.
• the select gates of a selected block are raised to one or more select voltages and the unselected word lines (e.g., WLO, WLl and WL3) of the selected block are raised to a read pass voltage (e.g. 4.5 volts) to make the transistors operate as pass gates.
• the selected word line of the selected block (e.g., WL2) is connected to a reference voltage, a level of which is specified for each read and verify operation in order to determine whether a threshold voltage of the concerned memory cell is above or below such level. For example, in a read operation of a one bit memory cell, the selected word line WL2 is grounded, so that it is detected whether the threshold voltage is higher than OV.
• the selected word line WL2 is connected to 0.8V, for example, so that as programming progresses it is verified whether or not the threshold voltage has reached 0.8V.
• the source and p-well are at zero volts during read and verify.
• the selected bit lines (BLe) are pre-charged to a level of, for example, 0.7V. If the threshold voltage is higher than the read or verify level, the potential level of the concerned bit line (BLe) maintains the high level, because of the associated non-conductive memory cell. On the other hand, if the threshold voltage is lower than the read or verify level, the potential level of the concerned bit line (BLe) decreases to a low level, for example less than 0.5V, because of the conductive memory cell.
• the state of the memory cell is detected by a sense amplifier that is connected to the bit line and senses the resulting bit line voltage.
• the difference between whether the memory cell is programmed or erased depends on whether or not net negative charge is stored in the floating gate. For example, if negative charge is stored in the floating gate, the threshold voltage becomes higher and the transistor can be in enhancement mode of operation.
• the drain and the p-well receive 0 volts while the control gate receives a series of programming pulses with increasing magnitudes.
• the magnitudes of the pulses in the series range from 12 volts to 24 volts.
• the range of pulses in the series can be different, for example, having a starting level of higher than 12 volts.
• verify operations are carried out in the periods between the programming pulses. That is, the programming level of each cell of a group of cells being programmed in parallel is read between each programming pulse to determine whether or not it has reached or exceeded a verify level to which it is being programmed.
• One means of verifying the programming is to test conduction at a specific compare point.
• the cells that are verified to be sufficiently programmed are locked out, for example in NAND cells, by raising the bit line voltage from 0 to VDD (e.g., 2.5 volts) for all subsequent programming pulses to terminate the programming process for those cells.
• VDD e.g. 2.5 volts
• the number of pulses will be limited (e.g. 20 pulses) and if a given memory cell is not sufficiently programmed by the last pulse, an error is assumed.
• memory cells are erased (in blocks or other units) prior to programming.
• Figure 6 depicts a program voltage signal in accordance with one embodiment.
• This signal has a set of pulses with increasing magnitudes. The magnitude of the pulses is increased with each pulse by a predetermined step size. In one embodiment that includes the memory cells storing multiple bits of data, an exemplary step size is 0.2 volts (or 0.4 volts). Between each of the program pulses are the verify pulses.
• the signal of Figure 6 assumes a four state memory cell, therefore, it includes three verify pulses. For example, between programming pulses 330 and 332 are three sequential verify pulses.
• the first verify pulse 334 is depicted at a zero volt verify voltage level.
• the second verify pulse 336 follows the first verify pulse at the second verify voltage level.
• the third verify pulse 338 follows the second verify pulse 336 at the third verify voltage level.
• a multi-state memory cell capable of storing data in eight states may need to perform verify operations at seven compare points.
• seven verify pulses are applied in sequence to perform seven verify operations at seven verify levels between two consecutive programming pulses. Based on the seven verify operations, the system can determine the state of the memory cells.
• One means for reducing the time burden of verifying is to use a more efficient verify process, for example, as disclosed in: U.S. Patent Application Serial No. 10/314,055, entitled “Smart Verify for Multi-State Memories," filed December 5, 2002; U.S. Patent Application Serial No. [Attorney Docket No. SAND-105 IUS I] 5 entitled "Method for
• FIG. 7 is a flow chart describing one embodiment of a method for programming non-volatile memory.
• the memory cells to be programmed are erased at step 340.
• Step 340 can include erasing more memory cells than those to be programmed (e.g., in blocks or other units).
• soft programming is performed to narrow the distribution of erased threshold voltages for the erased memory cells. Some memory cells may be in a deeper erased state than necessary as a result of the erase process. Soft programming can apply small programming pulses to move the threshold voltage of the erased memory cells closer to the erase verify level.
• a "data load" command is issued by controller 318 and input to command circuits 314, allowing data to be input to data input/output buffer 312.
• the input data is recognized as a command and latched by state machine 316 via a command latch signal, not illustrated, input to command circuits 314.
• address data designating the page address is input to row controller or decoder 306 from the controller or host.
• the input data is recognized as the page address and latched via state machine 316, affected by the address latch signal input to command circuits 314.
• a page of program data for the addressed page is input to data input/output buffer 312 for programming. For example, 532 bytes of data could be input in one embodiment. That data is latched in the appropriate registers for the selected bit lines. In some embodiments, the data is also latched in a second register for the selected bit lines to be used for verify operations.
• a "program" command is issued by the controller and input to data input/output buffer 312. The command is latched by state machine 316 via the command latch signal input to command circuits 314.
• step 354 the data latched in step 354 will be programmed into the selected memory cells controlled by state machine 316 using the stepped pulses of Figure 6 applied to the appropriate word line.
• Vpgm the programming pulse voltage level applied to the selected word line
• a program counter PC maintained by state machine 316 is initialized at 0.
• step 360 the first Vpgm pulse is applied to the selected word line. If logic "0" is stored in a particular data latch indicating that the corresponding memory cell should be programmed, then the corresponding bit line is grounded. On the other hand, if logic "1" is stored in the particular latch indicating that the corresponding memory cell should remain in its current data state, then the corresponding bit line is connected to VDD to inhibit programming.
• the states of the selected memory cells are verified. If it is detected that the target threshold voltage of a selected cell has reached the appropriate level, then the data stored in the corresponding data latch is changed to a logic "1.” If it is detected that the threshold voltage has not reached the appropriate level, the data stored in the corresponding data latch is not changed. In this manner, a bit line having a logic "1" stored in its corresponding data latch does not need to be programmed. When all of the data latches are storing logic "1,” the state machine knows that all selected cells have been programmed. At step 364, it is checked whether all of the data latches are storing logic "1.” If so, the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of "PASS" is reported at step 366.
• step 364 If, at step 364, it is determined that not all of the data latches are storing logic "I 5 " then the programming process continues.
• the program counter PC is checked against a program limit value.
• a program limit value is 20, however, other values can be used in various implementations. If the program counter PC is not less than 20, then it is determined at step 369 whether the number of bits that have not been successfully programmed is equal to or less than a predetermined number. If the number of unsuccessfully programmed bits is equal to or less than the predetermined number, then the programming process is flagged as passed and a status of pass is reported at step 371. The bits that are not successfully programmed- can be corrected using error correction during the read process.
• step 370 If however, the number of unsuccessfully programmed bits is greater than the predetermined number, the program process is flagged as failed and a status of fail is reported at step 370. If the program counter PC is less than 20, then the Vpgm level is increased by the step size and the program counter PC is incremented at step 372. After step 372, the process loops back to step 360 to apply the next Vpgm pulse.
• the flowchart of Figure 7 depicts a single-pass programming method as can be applied for binary storage.
• a two-pass programming method as can be applied for multi-level storage, for example, multiple programming or verification steps may be used in a single iteration of the flowchart.
• Steps 358-372 may be performed for each pass of the programming operation.
• one or more program pulses may be applied and the results thereof verified to determine if a cell is in the appropriate intermediate state.
• one or more program pulses may be applied and the results thereof verified to determine if the cell is in the appropriate final state.
• the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells.
• Figure 8 illustrates threshold voltage distributions for a memory cell array when each memory cell stores one bit of data.
• Figure 8 shows a first distribution 380 of threshold voltages for erased memory cells and a second distribution 382 of threshold voltages for programmed memory cells.
• the threshold voltage levels in the first distribution 380 are negative and correspond to logic "1" while the threshold voltage levels in the second distribution 382 are positive and correspond to logic "0.”
• Figure 9 illustrates exemplary threshold voltage distributions for a memory cell array when each memory cell stores two bits of data in four physical states.
• Distribution 384 represents a distribution of threshold voltages of cells that are in an erased state (storing "11"), having negative threshold voltage levels.
• Distribution 386 represents a distribution of threshold voltages of cells that are in a first programmed state, storing "10.”
• Distribution 388 represents a distribution of threshold voltages of cells that are in a second programmed state, storing "00.”
• Distribution 390 represents a distribution of threshold voltages of cells that are in a third programmed state, storing "01."
• Each of the two bits stored in a single memory cell, in this example, is from a different logical page. That is, each bit of the two bits stored in each memory cell carries a different logical page address. The bit displayed in the square corresponds to a lower page.
• the bit displayed in the circle corresponds to an upper page.
• the logical states are assigned to the sequential physical states of memory cells using a gray code sequence so that if the threshold voltage of a floating gate erroneously shifts to its nearest neighboring threshold voltage state range, only one bit will be affected.
• Fig. 3 illustrates three memory cells 224, 244 and 252 of a much larger number of cells along one word line WL2.
• One set of altemate cells, including cells 224 and 252 store bits from logical pages 0 and 1 ("even pages"), while another set of alternate cells, including cell 244, store bits from logical pages 2 and 3 ("odd pages").
• Memory cells are erased in one embodiment by raising the p-well to an erase voltage (e.g. 20 volts) and grounding or applying 0 volts to the word lines of a selected block while the source and bit lines are floating.
• Figure 10 depicts exemplary bias conditions for performing an erase operation. Due to capacitive coupling, the unselected word lines (e.g., those in unselected, not to- be-erased blocks), bit lines, select lines, and c-source are also raised to a high positive potential (e.g., 20V). A strong electric field is thus applied to the tunnel oxide layers of memory cells of a selected block and the data of the selected memory cells is erased as electrons of the floating gates are emitted to the substrate.
• an erase voltage e.g. 20 volts
• Erasing refers to lowering the threshold voltage of a memory cell by transferring electrons out of its floating gate. As sufficient electrons are transferred from the floating gate to the p-well region, the threshold voltage of a selected cell becomes negative. Once the threshold voltage reaches a predetermined sufficiently low value, the memory cell can be regarded as erased and the erase process deemed completed or successful. Thus, erasing a memory cell refers to lowering the threshold voltage of a memory cell and does not imply complete or successful erasing thereof. Erasing can be performed on the entire memory array, one or more blocks of the array, or another unit of cells.
• the erase voltage signal V era se is typically applied as a series of erase voltage pulses, with an erase verification operation being carried out in between each pulse.
• another erase voltage pulse can be applied to the p- well region.
• the peak value of the erase voltage is increased for each subsequent pulse (e.g., in IV increments from 16V to 20V).
• Figure 11 is a graph depicting the voltage at various portions of a NAND string during application of a single erase voltage pulse for a typical erase operation (e.g., under the bias condition of Figure 10).
• the example of Figure 11 illustrates an ideal case, ignoring inter-gate capacitive charge coupling as discussed below.
• Curve 410 depicts the voltage of the p-well region which receives erase voltage signal V erase - The erase voltage pulse causes the p- well to ramp up to 20V and then back to OV.
• Curves 414 and 412 depict the control gate voltage and floating gate voltage of a memory cell of the string. Before the erase voltage pulse is applied, the floating gate voltage depends on the programmed state of the memory cell and is typically lower than OV.
• a value of -IV is assumed for the floating gate voltage before the first erase voltage pulse.
• the control gate voltage 414 remains at OV throughout the erase operation while the floating gate voltage 412 rises in proportion to the p- well voltage.
• the floating gate is capacitively coupled across the tunnel dielectric region to the p-well.
• the capacitive coupling ratio between the floating gate of a memory cell and the p- well region is about 40-50%. Accordingly, floating gate voltage 412 rises in about a 0.5:1 ratio (when the coupling ratio is 50%) with the p-well voltage to a voltage of about 9V.
• the resulting erase potential the potential between the cell's floating gate and the p-well region, is given below the graph of Figure 11.
• V erase 20V
• the erase potential changes during the actual erase voltage pulse as electrons are transferred from the floating gate to the p- well.
• the floating gate voltage will be different than before the erase voltage pulse was applied.
• the floating gate voltage will be positive after the first erase voltage pulse, corresponding to a negative (erased) threshold voltage of the memory cell.
• Figure 12 provides a cross-sectional view of a NAND string including 8 memory cells. Although embodiments are presented with respect to Figure 12 and an 8 cell NAND structure, the present invention is not so limited and can be used in accordance with numerous NAND structures including fewer or more than 8 memory cells (e.g., 4, 12, 16, or more). As depicted in Figure 12, the memory cells of the NAND string are formed in p-well region 540.
• Each memory cell (502, 504, 506, 508, 510, 512, 514, and 516) includes a stacked gate structure that consists of the control gate (502c, 504c, 506c, 508c, 510c, 512c, 514c, and 516c) and a floating gate (502f, 504f, 506f, 510f, 512f, 514f, and 516f).
• the floating gates are formed on the surface of the p-well on top of an oxide or other dielectric composite film.
• the control gate is above the floating gate, with an oxide or other isolating dielectric layer separating the control gate and floating gate.
• the control gates of the memory cells connect to or form word lines WLO, WLl, WL2, WL3, WL4, WL5, WL6, and WL7.
• N+ diffused regions 542 are shared between neighboring cells whereby the cells are connected to one another in series to form a NAND string. These N+ diffused regions form the source and drain of each of the cells.
• N+ diffused region 526 connects to the bit line for the NAND string, while N+ diffused region 528 connects to a common source line for multiple NAND strings.
• the select gates 520 and 522 are formed of the same structure as the memory cells, however, the gate regions are electrically connected.
• the floating select gates 522 and 520 are raised to a high positive potential when a high erase voltage is applied to the p-well during erase operations.
• the erase voltage applied to the p-well, or some portion thereof couples from the well region to each of the select gates.
• About 90-100% of the p-well voltage can be expected to couple to each select gate in many NAND structures. Therefore, if an erase voltage pulse of 20V is applied to the p-well, the voltage on each select gate will rise about 18V-20V to a voltage of 18V-20V.
• the coupling from p-well 540 to select gates 522 and 520 is illustrated by arrows 530.
• each floating gate is also coupled to its corresponding control gate with a coupling of about 50-60%. To a smaller extent, each floating gate is coupled to neighboring floating gates and control gates. All the different couplings add up to a total of 100%. Assuming a 50% coupling from p-well to floating gate, the floating gate voltage of each memory cell is raised about 10V under application of a 20V erase voltage pulse. This coupling effect is illustrated by arrows 532. The voltage coupled to each memory cell's floating gate effects the V erase potential created across the tunnel oxide layer. For example, an erase potential of about 11V (20V-9V) is created under application of a 20V erase voltage pulse to the p-well for a memory cell having a floating gate voltage of -IV prior to erasing.
• Each memory cell of the string will experience some capacitive charge coupling from neighboring memory cells and/or transistors. This coupling can effect the potential of a cell's floating gate and consequently, the erase potential for the cell.
• the end memory cells (e.g., memory cells 502 and 516 in Figure 12) of the NAND string - those connected to the first and last word lines (end word lines) of the NAND string and adjacent to the select gates of the NAND string - will experience capacitive charge coupling from the neighboring select gates.
• this capacitive coupling is depicted by arrow 534 from select gate 520 to floating gate 502f of memory cell 520 and by arrow 538 from select gate 522 to floating gate 516f of memory cell 516.
• the voltage coupled to memory cells 502 and 516 will decrease the electric field present across those cells' tunnel dielectric regions (e.g., tunnel oxide) in proportion to the amount of voltage at the respective select gate.
• the coupling represented by arrows 538 and 534 occurs in both directions because during an erase operation, the select gates are in a floating state as well. As a result, the floating gate voltage of memory cells 516 and 502 will have some influence on the voltage on the select gates 522 and 520. However, the coupling from floating gate to select gate is much smaller than the coupling from the p-well to the select gates, and thus, the select gate voltage is determined almost completely by the p-well voltage.
• capacitive coupling from the select gates to the floating gates of the end memory cells of a NAND string can be expected to be on the order of about 2% to 5%. If an erase voltage of 20 volts is applied to the p-well region, each select gate's voltage will rise about 18V with 90% p-well to select gate coupling. Subsequently due to the 2-5% coupling from select gate to neighboring floating gate, the voltage on the neighboring floating gates (e.g., 516f and 502f) will rise about 0.4-1 V. The resulting voltage across the tunnel oxide of the end memory cells of the string will be about 0.4 to IV less than that for the ideal case shown in Figure 11.
• the above mentioned capacitive coupling can vary largely depending on the physical dimensions of the memory cells and select gates, the spacing between memory cells and select gates, and the dielectric properties of the materials used in constructing such components as the tunnel dielectric, dielectric between control and floating gates, and dielectric between select gates and memory cells. In some cases, for example, the above mentioned coupling may be larger or smaller than the above mentioned 2-5% range.
• the floating gate voltage of the end memory cells will be higher than that of the interior memory cells and thus, the erase potential will be lower for the end memory cells as hereinafter described.
• Figure 13 depicts the p-well voltage 420, floating gate voltage 422, and control gate voltage 424 for a typical end memory cell of a NAND string during application of a single erase voltage pulse for an erase operation under the bias conditions of Figure 10.
• the p-well voltage 420 rises from OV to a peak value of 20V and then back to OV.
• the control gate voltage 424 remains at OV since the word lines connected to each memory cell are supplied with OV.
• the floating gates of the end memory cells are capacitively coupled to the p-well region on the order of about 40-50%. As the p-well region voltage increases to 20V, this capacitive coupling causes the floating gate voltage to rise about 10V when 50% coupling is assumed.
• the end memory cells additionally have a portion of the voltage at the neighboring select gate coupled to them.
• the voltage on these floating gates will not only be increased in proportion with the p-well voltage that is capacitively coupled thereto, but will also be increased due to the 2-5% coupling from the select gates.
• the floating gate voltage 422 rises to a maximum value of 10V at the beginning of the erase voltage pulse as opposed to the maximum value of 9V for the ideal case depicted in Figure 11.
• the erase potential across the tunnel dielectric region for the end memory cells is given below the graph of Figure 13.
• the erase potential at the beginning of the erase voltage pulse is about 10 V, or about IV less than the 1 IV erase potential for the ideal case.
• the memory cells of a NAND string that are not adjacent to a select gate may be referred to herein as interior memory cells of the string.
• the interior memory cells of the NAND string are memory cells 504, 506, 508, 510, 512, and 514.
• the interior memory cells will experience capacitive coupling from neighboring floating gates that will decrease their erase potential (discussed hereinafter), it is of a lesser degree than that of the end memory cells.
• the interior memory cells will behave substantially as the ideal case described earlier and have an erase potential of about 11V (assuming that the cells were in a programmed state with a floating gate voltage of about -IV before the erase voltage pulse).
• the end memory cells Because of the lower potential across the tunnel oxide layers of the end memory cells compared to the interior memory cells, the end memory cells will erase slower and not be as deeply erased (will have fewer electrons transferred from their floating gates) as the interior memory cells after application of one or more erase voltage pulses.
• Memory cells of a NAND string are verified as erased when the charge on the floating gate is above a predetermined level (threshold voltage below a predetermined level). Because of the additional coupling to the floating gates of the end memory cells, the overall time for an erase operation is increased in order to sufficiently erase these end memory cells.
• the interior memory cells may be sufficiently erased after application of a number N erase voltage pulses, while the end memory cells of the NAND string may not be sufficiently erased until application of N+l or more erase voltage pulses.
• Figure 12 illustrates an additional capacitive coupling effect between the floating gates of individual memory cells of the NAND string by arrows 536.
• the coupling between neighboring floating gates on WLO and WLl may be on the order of 2-5%, but may be smaller or larger depending on the dimension and shape of the memory cells.
• a voltage present on the floating gate of memory cell 516 will influence the voltage of the floating gate of memory cell 514 and vice versa.
• a similar coupling will be present between the floating gates of memory cells 514 and 512, connected to WL2, and so on. This coupling exists in both directions, as indicated by the double head on arrows 536.
• Figure 14A shows the erased (E) and programmed (A 5 B 5 C) threshold voltage VT distributions of a four state or four level memory device after data has been written into the memory array.
• Figure 14B depicts the same four state memory device after an erase operation has been completed.
• the threshold voltage distributions for the memory cells of the interior word lines and end word lines are depicted separately.
• Distribution 430 shows the threshold voltage distribution for the interior word lines, which are erased deeper than the end word lines, depicted by distribution 432.
• the interior memory cells will be about 0.5-1V deeper erased than the end memory cells because of capacitive charge coupling from the select gates.
• the memory cells of both the interior and end word lines are in general erased deeper than required.
• a fresh memory device may have threshold voltage distributions as shown in Figure 14B after undergoing an erase operation.
• the interior memory cells of a NAND string may be over erased while attempting to sufficiently erase the end memory cells of the string. As previously described, the interior memory cells will erase faster than the end memory cells. If verification is performed at a NAND string level, the NAND string will continue to receive an erase voltage pulse at the p-well until each memory cell of the string is erased. Therefore, even though the interior memory cells may sufficiently erase after a lower number of erase voltage pulses than the end memory cells, the interior memory cells will receive additional erase voltage pulses until each memory cell of the string is verified as erased.
• a greater stress is placed on the interior memory cells than is necessary because of over erasure. Over erasing the interior memory cells because of the slower erase times of the end memory cells can decrease the life span of the interior memory cells and an overall non- volatile memory system. As understood in the art, application of a large potential across the tunnel oxide layer of a transistor stresses the oxide material. Application of a high enough potential across the tunnel oxide layer or application of a lower potential a number of times can eventually lead to a breakdown of the oxide layer.
• Disparate erase behavior between memory cells can also lead to increased erase operation times because of additional operations that may be performed to change the threshold voltage of a memory cell after being erased.
• the goal is that all erased cells have a negative threshold voltage within a predefined range of negative threshold voltages. As illustrated, however, the erase process may result in some cells having negative threshold voltages below the predefined range. Memory cells having a threshold voltage that is too low may not subsequently program properly or may cause other cells to not program properly (e.g., by increasing the probability that program disturb occurs). Thus, over-erased devices will often undergo what is called soft programming.
• Memory cells with threshold voltages of significantly lower values within the predefined range will receive a small amount of programming so that the threshold voltage is raised to be within the predefined range.
• the soft program process requires an additional operation to be performed and decreases memory performance due to increased erase times as soft programming is usually considered part of the erase operation.
• the word lines of a set of memory cells being erased are divided into subsets which are independently verified such that additional erase pulses can be provided to select word lines having slower erasing memory cells. In this manner, faster erasing word lines are not over-erased and the memory cells of all the word lines in the set will have the same (or substantially the same) threshold voltage distributions after an erase operation.
• Figure 15 is a flow chart depicting a method for erasing a set of memory cells in accordance with one embodiment. It will be appreciated by those of ordinary skill in the art that multiple NAND strings can be operated upon in parallel such as to erase a block of memory cells according to the method of Figure 15. Additionally, other units of cells can also be operated upon in accordance with the described embodiments. In one embodiment, erasing according to the flowchart of Figure 15 can be performed for erase step 340 of Figure 7. In one embodiment, erasing according to Figure 15 is performed after controller 318 receives a request from the host to erase or program a set of memory cells.
• the bit, source, source select gate, and drain select gate lines for the NAND string are floated at step 440.
• zero volts (or ground) is applied to each word line of the NAND string.
• Steps 440 and 442 enable erasing of the entire set of memory cells, which can include the NAND string or multiple NAND strings in parallel.
• the erase voltage pulse V erase is applied to the p-well region of the NAND string or strings.
• the memory cells connected to the interior word lines are verified for an erased state. The memory cells connected to the end word lines are excluded from verification so that only the interior memory cells are verified.
• the end word lines can be excluded from verification by applying a voltage to them that is sufficient to turn on a memory cell, whether or not it is erased.
• This voltage can be larger than the erase verify voltage Ey er i f y applied to the interior word lines.
• Numerous voltage levels can be used at step 446. For example, a voltage large enough to turn on a memory cell programmed to the highest state could be used, although a voltage only slightly larger than the erase verify voltage will be sufficient in most embodiments. The important factor is that the memory cells connected to the end word lines be conductive while verifying the interior word lines.
• step 448 it is determined whether each NAND string was successfully verified at step 446 as having its interior memory cells erased. In one embodiment, step 448 and the interior memory cell erase are deemed successful only if every NAND string is successfully verified as having its interior memory cells erased. In another embodiment, step 448 and the interior memory cell erase are deemed successful if only a predetermined number of NAND strings are successfully verified as having their interior memory cells erased. By determining that the interior memory cell erase is successful based on a predetermined number of NAND strings rather than every NAND string, the verification process can stop before the maximum erase loop number is reached (step 450), This can avoid over-erasing NAND strings due to one or a small number of difficult to erase or defective NAND strings.
• step 450 a verify counter VC is checked against an erase limit value.
• the verify counter is used to limit the number of iterations of the erase cycle.
• One example of an erase limit is 8, however, other values can be used. If the verify counter is less than the erase limit value, then VC is incremented by 1 and the value of the erase voltage pulse V erase is stepped up by a first step size or increment value ⁇ VERAI- In one embodiment, ⁇ VERAI is about 0.5V to IV.
• the first erase voltage pulse applied at step 444 is chosen in one embodiment to have an amplitude such that, both before and after write erase cycling, the cells connected to the interior word lines are just erased, without being over-erased, after application of the first pulse.
• the interior memory cells can be erased in one pulse such that for the majority of the time, the interior word lines will be verified after just one iteration of steps 440 through 446.
• ⁇ VERAI can be a relatively small value in order to just erase the interior memory cells in those instances where a further iteration is needed (e.g., after many write erase cycles). More details regarding the various step sizes that can be used in accordance with embodiments will be discussed with Figures 18A and 18B.
• step 452 the number of non- verified NAND strings is compared with a pre-determined number. If the number that is non- verified is less than or equal to the pre-determined number, then the method proceeds to step 458. If the number of non- verified strings is not less than the pre-determined number, then a status of fail is reported for the operation at step 454. Step 452 is optional. For example, in embodiments where step 448 is deemed successful based on less than all of the NAND strings, step 448 may be omitted.
• the memory cells of the interior word lines have been verified as erased. Additionally, all of the memory cells connected to all the word lines of the set being erased have had their floating gate charges increased (charge increased as electrons removed) as a result of steps 440 through 446. However, the end memory cells have not yet been verified as in an erased state. As previously described, these end memory cells erase slower than the interior memory cells. Thus, having confirmed that the faster memory cells are now erased, attention can be directed to the end memory cells to provide additional erasing therefore. In this manner, the interior and end memory cells of a set of memory cells will be erased to about the same level after completion of the erase operation.
• the verify counter VC is reset to zero. Additionally, the erase voltage V era se is stepped up by a second increment size of ⁇ VERA 2 - ⁇ VERA. can be larger than ⁇ VERAI- In one embodiment, ⁇ VERA2 can be about IV to 2V. ⁇ V E R A2 is preferably chosen such that after application of a single erase voltage pulse at the increased level, the end memory cells will be erased both before and after write/erase cycling.
• the bit, source, source select gate, and drain select gate lines are again floated.
• the interior word lines are inhibited from further erasing and the end word lines are enabled for further erasing.
• the interior memory cells can be inhibited from erasing during subsequent erase voltage pulses by floating the interior word lines.
• the end memory cells can be enabled for erasing by applying OV to the end word lines. Afiter setting up this condition, the first erase voltage pulse at the increased level is applied to the set of memory cells.
• the end word lines are verified for an erased state while excluding the interior word lines from verification. Again, as in step 446, this can be accomplished by applying the erase verify voltage to the end word lines, while applying a voltage sufficient to turn on the memory cells of the interior word lines, regardless of their state, to the interior word lines. This voltage applied to the interior word lines will be larger than the erase verify voltage applied to the end word lines.
• the entire NAND string can be verified at step 466 for an erased state.
• the interior memory cells have already been verified as erased and thus, they should be conductive under application of the erase verify voltage. Therefore, each memory cell of the string can be verified at step 466 in this alternative embodiment. However, it may be preferred to apply a larger voltage to the interior memory cells in order that verification can just be performed on the end word lines which have not yet been verified.
• step 468 it is determined whether each NAND string was successfully verified as having its end memory cells erased. Like step 448, a successful determination at step 468 can be made when all or only a predetermined number of NAND strings are successfully verified. If all or a predetermined number of NAND strings are successfully verified, a status of pass is reported at step 470. If all or the predetermined number are not successfully verified, the verify counter is checked against the erase limit value at step 472. If the verify counter is less than the limit, the method proceeds to step 474, where the verify counter is incremented by one and the erase voltage Verase is stepped up by a third increment step size of ⁇ VE R A 3 -
• ⁇ VERA 3 is the same value as ⁇ VERAI- In other embodiments, ⁇ VERA3 is larger than ⁇ VERAI since the end memory cells are slower to erase and may benefit from a larger increment value to speed up their erase.
• the result of step 458 and 474 is that the erase voltage pulse is increased by a large amount after verifying the interior word lines for a first application of the erase voltage to the end memory cells. It is then increased by a smaller amount thereafter at step 474 if multiple iterations are required in order to fully erase the end memory cells. Again, more details and alternatives for the increment values will be discussed hereinafter. If the verify counter is not less than 8, then the number of non-verified NAND strings is compared with a predetermined number at step 476.
• step 476 is optional. If the number of non- verified strings is less than the predetermined number, then a status of pass is reported at step 470. If however, the number of non-verified NAND strings is greater than the predetermined number, then a status of fail is reported at step 454.
• Figure 16 is a table showing the bias conditions for the various sub operations performed as part of the erase operation of Figure 15.
• Column 480 sets forth the bias conditions for erasing the memory cells of all the word lines of the set of word lines being erased.
• Column 480 corresponds to steps 440 through 444 of Figure 15. In these steps all the memory cells of each word line have the charge at their floating gate increased by transferring electrons therefrom.
• the bit and source lines are floating as well as the source and drain select gate lines.
• Each word line is supplied with OV in order to enable erasing thereof.
• the p-well receives the erase voltage and electrons are transferred from the floating gates of each memory cell of the set by virtue of the potential created by applying OV to the word lines and V erase to the p-well.
• Column 482 sets forth the bias conditions for verifying just the interior word lines for an erased state. Column 482 corresponds to step 446 of Figure 15.
• the bit line is floating while the source line is at VDD-
• the drain select gate and source select gate lines are supplied with a positive voltage V SG sufficient to turn on both select gates.
• V S G is typically larger than VDD-
• V SG can be about 4-4.5V in one embodiment.
• the interior word lines are provided with the erase verify voltage (e.g., OV) for the operation.
• Word line WL 0 and word line WL n are provided with a voltage V usel .
• V usel can be a range of voltages as previously described, but is typically chosen so as to ensure conduction of the memory cells connected at word lines WL 0 and WL n .
• V use i could be a larger voltage than any of the potential voltages of a programmed memory cell.
• V use i as the voltage applied to word line WL 0 and word line WL n , the end memory cells are excluded from the interior word line verification operation at step 446.
• the bias conditions of column 482 are applied to a NAND string and the bit line voltage is sensed; If the interior memory cells are erased sufficiently deep, they will be in the on state and provide a conduction path from the source line to the bit line. A current will be induced through the NAND string and the bit line voltage will increase. After a predetermined amount of time the bit line voltage is sensed or checked by a sense amplifier. If the bit line voltage has reached a predetermined level, the interior memory cells are verified as erased. If the interior memory cells are not erased sufficiently deep, they will not be in the on state and therefore, will not conduct any current or will conduct too little current. As a result, the bit line voltage will not increase up to the predetermined level. When the bit line voltage is sensed after the predetermined amount of time, it will not have reached the predetermined level and the interior memory cells will not be verified as erased.
• Column 484 sets forth the bias conditions for erasing only the memory cells connected to the end word lines of the set being erased. Column 484 corresponds to steps 460 through 464 of Figure 15. As with erasing all the word lines, the bit line, source line, source select gate line, and drain select gate line are all floating. Additionally, the p-well will be supplied with the erase voltage V erase - To inhibit further erasing of the memory cells of the interior word lines (which have already been verified as erased), the interior word lines are floated while the end word lines are provided with OV. In this manner, the interior word lines will couple to the p-well and create no erase potential across the tunnel dielectric region of the memory cells connected thereto. However, by supplying OV to the end word lines, those memory cells will be enabled for erasing. Thus, just the memory cells of the end word lines are erased when the erase voltage pulse is applied to the p-well.
• Column 486 sets forth the bias conditions for verifying the erased state of just the end word lines. Column 486 corresponds to step 466 of Figure 15. As with the interior word line verification operation of column 482, the bit line is floating while the source line is at V D D- The p-well is grounded and the drain select gate and source select gate are turned on by voltage V SG . In order to verify the end word lines while excluding the interior word lines from verification, the erase verify voltage Ey er ify (e.g., OV) is applied to word lines WL 0 and WL n , while V usel is provided to the interior word lines. V US ei will ensure conduction of the memory cells of the interior word lines such that the erased state of just the end word lines can be tested.
• Ey er ify e.g., OV
• the end memory cells If the end memory cells are sufficiently erased, they will turn on under application of the Ey er i f y voltage.
• the bit line voltage will increase up to or beyond a predetermined level which indicates the end memory cells are erased. If the end memory cells are not sufficiently erased, they will remain off or at least not sufficiently turned on under application of the Ey e ⁇ f y voltage. The bit line voltage will not increase up to the predetermined level which indicates that the end memory cells are not yet erased.
• the entire NAND string can be optionally verified since the interior memory cells have previously been verified at step 446.
• the erase verify voltage could be applied to the interior word lines for the end word line verification since they should conduct under the erase verify voltage. However, it may be beneficial to supply V usel to ensure conduction in order to only test for an erased state of the end memory cells.
• Figure 17A through 17C depict the improved erase threshold voltage distributions of a set of memory cells erased according to embodiments.
• Figure 17A shows the erased and programmed threshold voltage distributions for a four level NAND memory device after data has been written into the memory array.
• Figure 17B shows the erased threshold voltage distributions for the memory cells of the device after completion of application of a single erase voltage pulse.
• Figure 17B can correspond to the time at which step 444 of Figure 15 has been completed according to the bias conditions of Figure 16, column 480.
• Figure 17B can correspond to the time at which step 444 of Figure 15 has been completed according to the bias conditions of Figure 16, column 480.
• FIG. 17B shows after application of the first erase voltage pulse only the memory cells of the interior word lines (shown in distribution 430) will be sufficiently erased.
• Figure 17C shows the erased threshold distributions for the subsets of memory cells after additional erase pulses have been applied only to the end word lines of the set being erased.
• Figure 17C can correspond to the time after completion of step 464 in Figure 15. This could be after one additional erase pulse has been applied to the end word lines, or after multiple erase pulses have been applied through multiple iterations of steps 460 - 474.
• the two most end word lines of a NAND string can be grouped together as the end word lines and the remaining word lines (WL2 - WL n-2 ) grouped together as the interior word lines.
• step 446 of Figure 15 will include verifying word lines WL2 - WL n-2 and steps 462 and 466 will be performed to further erase and verify word lines WLO, WLl, WL n-I , and WL n .
• six or more word lines could be grouped together as the end word lines. Other groupings can also be implemented.
• Figures 18A and 18B depict erase voltage signals that can be used in accordance with various embodiments.
• Figure 18A shows a first erase voltage pulse, pulse 1; having a magnitude of V era sei-
• the first pulse can be the first pulse applied to the set of memory cells being erased at step 444 of Figure 15. This pulse is used to erase all memory cells of the set.
• the first value of the erase pulse can be about 15V to 20V.
• the magnitude of the first erase pulse be chosen in such a way that both before and after write/erase cycling, the cells on the interior word lines will be just erased (and without being over-erased) after application of the single erase voltage pulse.
• the first erase voltage pulse may be chosen such that only before write/erase cycling or only during a limited number of write/erase cycles, the interior memory cells will be erased after application of the first pulse. After extended write/erase cycling, more pulses may be needed. This technique can reduce the over erase at the beginning of write/erase cycling at the expense of more erase voltage pulses after extended write/erase cycling.
• a second pulse, pulse 2j is applied before the interior word lines are successfully verified as erased.
• the erase voltage signal is increased by a step size of ⁇ V ER AI from puls ⁇ i to pulse 2 .
• the increase by ⁇ VERAI corresponds to step 456 of Figure 15.
• ⁇ VE R AI can be about 0.5V to IV in one embodiment.
• After application of the second erase voltage pulse all of the interior word lines are successfully verified. This can correspond to step 448 of Figure 15. After all the interior word lines are verified, erasing only continues for the end memory cells. These memory cells erase slower, thus the erase voltage signal is increased by a second larger increment step size of ⁇ V ER A 2 for application of the third erase voltage pulse, pulse 3 .
• ⁇ VERA 2 be chosen such that after application of the first erase voltage pulse (e.g., pulse 3 ) to just the end memory cells, all of the end memory cells will be erased, both before and after write erase cycling. In one embodiment, ⁇ VERA 2 is about 2 volts.
• Application of pulse 3 corresponds to step 464 of Figure 15. The pulses are increased by a third step size ⁇ VE R A 3 thereafter. This corresponds to step 474 of Figure 15.
• ⁇ V ER A 3 can be equal to ⁇ V ER AI in one embodiment, or can be larger or smaller in other embodiments.
• Figure 18B depicts an alternate embodiment of the erase voltage signal that can be used when performing the method of Figure 15.
• the first erase voltage pulse is chosen to be larger than the second pulse.
• the first erase voltage pulse, pulse l5 is chosen to induce a large voltage shift (for example, about 6V).
• This erase voltage pulse is still ideally chosen such that the interior memory cells will be erased after application of the single pulse, both before and after a certain number of write/erase cycles. However, it recognizes that it may take more than one pulse to erase all the interior memory cells in some instances.
• the first erase voltage pulse may be chosen such that only before write/erase cycling or only during a limited number of write/erase cycles, the interior memory cells will be erased after application of the first erase voltage pulse.
• a second erase voltage pulse, puls ⁇ 2 is smaller by a step size of ⁇ V E RA4 than pulsei.
• the decrementation of the erase voltage signal also corresponds to step 456 of Figure 15.
• it is decreased in size by ⁇ VERA ⁇ This ensures that the interior memory cells are not over-erased after application of the second erase voltage pulse.
• the second pulse is made smaller to induce a smaller shift in the threshold voltage of the memory cells. If a third erase voltage pulse is needed, such as shown by pulse 3 , it can then be increased by a step size of ⁇ VE R AI to ensure that electrons continue to be transferred from the floating gates of those memory cells.
• the interior memory cells are verified as erased.
• the remainder of Figure 18B is the same as in Figure 18 A.
• the first erase voltage pulse, pulse 4 that is applied to just the end memory cells, is increased from the previous erase voltage pulse size by a magnitude of ⁇ V ER A 2 - This corresponds to step 458 of Figure 15.
• an additional erase voltage pulse is needed to erase the end memory cells.
• the fifth erase voltage pulse, pulse 5 is increased by a value of ⁇ VE RA3 over the fourth erase voltage pulse value.
• the second erase voltage pulse, pulse ⁇ can be the same size of pulsei rather than decreasing in size. In such an embodiment, any erase voltage pulses thereafter needed to erase the interior memory cells will be increased by a value of ⁇ VERAI as shown.
• FIG 19 is a flow chart depicting a method in accordance with one embodiment for performing step 456 of Figure 15.
• step 456 is performed as shown by the erase voltage pulse of Figure 18B.
• step 450 of Figure 15 a determination is first made at step 490 whether the verify counter VC is equal to zero, indicating that only one erase voltage pulse has been applied to the set of memory cells thus far. If the verify counter is equal to zero, indicating that this is the first change to the size of the erase voltage pulse, then the method proceeds to step 492, where the erase voltage pulse size is stepped down by the value ⁇ V ERA ⁇ This will result in a pulse like puls ⁇ 2 being applied during the next iteration.
• step 494 the erase voltage signal is stepped up by ⁇ VERAI J resulting in a pulse like pulse 3 of Figure 18B. From steps 492 and 494, the method again proceeds to step 440 of Figure 15.
• Capacitive coupling can also lead to disparate behavior amongst memory cells of a NAND string during so-called soft programming operations.
• a soft programming operation is typically carried out by applying soft programming pulses to all the word lines of a selected block at the same time.
• Soft programming is performed after erasing a set of memory cells. The soft programming is performed to narrow the width of the erased threshold distribution for the set of memory cells and also to normalize the erased threshold distribution of the individual memory cells within the set.
• Soft programming pulses are lower in amplitude than regular programming pulses (e.g., as shown in Figure 6) to avoid that the cells reach a programmed state. What is desired as a result of the soft programming is that the cells have a narrower erase threshold voltage distribution. Consequently, the threshold voltages are not intended to be shifted into a programmed state range.
• Figure 20 shows the erased threshold voltage distribution for the memory cells of a NAND string after undergoing soft programming.
• Distribution 430 depicts the erased threshold distribution of the interior word line memory cells after undergoing soft programming.
• Soft programming has shifted this erased threshold voltage distribution closer to the erase verify level. Since the verification for soft programming verifies a group of cells as successfully soft programmed when a predetermined number of NAND strings are non-conductive under application of the erase verify voltage, a certain number of cells will have their threshold voltage shifted beyond the erase verify level. The actual number having a threshold voltage higher than the erase verify level will depend upon the actual verification scheme employed. For example, if the scheme verified soft programming as complete when a single string becomes non-conductive, only one cell in the group may be higher than the verify level.
• the word lines of a set of memory cells are again divided into subsets such that soft programming can be carried out in a way adapted to the needs of the individual subsets of word lines.
• the method is similar to the erase verification method depicted in Figure 15. AU of the word lines of the set that are being soft programmed undergo some initial soft programming. After verifying that the set of memory cells or a subset thereof has been successfully soft programmed, additional soft programming can be performed for just the end word lines in order to move them out of their deeper erased state and closer to the erased verify level.
• Figure 21 depicts a method for soft programming in one embodiment.
• the method of Figure 21 could be used to soft- program a plurality of NAND strings of a block of memory cells.
• soft programming according to Figure 21 can be performed for soft programming step 342 of Figure 7.
• the soft programming voltage signal V S P G M is set to its initial value and the soft programming counter SPC is set to zero.
• the source, bit, and source select gate lines are grounded at step 604.
• V SG is applied to the drain select gate line.
• the drain select gate line voltage may be lowered to about 2.5V just before applying the soft programming pulse to allow boosting for soft programming inhibition (step 617) if needed. In other instances it is not.
• Soft programming inhibition can still occur to a certain extent by the channel which will be biased to VDD (step 617).
• the first soft programming pulse is applied to all the word lines of the set being soft programmed.
• the memory cells of all the word lines are verified for an erased state using the erase verify voltage level.
• step 608 can include verifying only the memory cells of the interior word lines while ensuring conduction of the end memory cells. However, the memory cells of the end word lines will conduct in most instances anyway under application of the erase verify voltage as they are slower to soft- program than the memory cells of the interior word lines. [00117]
• the number of non-conducting NAND strings in the block being soft programmed is compared to a predetermined number.
• the soft programming counter SPC is compared against a predetermined limit value (for example 20) at step 612. If the soft programming counter is not less than 20, then a status of fail is reported at step 614 for the soft programming operation. If the soft programming counter is less than 20, the method proceeds to step 616, where the soft programming counter SPC is incremented by 1 and the soft programming voltage signal is stepped up by a predetermined value. At step 617, the NAND strings that were non-conductive (successfully soft programmed) during the verification at step 608 are inhibited from further soft programming.
• a predetermined limit value for example 20
• Soft programming in a particular NAND string can be inhibited by applying a higher voltage such as V DD to the corresponding bit line.
• V DD voltage
• the channel area of the inhibited NAND string will be boosted to a high voltage during the next soft programming cycle.
• the voltage difference between the floating gates of the memory cells and channel area of the inhibited NAND string will be too low to cause further soft programming of the cells.
• the method then proceeds to step 604 to apply an additional soft programming pulse to the set of memory cells.
• step 618 can further include increasing the soft programming voltage signal.
• the increase at step 618 can be the same as in step 616 or another value.
• the soft programming voltage signal is incremented by a step size of ⁇ V spgml at step 616.
• it can be incremented by a step size of ⁇ V sp gm2, which could be larger than ⁇ V sp gmi.
• a soft programming voltage signal similar to the erase voltage signal of Figure 18A can be used in one embodiment.
• the source, bit, and source select gate lines are grounded and V SG is applied to the drain side select gate line.
• soft programming of the interior word lines is inhibited.
• Soft programming of the interior word lines can be inhibited by applying a small positive voltage on the order of about OV to 3V to the interior word lines.
• the voltage applied to the interior word lines is larger and on the order of about 5 V to 10V.
• the voltage can be a pass voltage (V paSs ) as typically applied to boost the voltage of a string's channel region to inhibit programming or soft programming.
• the higher voltage will be sufficient to ensure that the channel area of the inhibited NAND strings is sufficiently boosted to avoid further soft programming.
• the soft programming pulse is applied to just the end word lines of the set being erased in order to further soft program the end memory cells.
• the end memory cell word lines are verified for an erased state, while ensuring that the interior word lines are conductive regardless of their state (excluding the interior word lines from verification).
• the erase verify voltage level can be applied to the end word lines while a voltage of V usel (sufficient to ensure conduction of the interior word lines) is applied to the interior word lines. In this manner, verification is only performed for the end word lines, while excluding the interior word lines from verification.
• step 628 the number of non-conducting strings determined in step 626 is compared against a predetermined number. If the number of nonconducting strings is greater than the predetermined number, indicating that the cells of the end word lines have now shifted up close to the erase verify level, the method proceeds to step 630, where a status of pass is reported. If the number of non-conducting strings is not greater than the predetermined number, then the soft programming counter is compared against a predetermined limit value. If the soft programming counter is greater than the predetermined limit value, a status of fail is reported at step 614 for the operation.
• the soft programming counter is incremented by 1 and the soft programming voltage signal is stepped up at step 634.
• the NAND strings that were non- conductive (successfully soft programmed) during the verification at step 626 are inhibited from further soft programming. The method then proceeds to step 620 for further soft programming of the end memory cells.
• step 634 increments the soft programming voltage signal by the same size as step 616, while in other embodiments, other values are used.
• step 634 can include increasing by a size ⁇ V sp gm3 (similar to ⁇ VE RA 3)
• step 618 can include increasing by a size ⁇ V spgm2 (similar to ⁇ VE R A 2 )
• step 616 can include increasing by a size ⁇ V spgm i (similar to ⁇ VERAI)-
• step 616 could further include decreasing by a size ⁇ V spgm4 (similar to ⁇ VE R A4) during a first iteration and the increasing by a size ⁇ Vs Pgml for subsequent iterations.
• division of word lines within a NAND string for soft programming can be made in different way in different embodiments.
• the two most end word lines of a NAND string e.g., WLO, WLl, WL n-I , and WL n
• WLO, WLl, WL n-I , and WL n can be grouped together as the end word lines and the remaining word lines (WL2 - WL n-2 ) grouped together. as the interior word lines.
• step 622 of Figure 21 will include inhibiting word lines WL2 - WLn-2 and steps 624 and 626 will be performed to further soft program and verify word lines WLO, WLl 5 WL n-I , and WL n .
• six or more word lines could be grouped together as the end word lines. Other groupings can also be implemented.
• Figure 22 sets forth the bias conditions for the various operations of the flow chart depicted in Figure 21.
• Column 640 sets forth the bias conditions of the soft programming operation for all the memory cells of the set being erased. Column 640 corresponds to steps 604 through 606 of Figure 21.
• the bit line, source line, and p-well are at OV for soft programming.
• V DD is shown in parenthesis for the bit line voltage to indicate that V D D is applied to those NAND strings that are to be inhibited from soft programming.
• the source side select gate line is at OV, while the drain side select gate line is at V SG .
• the soft programming pulse V sp g m is applied to each of the word lines of the set in order to raise the threshold voltage of each memory cell connected thereto.
• Column 642 sets forth the bias conditions for verifying soft programming of all the memory cells of the set. Column 642 corresponds to step 608 of Figure 21. These bias conditions are the same as those for verifying erasure of all memory cells in a set of memory cells.
• the bit line is floating and the p-well is at OV, while VD D is provided to the source line. Both select gates are turned on by V SG .
• the erase verify voltage is applied to each word line to determine whether the string is non-conductive and thus has at least one memory cell that has reached the erase verify level.
• Column 644 sets forth the bias conditions for soft programming just the end word lines. Column 644 corresponds to steps 620 through 624 of Figure 21.
• the drain side select gate is turned on by supplying VS G to the drain side select gate line and the source side select gate is turned off by supplying OV to the source side select gate line.
• the interior word lines are provided a low positive voltage of V usel (e.g, OV to 5V). By supplying a small positive voltage to the interior word lines, the memory cells connected thereto can be inhibited from further programming under application of the soft programming pulses.
• the end word lines receive the soft programming pulse V S P G M in order to undergo further soft programming.
• Column 646 sets forth the soft programming verify bias conditions for just the end word lines.
• Column 646 can correspond to step 626 of Figure 21.
• the bit line is floating, while the source line is at VDD-
• the p-well is at zero volts.
• Both of the select gates are turned on by supplying Vso to the drain select gate line and the source select gate line.
• V US ei is applied to the interior word lines.
• the value of V usel used during soft programming (column 644) may be larger than OV to 3V in some instances.
• the value of V use i for verification is on the order of OV to 3 V. It need only be higher than the erase verify voltage to be sure the cells of the interior word lines for which soft programming is already completed are in a conducting state.
• the state of the memory cells on the end word lines can be determined independently and verified.
• the value of Vusel used during soft programming e.g., 5V to 10V
• the value used during soft programming verification e.g., OV to 3V.
• the erase verify voltage or OV is applied to the end word lines. In this manner, the interior word lines are excluded from soft programming verification, while the end word lines undergo verification.
• Figure 23 depicts the threshold voltage distributions for a set of memory cells after undergoing soft programming according to the embodiment of Figures 21 and 22. As shown in Figure 23, both the erase threshold distributions for the interior and end word lines have been moved up close to the erase verify level. The interior word line threshold voltage distribution 430 is shifted up close to the erase verify level as would occur normally. The end word line distribution 432 has also been moved up close to the erase verify level as a result of the additional soft programming (steps 618-635).

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