EP1864275A1

EP1864275A1 - Image display device and method of controlling same

Info

Publication number: EP1864275A1
Application number: EP06709267A
Authority: EP
Inventors: Arnaud Trochet; Sylvain Thiebaud; Philippe Leroy
Original assignee: Thomson Licensing SAS
Current assignee: THOMSON LICENSING
Priority date: 2005-02-10
Filing date: 2006-02-07
Publication date: 2007-12-12
Anticipated expiration: 2026-02-07
Also published as: US7924250B2; CN101116131A; JP4988603B2; CN101116131B; KR20070102524A; EP1864275B1; JP2008530604A; US20080062073A1; DE602006009087D1; WO2006084989A1; KR101321951B1

Abstract

The invention relates to an active matrix image display device (60) comprising: several light emitters (2, 4, 6, 8; 62, 64) which form a network that is divided into rows (10, 12; 61, 68) and columns (14, 16); a current modulator (36) for each emitter (2, 4, 6, 8; 62, 64); and at least one reverse-bias voltage generator (52, 54; 69). The inventive device is characterised in that it also comprises: a reverse-bias switch (59) for each emitter (2, 4, 6, 8; 62, 64), said reverse-bias switch (59) being connected to (i) each modulator (36) and (ii) each reverse-bias voltage generator (52, 54; 69); and control electrodes (70, 71, 72, 74) which can control all of the reverse-bias switches (59) in one row of emitters (10, 12; 61; 68). The invention also relates to a method of controlling the device.

Description

An image display device and method for controlling the same.

The present invention relates to an active matrix image display device comprising; a) several light emitters forming a network, divided into rows and columns; b) power supply means for the emitters; c) transmitter control means comprising:

a current modulator for each emitter, the modulator comprising a source electrode, a drain electrode, a gate electrode, the modulator being able to be traversed by a drain current, for supplying the emitter for a voltage between the electrode; source and the gate electrode, greater than or equal to a trigger threshold voltage of this modulator;

a storage capacitor for each emitter, said capacitor comprising a first and a second terminal and being able to store electrical charges at the gate electrode of each modulator;

addressing means capable of addressing display data to the emitters of each column;

selection means capable of selecting the emitters of each line, the selection means comprising a selection switch for each emitter, the selection switch being adapted to enable the gate electrode to be applied to the emitter of the electrode; source of each modulator addressing data provided by the addressing means; and d) at least one reverse bias voltage generator adapted to apply a bias bias bias bias voltage of said address data between the gate electrode and the source electrode of each modulator to compensate for voltage variation. trigger threshold of each modulator.

An OLED (Organic Light Emitting Diode) active matrix display device comprises light emitters formed from organic electroluminescent cells. For the control of these emitters, such a device comprises thin film transistors, called TFT (Thin Film Transistor) transistors. These transistors are able to control the current flowing through the emitters. They are made of polycrystalline silicon, for example using low temperature amorphous silicon (LTPS) crystallization technology, or directly in amorphous silicon.

However, the TFT manufacturing technology introduces local spatial variations in the trigger threshold voltage of these transistors. As a result, TFT transistors fed by the same supply voltage and controlled by identical voltages generate currents of different intensities which result in a non-uniform brightness of the display device comprising such transistors. As a result, for a given object of homogeneous luminance of an image to be displayed, spatial variations in the luminance of the pixels of the display device and a visible visual discomfort for the user.

The instability of the amorphous silicon results in a variation of the characteristics of the TFT when a voltage is applied between the gate and the source of the TFT. More particularly, the trigger threshold voltage of the TFT transistors increases when a positive polarity voltage is applied. is applied their gate and their source and decreases when a negative polarity voltage is applied between their gate and their source. Since the voltage applied between the gate and the source of the transistors generally differs from one transistor to the other according to the luminance deviations of the pixels of an image to be displayed, the degree of fluctuation of the trigger threshold voltage differs from one transistor to another. As a result, the resulting luminance variation is unevenly distributed on the display device, resulting in changes over time in the luminance of the display pixels and obvious visual discomfort for the display. 'user. In order to limit these disadvantages, various compensation circuits for the trigger threshold voltage drift have been proposed.

For example, the document US 2003/0052614 describes an image display device of the aforementioned type. This device comprises in particular, for each transmitter column, a control switch controlled by an electric control trode for moving this switch between a connection position to a reverse bias generator and a connection position to a column driving unit.

The inverse polarization generator is able to apply between the gate and the source of the modulators associated with the emitters of a column, a reverse bias voltage during so-called modulator regeneration phases, adapted to compensate for the drifts of their threshold voltage. trigger. This reverse bias voltage has a polarity inverse to the polarity of the addressing voltages applied between the gate and the source of these same modulators during illumination phases of the transmitters.

Note that the device described in the document US2003 / 0112205 does not allow to apply a reverse bias voltage between the gate and the source of the modulators associated with transmitters of the same line: in fact, in this document, when a inverse polarization is applied (see paragraph 44), it is at the terminals of the transmitters (see for example last sentence of paragraph 44) and not between the gate and the source of the modulators; in fact, during the reverse bias phases in question here, the gate and the source of the modulators are brought to the same potential by the simultaneous closing of the switches referenced Tr3 and Tr4, and there is no polarization, inverse or not, between the grid and the source.

An object of the invention is in particular to provide an alternative display device adapted to compensate for the variations over time of the trigger threshold voltages.

The invention relates to a display device of the aforementioned type, characterized in that it further comprises:

a reverse bias switch for each emitter, said inverse bias switch being connected between firstly the gate electrode of each modulator and the first terminal of the storage capacitor of this emitter, and secondly the or each reverse bias voltage generator and the second terminal of the storage capacitor of this emitter; and

control electrodes, each control electrode being able to drive all the reverse bias switches of a line of transmitters. According to particular embodiments, the display device comprises one or more of the following characteristics:

the selection means comprise selection electrodes suitable for driving the selection switches, said selection electrodes being distinct and independent of the control electrodes;

the network formed by the emitters comprises a first group of emitter lines and a second group of emitter lines, the lines of the two groups being intercalated, and each control electrode is connected to the gate of the inverse polarization switches; a line of emitters of the first group and the gate of the selector switches of a line of emitters of the second group for controlling the simultaneous closing of the selector switches and the control switches belonging to these lines of emitters;

it comprises a single reverse bias voltage generator connected to all the inverse polarization switches of the device;

it comprises a plurality of reverse bias voltage generators each capable of producing a clean reverse bias voltage different from the reverse bias voltages produced by the other generators, each generator being connected only to the set of reverse bias switches; a line of transmitters.

Advantageously, this device divides by two the number of line electrodes contained in the device.

The subject of the invention is also a method for controlling the image display device according to claim 3, said device comprising successively first and second transmitter lines, characterized in that the method comprises the following steps:

applying a first selection voltage to the control electrode connected to the selection switches of the first line of transmitters at a predefined frequency,

applying a second selection voltage to the control electrode connected to the selection switches of the second line of transmitters at the same preset frequency, and in that the applications of the first and second selection voltages are shifted by half a period, the duration of this half-period being equal to the duration of one half-frame of image.

According to particular embodiments, the control method of the display device comprises one or more of the following characteristics:

applying a selection voltage to the selection electrode at a predefined frequency,

- application of a control voltage to the control electrode at the same preset frequency, the application of said control voltage being shifted in time by a fraction of a period with respect to the application of said voltage of selection;

- the fraction of period is equal to half a period;

- the fraction of period is equal to one-third of a period; and the duration of a period is equal to the duration of an image frame.

The invention will be better understood on reading the description which follows, given solely by way of example and with reference to the appended drawings, in which:

- Fig.1 is a schematic view of a portion of a display device according to a first embodiment of the invention;

FIGS. 2 and 4 are graphs representing the temporal evolution of a selection signal suitable for selecting a first and a second transmitter of the device shown in FIG.

FIGS. 3 and 5 are graphs representing the time evolution of a control signal suitable for controlling the first and second emitters of the device shown in FIG.

FIGS. 6 and 7 are graphs representing the temporal evolution of a voltage associated with the first emitter and the second emitter of the device represented in FIG. - Fig.8 is a schematic view of a portion of a display device according to a second embodiment of the invention;

FIGS. 9, 10, 11 and 12 are graphs representing the temporal evolution of a control signal suitable for controlling a transmitter of a first line of transmitters, a transmitter of a second line of transmitters as well as a transmitter of a third line of transmitters, and respectively the transmitter of the third line of transmitters and a transmitter of a fourth line of transmitters, the device shown in Fig.8; and

13, 14 and 15 are graphs showing the time evolution of a voltage stored by a capacitor associated with the transmitter of the first line of transmitters, the transmitter of the second line of FIG. transmitters and respectively associated with the transmitter of the third line of transmitters, the device shown in Fig.8.

Part of the display device 1 according to a first embodiment of the invention is illustrated schematically in FIG. It comprises light emitters 2, 4, 6, 8, distributed in a network comprising rows and columns of emitters.

In Fig.1, only a first 10 and a second 12 lines of transmitters and a first 14 and second 16 columns of transmitters have been shown.

The emitters 2, 4, 6, 8 are organic light emitting diodes. They include an anode and a cathode. They emit a luminous intensity directly proportional to the current passing through them. Each transmitter constitutes an elementary pixel of the display device. The display device further comprises addressing circuits

18, 20, 22, 24 distributed in a network.

Each addressing circuit is connected to a transmitter 2, 4, 6, 8 to drive it.

Addressing circuits 18, 22; 20, 24 of each column of emitters 14, 16 are addressed via an addressing electrode 26, 28 of this column of emitters. Each addressing electrode 26, 28 is connected to a column driver unit 30 (in English: column driver).

The control unit 30 is able to receive an image display signal and to transmit simultaneously to each addressing electrode 26, 28 of a column, an address voltage V _data representative of a data item. display of a transmitter to be addressed in this column.

Addressing circuits 18, 20; 22, 24 of each emitter line 10, 12 are selected via a selection electrode 32, 34, each connected to a selection control unit 33, 35. The selection control unit 33, 35 of a line of transmitters 10, 12 is adapted to generate at a preset frequency, a selection signal V ₃₂ , V ₃₄ at the selection electrode 32, 34 of this line 10. , 12 to select all transmitters 2, 4 and 6, 8 of this line 10, 12. This selection signal comprises a series of pulses each generated at each new image frame. These pulses are logical data for selecting a transmitter of a line of transmitters.

Since the addressing circuits 18, 20, 22 and 24 are identical, only the circuit 18 will be described in detail. This circuit 18 comprises a current modulator 36, a selection switch 38, a storage capacitor 40 (referenced 41 in the addressing circuit 28 of the second emitter line 12) and two power supply electrodes 42, 44.

The current modulator 36 and the switch 38 are thin film transistors (in English: Thin Film Transistor), based on a technology using polycrystalline silicon (PoIy-Si), amorphous silicon (a-Si) or silicon microcrystalline (micro-Si) deposited in thin layers on a glass substrate. Such components comprise three electrodes: a drain electrode and a source electrode between which circulates a modulated current called drain current, and a gate electrode.

The modulator 36 shown in FIG. 1 is of type N, so that, in operation, its drain current flows from its drain to its source. It will be noted that the device according to the invention can also be used to drive P type TFT transistors. The capacitor 40 is able to store electrical charges to maintain a voltage at the gate of the modulator 36 after the transmission of a voltage. addressing.

The capacitor 40 comprises a first terminal 40a connected to the gate of the modulator 36 and a second terminal 40b connected to a reverse bias electrode 52.

The drain of the modulator 36 is connected to the cathode of the transmitter 2. The source of the modulator 36 is connected to the supply electrode 44 which is maintained at a constant potential. The gate of the modulator 36 is connected on the one hand to a first terminal of the capacitor 40 and on the other hand to a trode current passage (drain or source) of the switch 38. The other current passage electrode (drain or source) of the switch 38 is connected to the addressing electrode 26. The grid of the switch 38 is connected to the selection electrode 32. The anode of the transmitter 2 is connected to the supply electrode 42.

The display device 1 further comprises, for each line of emitters 10, 12, a reverse bias generator 46, 48 connected to a reverse bias electrode 52, 54 and a reverse bias control generator 53, 55 connected to a reverse bias control electrode 56, 58.

The inverse polarization generators 46 and 48 are capable of generating, each between the gate and the source of the modulators 36, a bias voltage Vp, with values possibly different from each other and of polarity opposite to the polarity of the addressing voltages V _data applied between the gate and the source of the modulators 36 during the emission phases of the emitters 2, 4, 6, 8.

The inverse bias electrode 52, 54 is connected to the second terminal of the capacitor 40, 41 of each addressing circuit of a transmitter line 10, 12.

Bias control generators reverse 53, 55, are adapted to produce a reverse bias control signal V ₅ 6, V ₅ 8, similar to the selection signal ₃₂ V, V3 _4, the same frequency and shifted by a half period or period variable with respect to this selection signal.

The device 1 further comprises a reverse bias switch 59 in each addressing circuit 18, 20, 22, 24. This switch 59 is a thin-film transistor of the same type as the switch 38 and the modulator 36.

A current-passing electrode (source or drain) of the switch 59 of each addressing circuit of an emitter line 10, 12 is connected to the inverse bias electrode 52, 54 of this emitter line. 10, 12, and therefore also to the second terminal 40b of the capacitor 40, 41. The other current-passing electrode (source or drain) of the switch 59 is connected to the gate of the modulator 36, and consequently, also at the first terminal 40a of the capacitor 40, 41. The gate of the switch 59 of each addressing circuit of an emitter line 10, 12 is connected to the reverse bias control electrode 56, 58 of this same emitter line 10, 12.

Only the operation of the emitters 2, 6 of the first column 14, and the first 10 and the second 12 emitter lines is described in detail.

At the time T = TO ₁ a pulse of the selection signal V ₃₂ shown in Fig.2, is generated at the selection electrode 32 of the first line of transmitters 10. Simultaneously, the control unit 30 addresses a voltage of address V _da ta2 to the addressing electrode 26. The value of this addressing voltage is referenced to the constant potential of the supply electrode 44.

As a result, the switches 38 of the first line of transmitters

10 are closed and the voltage V _da ta2 is applied to the first terminal 40a of the capacitor 40 and between the gate and the source of the modulator 36 of the addressing circuit 18, as shown in FIG. After the end of the pulse of the selection signal V ₃₂ , the switches 38 of the first line of emitters 10 open and the voltage V _da t _a2 is maintained, thanks to the capacitor 40, between the gate and the source of the modulator 36 of the addressing circuit 18, as visible in FIG.

Since the voltage V _data2 is greater than the triggering threshold voltage of the modulator 36, a drain current passes through the emitter 2 which is illuminated.

At the time T = T1, a pulse of the selection signal V ₃₄ shown in FIG. 4 is applied to the selection electrode 34. Simultaneously, the control unit 30 addresses an address voltage Vdataβ to the electrode The value of this addressing voltage is also referenced to the constant potential of the supply electrode 44.

Consequently, the switches 38 of the second line of emitters 12 close and the voltage V _data6 is applied to the capacitor 41 and between the gate and the source of the modulator 36 of the addressing circuit 22 of the second emitter line 12 Since the voltage V _d ataβ is greater than the trigger threshold voltage of the modulator 36, a drain current passes through the emitter 6 which is illuminated. After the end of the pulse of the selection signal V ₃₄ , the switches 38 of the second line of emitters 12 open and the voltage Vdataδ is maintained, thanks to the capacitor 41, between the gate and the source of the modulator 36 of the addressing circuit 22, as visible in FIG.

This step is repeated successively for each transmitter of a line, line by line for all the lines of the display device during a period ranging from T = T1 to T = T4.

At the same time, at the time T = T2, a pulse of the control signal V ₅₆ shown in FIG. 3 is applied to the control electrode 56.

This pulse closes the switches 59 of the first emitter line 10, so that the reverse bias voltage V _p generated by the generator 46 is applied between the gate and the source of the modulator 36 of the addressing circuit 18; as the switch 59 then bypasses the two terminals of the capacitor 40, this capacitor is discharged. After the end of the pulse of V ₅ 6 Control signal, the switches 59 of the first row of emitters 10 open and the voltage Vp is maintained between the gate and the source of the modulator 36 of the addressing circuit 18 as shown in Fig. 6, since the capacitor 40 retains zero charge.

Then, at the time T = T3, a pulse of the control signal V ₅₈ shown in FIG. 5 is applied to the control electrode 58 of the second emitter line 12 to close the switches 59 of this second line 12. Consequently, the reverse bias voltage V _p generated by the generator 48 is applied to the second terminal of the capacitor 41 as well as to the gate of the modulator 36 of the addressing circuit 22 of the second emitter line 12; as the switch 59 bypasses both terminals of the capacitor 41, this capacitor is discharged. After the end of the pulse of the control signal V ₅₈ , the switches 59 of the second line of emitters 12 open and the voltage Vp is maintained between the gate and the source of the modulator 36 of the addressing circuit 22, as shown in Fig.7, because the capacitor 41 retains a zero charge.

At time T = T4, the step performed at time T = TO is repeated. Thus, a pulse of the selection signal V32 shown in FIG. 2 is applied to the selection electrode 32. Simultaneously, the control unit 30 addresses a new address voltage to the addressing electrode 26.

At time T = T5, the step performed at time T = T 1 is repeated. Next, the operating method of the device according to the invention is continued by repeating the steps described above.

The duration of TO to T4 corresponds to the duration of an image frame. The duration of an image frame is divided into two phases, here TO to T2 and T2 to T4, for example of a duration each equal to the duration of a half frame of image.

During a first phase (corresponding to the durations of T = TO to

T = T2 and T = T 1 to T = T3), the emitters of the screen are illuminated, and during a second phase (corresponding to the durations of T = T2 at T = T4 and T = T3 at

T = T5), the transmitters are off. The ratio of the durations between the first phase and the second phase is 50/50.

Alternatively, the ratio of the durations between the first phase and the second phase is 60/40 or 70/30.

During the transmission phases of the transmitters, the V _data addressing voltages of display data applied between the gate and the source of the modulators 36 connected to these transmitters, are adapted to vary the tripping threshold voltages of the modulators. 36 in a first sense.

During the off-state of the emitters, the reverse bias voltages V _p are applied between the gate and the source of the modulators 36 connected to these emitters to vary their trigger threshold voltage in the opposite direction so as to compensate for the drift. possible of this threshold voltage.

As the reverse bias voltages V _p shown in FIGS. 6 and 7, have a polarity inverse to the polarity of the addressing voltages V _data 2, V _da ta6 previously applied to the modulators 36, they are adapted to reduce the trigger threshold voltage of the modulators 36 in order to bring it back to their initial tripping threshold voltage (before application of the addressing voltage).

Part of a display device 60 according to a second embodiment of the invention is illustrated schematically in FIG. The elements of the second embodiment illustrated in Fig.8 identical or similar to the elements of the first embodiment illustrated in Fig.1, are designated by the same reference numerals as in Fig.1, and are not described a second time. FIG. 8, representing the device 60, comprises in addition to the part of the device 1 represented in FIG. 1, a third line of emitters 61, comprising emitters 62 and 64, each driven by an addressing circuit 66, 67, as well as a fourth line of emitters 68 not shown in detail. The circuit 66 is identical to the circuits 18, 20, 22, 24. It comprises a referenced capacitor 76 having a first 76a and a second 76b terminals, and a reverse bias electrode referenced 69 similar to the electrodes 52 and 54 and connected to the second terminal 76b of the capacitor 76 and a current passing electrode of the switch 59. The reverse bias generators 46, 48 connected to the electrodes 52, 54 and 69 have not been shown to simplify Fig.8.

The device 60 comprises control electrodes for selection and for the reverse bias 70, 71 and 72 in place of the selection electrodes 32, 34 and the reverse bias control electrodes 56 and 58 of the device 1 and an additional control electrode referenced 74.

The control electrode 70 is connected to all of the reverse bias control switches 59 of a transmitter line, not shown, positioned just above the first line 10, as well as to all the switches. 38 of the first line of transmitters 10. The control electrode 71 is connected to all of the reverse bias control switches 59 of the first line of emitters 10, as well as to all the switches. 38 of the second line of transmitters 12.

Similarly, the control electrode 72, respectively the control electrode 74, is connected to all the reverse bias control switches 59 of the second line of emitters 12, respectively of the third line of emitters 61. , as well as to all the selection switches 38 of the third line of emitters 61, respectively of the fourth line of emitters 68. Thus, the reverse bias control switches 59 of a line are connected to the same control electrode as the selector switches 38 of the next line.

The device 60 further comprises control generators 80, 82, 84, 86 each connected to a control electrode 70, 71, 72, 74. The generators 80, 82, 84, 86 are capable of producing a control signal V70, V71, V72, V ₇₄ of the same frequency. As can be seen in FIGS. 9 to 12, the control signals Vz _O , Vn applied to the electrodes of two adjacent lines 10, 12 are shifted by half a picture period. Only the operation of emitters 6 and 62 of the first column

14 and first 10, second 12 and third 61 lines of transmitters, is described in detail.

At the time T = TO, a pulse of the control signal V ₇₁ shown in FIG. 10 is transmitted to the control electrode 71. This pulse causes the closing of the reverse bias switches 59 of the first line of FIG. transmitters 10 and selector switches 38 of the second line of transmitters 12.

Simultaneously, an addressing voltage Vd _ata β representative of a display datum is applied to the addressing electrode 26 by the control unit 30. The value of this addressing voltage is referenced to the potential constant of the supply electrode 44.

Since the switches 59 of the first line of emitters 10 are closed, the reverse bias voltage V _p resulting from the inverse bias electrode 52 is applied between the gate and the source of the modulators 36 and across the capacitors 40 of the first line of emitters 10. As the switch 59 then bypasses the two terminals of the capacitor 40, this capacitor is discharged. After the end of the pulse of the control signal V ₇₁ , the switches 59 of the first line of emitters 10 open and the voltage V _p is maintained between the gate and the source of the modulator 36 of the addressing circuit 18 , as visible in Fig.13, because the capacitor 40 retains a zero charge.

At the same time, since the switches 38 of the second line of emitters 12 are simultaneously closed, the addressing voltage Vdataδ originating from the electrode 26 is applied to the first terminal 41a of the capacitor 41 and to the gate of the modulator 36 of the second row of transmitters 12, as visible on the

Fig.14.

As a result, the transmitter 2 is off and the transmitter 6 is illuminated. After the end of the pulse of the control signal V ₇₁ , the switches 38 of the second line of emitters 12 open and the voltage Vdataβ is maintained, thanks to to the capacitor 41, between the gate and the source of the modulator 36 of the addressing circuit 22, as visible in FIG.

At the time T = T 1, a pulse of the control signal V ₇₄ shown in FIG. 12 is applied to the control electrode 74. The application of this pulse causes the switches 59 of the third line to close. Transmitters 61. As a result of this closure, the reverse bias voltage V _p of the inverse bias electrode 69 is applied between the gate and the source of the modulator 36 and across the capacitor 76 of the third emitter line 61, as shown in Fig.15. As a result, the transmitter 62 turns off.

As the switch 59 then bypasses the two terminals of the capacitor 76, this capacitor is discharged. After the end of the pulse of the control signal V ₇₄ , the switches 59 of the third line of emitters 66 open and the voltage V _p is maintained between the gate and the source of the modulator 36 of the addressing circuit 66 as shown in Fig. 15 because the capacitor 76 retains zero charge.

At time T≈T2, a pulse of the control signal V ₇₀ shown in FIG. 9 is applied to the control electrode 70 by the generator 80 and an addressing voltage Vdata2 is applied to the addressing electrode 26. by the addressing control unit 30. The value of this addressing voltage is also referenced to the constant potential of the supply electrode 44.

Accordingly, the addressing voltage V _dat a2, as shown in Fig.13 is applied to the gate of the modulator 36 and across the capacitor 40 of the first emitter line 10 and the emitter 2 is illuminated. After the end of the pulse of the control signal V ₇₀ , the switches 38 of the first line of emitters 10 open and the voltage V _da ta2 is maintained, thanks to the capacitor 40, between the gate and the source of the modulator 36 of the addressing circuit 18, as visible in Fig.13.

At the time T = T3, a pulse of the control signal V ₇₂ shown in FIG. 11 is applied to the control electrode 72. This causes the closing of the inverse polarization switches 59 of the second emitter line 12 and the closing of the selector switches 38 of the third line of emitters 61. As the switch 59 then bypasses the two terminals of the capacitor 41, this capacitor is discharged. After the end of the pulse of control signal V72, the switches 59 of the second line of emitters 12 open and the voltage V _p is maintained between the gate and the source of the modulator 36 of the addressing circuit 22, as can be seen in FIG. because the capacitor 41 maintains a zero charge. Consequently, the reverse bias voltage V _p of the inverse bias electrode 54 is applied between the gate and the source of the modulator 36 and across the capacitor 41 of the second emitter line 12, as can be seen in FIG. 14.

As a result, the transmitter 6 goes off. At the same time, an address voltage V _data _ ₆₂ , as shown in FIG. 15, is transmitted by the electrode 26, and applied to the gate of the modulator 36 and to a terminal of the capacitor 76 of the third line of FIG. Transmitters 61. Accordingly, transmitter 62 is illuminated.

At time T = T4 and T = T5, the steps performed at time T = O and T = 1 are repeated, respectively.

The time periods from T = TO to T = T4 and from T = T1 to T = T5 each correspond to the duration of an image, here consisting of two interlaced fields.

According to this embodiment of the invention, the emitters of a group comprising the odd lines 10, 61 of the device are extinguished during a first frame T0-T2; T1-T3, then illuminated during a second T2-T4 frame; T3-T5.

Conversely, the transmitters of another group comprising the even lines 12, 68 of the device are illuminated during a first frame T0-T2; T1-T3 then extinguished during a second T2-T4 frame; T3-T5.

Without departing from the invention, it is possible to reverse the order between the even fields and the odd fields.

When the emitters 2, 4 of the first line 12 are off, the emitters 6, 8 of the second line 12 are illuminated and vice versa. Advantageously, this second embodiment of the invention facilitates the addressing of the display data when the display mode is interlaced because the control unit 30 does not need to recalculate the staggering of the data to be addressed. display signal it receives, to return to so-called "progressive" mode. Indeed, when using an interlaced display mode, the transmitters of a line are addressed on all the columns simultaneously, for all the even lines in a first frame, and then for the set odd lines in a second frame. Advantageously, this second embodiment of the invention makes it possible to reduce the number of line electrodes because the control electrodes 70, 71, 72, 74 make it possible to control both the addressing of the addressing voltages and the addressing reverse bias voltages.

Advantageously, this device makes it possible not to use a control unit capable of addressing positive and negative polarity voltages. This type of control unit is indeed expensive.

In a variant, the reverse biasing electrodes 52, 54, 69 of the entire display device are connected to a single reverse bias voltage generator.

Claims

An active matrix image display device (1; 60) comprising; a) a plurality of light emitters (2, 4, 6, 8, 62, 64) forming a network, divided into lines (10, 12; 61, 68) and columns (14, 16); b) power supply means (42, 44) of the emitters; c) transmitter control means comprising:

a current modulator (36) for each emitter (2, 4, 6, 8; 62, 64), the modulator (36) comprising a source electrode, a drain electrode, a gate electrode, the modulator (36) being capable of being traversed by a drain current, for supplying said transmitter (2, 4, 6, 8; 62, 64) for a voltage between the source electrode and the gate electrode, greater than or equal to a voltage tripping threshold of this modulator;

a storage capacitor (40, 41, 76) for each transmitter (2, 4, 6, 8, 62, 64), said capacitor (40, 41, 76) having a first (40a, 41a, 76a) and a second (40b, 41b; 76b) terminals and being adapted to store electrical charges at the gate electrode of each modulator (36);

addressing means (26, 28, 30) able to send display data to the emitters (2, 4, 6, 8, 62, 64) of each column (14, 16); selection means (32, 34, 38) capable of selecting the transmitters (2, 4, 6, 8, 62, 64) of each line (10, 12, 61, 68), the selection means (32, 34, 38) comprising a selection switch (38) for each transmitter (2, 4, 6, 8; 62, 64), the selection switch (38) being adapted to allow application between the gate electrode and the source electrode of each modulator (36) an address data provided by the addressing means (26, 28, 30); and d) at least one reverse bias voltage generator (46, 48, 52, 54; 69) adapted to apply a reverse bias voltage (V _p ) of the polarization of said addressing data between the gate electrode and the source electrode of each modulator (36) for compensating the variation of the trigger threshold voltage of each modulator (36); characterized in that it further comprises:

- a reverse bias switch (59) for each transmitter (2, 4, 6, 8; 62, 64), said reverse bias switch (59) being connected between on the one hand the gate electrode of each modulator (36) and the first terminal (40a, 41a; 76a) of the storage capacitor (40, 41; 76) of this emitter, and on the other hand the or each generator the reverse bias voltage (46, 48, 52, 54; 69) and the second terminal (40b, 41b, 76b) of the storage capacitor (40, 41; 76) of this emitter; and

control electrodes (56, 58; 70, 71, 72, 74), each control electrode (56, 58; 70, 71, 72, 74) being able to control all the reverse-biasing switches (59, 58, 70, 71, 72, 74); ) of a transmitter line (10, 12; 61, 68).

2. Device (1) according to claim 1, characterized in that the selection means (32, 34, 38) comprise selection electrodes (32, 34) adapted to drive the selection switches (38), said electrodes of selection (32, 34) being distinct and independent of the control electrodes (56, 58).

3. Device (60) according to claim 1, characterized in that the network formed by the emitters (2, 4, 6, 8, 62, 64) comprises a first group of emitter lines (10, 61) and a second group of emitter lines (12, 68), the lines of the two groups being interposed, and in that each control electrode (71, 74) is connected to the gate of the inverse polarization switches (59) d a line of emitters (10, 61) of the first group and the gate of the selector switches (38) of a line of emitters (12, 69) of the second group for controlling the simultaneous closing of the selection switches ( 38) and control switches (59) belonging to these transmitter lines (10, 12, 61, 69).

4. Device (1; 60) according to any one of claims 1 to 3, characterized in that it comprises a single reverse bias voltage generator (46, 48, 52, 54; 69) connected to the assembly reverse bias switches (59) of the device.

5. Device (1; 60) according to any one of claims 1 to 3, characterized in that it comprises several generators (46, 48, 52, 54, 69) of reverse bias voltage each to produce a voltage of own inverse polarization (V _p ) and different from the reverse bias voltages (V _p ) produced by the other generators, each generator (46, 48, 52, 54; 69) being connected only to the set of reverse bias switches (59) of a transmitter line (10, 12; 61, 68).

6. A method of controlling an image display device (60) according to claim 3, said device comprising successively a first (10) and a second (12) line of transmitters, characterized in that the method comprises the following steps:

- applying a first selection voltage (V7 ₀ ) to the control electrode (70) connected to the selection switches (38) of the first transmitter line (10) at a predefined frequency, - application of a second selection voltage (V ₇₁ ) to the control electrode (71) connected to the selection switches (38) of the second transmitter line (12), at the same predetermined frequency, and that the applications of the first (V ₇₀ ) and second (V71) selection voltages are shifted by half a period, the duration of this half-period being equal to the duration of half a frame of image.

7. A method of controlling an image display device (1) according to claim 2, said device comprising successively a first (10) and a second (12) line of transmitters, characterized in that the method comprises the following steps: - application of a selection voltage (V ₃₂ ) to the selection electrode

(32), at a predefined frequency,

- application of a control voltage (Vsβ) to the control electrode (56) at the same preset frequency, the application of said control voltage (V ₅₅ ) being shifted in time by a fraction of a period with respect to the application of said selection voltage (V ₃₂ ).

8. Driving method according to claim 7, characterized in that the period fraction is equal to half a period.

9. Driving method according to claim 7, characterized in that the period fraction is equal to one-third of a period.

10. Driving method according to any one of claims 7 to

9, characterized in that the duration of a period is equal to the duration of an image frame.