EP1852873A1 - Magnetic memory device - Google Patents

Magnetic memory device Download PDF

Info

Publication number
EP1852873A1
EP1852873A1 EP06113534A EP06113534A EP1852873A1 EP 1852873 A1 EP1852873 A1 EP 1852873A1 EP 06113534 A EP06113534 A EP 06113534A EP 06113534 A EP06113534 A EP 06113534A EP 1852873 A1 EP1852873 A1 EP 1852873A1
Authority
EP
European Patent Office
Prior art keywords
magnetic
layer
ferromagnetic layer
multilayer structure
magnetic field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06113534A
Other languages
German (de)
English (en)
French (fr)
Inventor
Kenchi Ito
Hiromasa Takahashi
Takayuki Kawahara
Riichiro Takemura
Thibaut Devolder
Paul Crozat
Joo-Von Kim
Claude Chappert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Centre National de la Recherche Scientifique CNRS
Universite Paris Sud Paris 11
Hitachi Ltd
Original Assignee
Centre National de la Recherche Scientifique CNRS
Universite Paris Sud Paris 11
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Centre National de la Recherche Scientifique CNRS, Universite Paris Sud Paris 11, Hitachi Ltd filed Critical Centre National de la Recherche Scientifique CNRS
Priority to EP06113534A priority Critical patent/EP1852873A1/en
Priority to PT06118378T priority patent/PT1863034E/pt
Priority to EP06118378A priority patent/EP1863034B1/en
Priority to DE602006019389T priority patent/DE602006019389D1/de
Priority to TW095146660A priority patent/TWI332662B/zh
Priority to US11/638,379 priority patent/US7738286B2/en
Priority to CN2006101694759A priority patent/CN101068036B/zh
Priority to KR1020060128494A priority patent/KR100856985B1/ko
Priority to JP2007090269A priority patent/JP5295513B2/ja
Publication of EP1852873A1 publication Critical patent/EP1852873A1/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1657—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access

Definitions

  • the present invention relates to a magnetic memory device and in particular, although not exclusively, to a magnetic random access memory.
  • the present invention relates also to a method of writing to a magnetic memory device.
  • MRAM magnetic random access memory
  • DRAM dynamic RAM
  • SRAM static RAM
  • a conventional MRAM cell comprises a magnetic element having a ferromagnetic free layer and a ferromagnetic pinned layer, separated by a non-magnetic layer.
  • the pinned layer has a relatively high coercivity, so that its magnetisation remains fixed upon the application of a writing magnetic field.
  • the free layer has a relatively low coercivity, so that its magnetisation can be changed upon application of the writing magnetic field.
  • the writing magnetic field is applied to switch the magnetisation of the free layer to be either parallel or anti-parallel to the pinned layer.
  • the free layer exhibits magnetic hysteresis, thus its magnetisation remains unchanged when the magnetic field is removed. This results in a non-volatile memory.
  • the state of the magnetic element To read the state of the MRAM cell, a small current is driven through the magnetic element.
  • the magnetoresistance of the magnetic element will be higher when the magnetisations of the free layer and the pinned layer are antiparallel, than when the magnetisations of the free layer and the pinned layer are parallel. In this way, the state of the magnetic element can be determined by measuring its resistance.
  • Such a conventional MRAM suffers from the disadvantage that as the size of the MRAM cell decreases, the magnetic field required to switch the magnetisation of the free layer increases. Therefore, the power consumption of the device increases as the cell size decreases.
  • STT switching is described in " Current-driven Excitation of Magnetic Multilayers" by J.C. Slonczewski, p.9353, Phys. Rev. B, Vol. 54 (1996 ).
  • a current is driven through the magnetic element perpendicular to the plane of the free and pinned layers. This can result in the injection of spin-polarised electrons into the free layer, either by electrons flowing through the pinned layer, when current is driven from the free layer to the pinned layer, or by electrons scattering from the pinned layer 85, when current is driven from the pinned layer to the free layer.
  • the threshold current density for STT switching depends on material constants such as the saturation magnetisation, Gilbert's damping constant, and the spin polarisations of both the pinned and free layers.
  • Magnetization switching by spin torque using subnanosecond current pulses assisted by hard axis magnetic fields by T. Devolder et al., Appl. Phys. Lett., 88, pp.152502 (2006 ) describes an experiment conducted using a pillar-shaped spin valve in which magnetisation switching is induced by spin transfer using nano-second current pulses combined with a fixed hard axis field.
  • the present invention seeks to provide an improved magnetic memory device.
  • a magnetic memory device comprising: first and second leads; a magnetoresistive multilayer structure arranged between said leads such that current is conducted from the first lead to the second lead through layers of said multilayer structure, said multilayer structure exhibiting a first, relatively high resistance state and a second, relatively low resistance state, said multilayer structure including a first ferromagnetic layer having a magnetic hard axis and a magnetic easy axis, and said multilayer structure being switchable between said first and second states; and characterised by a magnetic field source for controllably applying a magnetic field along the magnetic hard axis in the ferromagnetic layer independently of current flow through the multilayer structure for assisting switching of the multilayer structure between first and second states.
  • a lower switching current can be used. In turn, this can lead to an increase in writing speed for a given current.
  • the multilayer structure may comprise a magnetic tunnel junction, the magnetic tunnel junction comprising said first ferromagnetic layer, a second region and an insulating layer separating the first ferromagnetic layer and the second region. This can increase the ratio of magnetoresistance of the relatively high resistance state and the relatively low resistance state.
  • the first ferromagnetic layer may have a relatively low coercivity and the second region may comprise a synthetic anti-ferromagnetic (SAF) layer, having a relatively high coercivity; wherein the SAF layer comprises: a first ferromagnetic sub-layer; a second ferromagnetic sub-layer, with a magnetisation of substantially equal magnitude and anti-parallel to the magnetisation of first ferromagnetic layer; and an anti-ferromagnetic coupling sub-layer separating the first ferromagnetic sub-layer and second ferromagnetic sub-layer, and wherein said multilayer structure further comprises an anti-ferromagnetic layer coupled to said SAF layer for pinning the magnetisation of the SAF layer, the SAF layer separating the insulating layer and the pinning layer.
  • SAF synthetic anti-ferromagnetic
  • the first ferromagnetic layer may have a relatively low coercivity and the second region may comprise a second ferromagnetic layer, having a relatively high coercivity.
  • the second ferromagnetic layer may be thicker than the first ferromagnetic layer.
  • the multilayer structure may further comprise an anti-ferromagnetic layer coupled to the second ferromagnetic layer for pinning the magnetisation of the second ferromagnetic layer, wherein the second ferromagnetic layer separates the insulating layer and the anti-ferromagnetic layer.
  • the multilayer structure may further comprise a third ferromagnetic layer, spaced from the first ferromagnetic layer, for spin-polarising electrons when current flows from the second ferromagnetic layer to the first ferromagnetic layer.
  • the multilayer structure may be formed in an upstanding pillar.
  • the pillar may have an elliptical base having short and long axes, wherein the magnetic hard axis of the first ferromagnetic layer is directed along the short axis.
  • the ratio of the axes may be in the range 1:1.5 to 1:2.5.
  • the ratio of the axes may be 1:2.
  • the magnetic field source may comprise an elongate conductor having a longitudinal axis arranged parallel to the easy axis of the first ferromagnetic layer.
  • the elongate conductor may be a wire.
  • the elongate conductor may be formed of a metal.
  • the elongate conductor may be formed of an alloy.
  • the elongate conductor may have a thickness between 10 nm and 100 nm.
  • the elongate conductor may have width between 10 nm and 100 nm.
  • the elongate conductor may pass less than 200 nm from the first ferromagnetic layer.
  • the elongate conductor may pass between 20 nm and 100 nm from the first ferromagnetic layer.
  • the conductor may be configured such that when a current passes through the conductor in response to a bias of the order of 1 V applied across the conductor, a magnetic field of between 0.1 to 0.2 of an anisotropy magnetic field of the first ferromagnetic layer is generated in the first ferromagnetic layer.
  • the conductor may be configured such that when a current passes through the conductor in response to a bias of the order of 1 V applied across the conductor, a magnetic field of at least 20 Oe is generated in the first ferromagnetic layer.
  • the conductor may be configured such that when a current passes through the conductor in response to a bias of the order of 1 V applied across the conductor, a magnetic field of between 20 Oe to 50 Oe is generated in the first ferromagnetic layer.
  • a magnetic random access memory comprising: an array of the magnetic memory devices, wherein each multilayer structure connects a one of said first leads with a one of said second leads; and a third set of leads, such that each multilayer structure is addressable by one of said first or second leads and one of said third set of leads.
  • an MRAM comprising: a first, second and thirds sets of leads; an array of magnetoresistive multilayer structures, each magnetoresistive multilayer structure connecting a one of said first set of leads with a one of said second set of leads, such that each multilayer structure is addressable by one of said first or second set of leads and one of said third set of leads, said multilayer structure exhibiting a first, relatively high resistance state and a second, relatively low resistance state, said multilayer structure including a ferromagnetic layer having a magnetic hard axis and a magnetic easy axis, and said multilayer structure being switchable between said first and second states; and characterised by a plurality of magnetic field sources, each for controllably applying a magnetic field along the magnetic hard axis in the ferromagnetic layer of at least one of said array of magnetoresistance multilayer structures, independently of current flow through the multilayer structures for assisting switching of the multilayer structures between first and second states.
  • Each of said first leads and each of said second leads may be shared between a column of the array.
  • Each of said third leads may be shared between a row of the array.
  • the MRAM may further comprise an array of isolation transistors, wherein each of said multilayer structures is connected to the source or drain of one of said isolation transistors by one of said first leads or one of said second leads, and each of said third leads is connected to the base of the isolation transistors in a row of the array.
  • a magnetic field source may be provided for each column of the array, and wherein each magnetic field source comprises an elongate conductor having a longitudinal axis arranged parallel to the magnetic easy axis of the ferromagnetic layers.
  • a method of writing to a magnetic memory device comprising: first and second leads; a magnetoresistive multilayer structure arranged between said leads, said multilayer structure exhibiting a first, relatively high resistance state and a second, relatively low resistance state, said multilayer structure including a ferromagnetic layer having a magnetic hard axis and a magnetic easy axis, and said multilayer structure being switchable between said first and second states; and characterised by a magnetic field source for controllably applying a magnetic field along the magnetic hard axis in the ferromagnetic layer independently of current flow through the multilayer structure for assisting switching of the multilayer structure between first and second states, said method comprising: applying a magnetic field along the magnetic hard axis in the ferromagnetic layer using the magnetic field source; applying a bias between the first lead and the second lead to drive a current through the magnetoresistive multilayer structure; removing said magnetic field; and removing said bias, wherein applying the magnetic field occurs
  • Applying the magnetic field may occur at least 1 ns before applying the bias.
  • Removing the magnetic field may occurs before removing the bias.
  • Applying the bias may occurs 2 ns after applying the magnetic field, removing the magnetic field may occurs 3 ns after applying the magnetic field, and removing said bias may occur 6 ns after applying the magnetic field.
  • the magnitude of the applied magnetic field in the ferromagnetic layer may be between 0.1 to 0.2 of an anisotropy magnetic field of the first ferromagnetic layer.
  • FIG. 1 a schematic of a prior art MRAM array is shown.
  • the MRAM array is arranged in a cross-point architecture, with a magnetic tunnel junction (MTJ) 1 between each intersection of one of a plurality of bit lines 3 and one of a plurality of digit lines 5 arranged perpendicular to the bit lines 3. Therefore, each row of the array is defined by a bit line 3 and each column of the array is defined by a digit line 5.
  • MTJ magnetic tunnel junction
  • the MTJ 1 is in electrical contact with the bit line 3. However, the MTJ 1 is electrically isolated from the digit line 5 by an insulating matrix 18.
  • the MTJ 1 has a magnetic easy axis in the plane of the MTJ 1 (defined herein as the x-y plane) and a magnetic hard axis in the plane of the MTJ 1.
  • the magnetic easy axis is defined to be parallel to the x-axis
  • the magnetic hard axis is defined to be parallel to the y-axis.
  • the bit line 3 is aligned parallel to the easy axis of the MTJ 1 i.e. aligned parallel to the x-axis.
  • the digit line 5 is aligned parallel to the hard axis of the MTJ 1 i.e. aligned parallel to the y-axis.
  • Each MTJ 1 is disposed on a bottom electrode 7.
  • Each bottom electrode 7 is connected to an isolation transistor 9, 9a, 9b.
  • Each isolation transistor 9, 9a, 9b is connected to a sense line (not shown).
  • Word lines 11 run parallel to the digit lines 5 i.e. parallel to the y-axis. Each word line 11 is connected to the gate of all the transistors 9, 9a, 9b in a single column.
  • Figure 2 is a cross-section through two neighbouring memory cells of a row of the MRAM array, taken along the line A-A'.
  • Each memory cell 13a, 13b is formed of one transistor 9a, 9b and one MTJ 1a, 1b.
  • a source 15 of each isolation transistor 9a,9b is shared between neighbouring cells 13a, 13b.
  • a sense line 17 is connected to the source 15 of the isolation transistor 9a, 9b.
  • both MTJs 1a, 1b are connected to the bit line 3.
  • Each MTJ 1a, 1b is connected via a respective bottom electrode 7a, 7b to a drain 19a, 19b of the transistor 9a, 9b.
  • a word line 11a, 11b is connected to a gate 21 a, 21 b of each transistor 9a, 9b.
  • a digit line 5a, 5b runs underneath each MTJ 1a, 1b. The digit line 5a, 5b is separated from the bottom electrode 7a, 7b by an insulating matrix 18.
  • Each MTJ 1a, 1b comprises a free layer 23, a pinned layer 25, and a thin dielectric barrier 27 between the free layer 23 and the pinned layer 25.
  • a pinning layer 29 is coupled to the pinned layer 25.
  • the free layer 23 is a ferromagnetic layer having a relatively low coercivity.
  • the pinned layer 25 is a ferromagnetic layer having a relatively high coercivity.
  • the dielectric barrier 27 has a thickness such that electrons can tunnel through it.
  • the pinning layer 29 is an antiferromagnetic layer and prevents the magnetisation of the pinned layer 25 from switching.
  • the dielectric barrier 27 comprises aluminium oxide (AlO x ) and has a thickness of about 20 ⁇ .
  • the free layer 23 and the pinned layer 25 are formed of nickel iron (NiFe).
  • the pinning layer 29 can be formed of iron manganese (FeMn) or iridium manganese (IrMn).
  • the field H 1 generated by the bit line 3 is about half the field required to switch the magnetisation of the free layer 23.
  • the field H 2 generated by the digit line 5a is also about half the field required to switch the magnetisation of the free layer 23.
  • the sum of the two magnetic fields H 1 and H 2 is just over the switching threshold of the free layer 23.
  • the magnetic field generated around the MTJ 1b is insufficient to cause switching of the free layer 23.
  • the magnetic field generated around the MTJ 1 a is sufficient to cause switching of the free layer 23. In this way, only a single MTJ 1a is switched by driving current through the bit line 3 corresponding to the row of the MTJ 1a and through the digit line 5a corresponding to the column of the MTJ 1a.
  • the sum of the magnetic fields H 1 and H 2 is insufficient to cause switching of the pinned layer 25.
  • a bias is applied to the word line 11 a, so that the transistor 9a is switched on. Therefore, current can flow through the MTJ 1a, and current is also able to flow through all the MTJs in the same column of the array. Then, a bias is also applied to the bit line 3. Therefore, current flows through the MTJ 1 a in the column defined by the word line 11 a and the row defined by the bit line 3.
  • the magnetoresistance of the MTJ 1a depends on the direction of magnetisation of the free layer 23.
  • the magnetisation of the free layer 23 is arranged parallel to the magnetisation of the pinned layer 25, there is an equal density of states across the dielectric barrier 27 for spin-up and spin-down electrons. This results in a high probability of tunnelling across the barrier 27, resulting in low resistance state.
  • the magnetisation of the free layer 23 is arranged anti-parallel to the magnetisation of the pinned layer 25, the density of states across the barrier 27 is not equal for spin-up and spin-down electrons. This reduces the probability of tunnelling across the barrier 27, resulting in a high resistance state.
  • the resistance of the memory cell 13a is compared with an associated reference memory cell (not shown) through sense circuitry (not shown). In this way, the state of the memory cell 13a can be determined.
  • the size of the above-described memory cell 13a is limited by the available power. This is because, as the size of the MTJ decreases, the coercivity of the free layer 23 increases, increasing the current required through the bit lines 3 and the digit lines 5 to switch the memory cell 13a.
  • half-selected MTJs i.e. the MTJs in the column of the selected digit line or row of the selected bit line
  • this writing method suffers from a small writing margin due to shape variations in the free layer.
  • STT switching MRAMs can reduce the required power for a given cell size.
  • the current required for writing in the nano-second regime can be many times larger than the DC threshold current.
  • the memory array is a magnetic random access memory (MRAM).
  • MRAM magnetic random access memory
  • the memory array is made up of a plurality of word lines 53, defining a first dimension of the array, in this example columns of the array, and a plurality of bit lines 31, overlying and perpendicular to the word lines 53, defining a second dimension of the array, in this example rows of the array.
  • a plurality of magnetic tunnel junctions (MTJs) 37 having stacked layers are connected to the underside of each bit line 31, in spaces between the word lines 53.
  • MTJs magnetic tunnel junctions
  • the bit lines 31 are arranged in a first direction, herein defined as the x-axis.
  • the word lines 53 are arranged in a second direction, herein defined as the y-axis
  • a plurality of assist current lines 33 are arranged parallel to the x-axis.
  • the assist current lines 33 overlie the bit lines 31 and are electrically isolated from the bit lines 31 by an insulating matrix 35.
  • each MTJ 37 is formed in a pillar defined by sidewalls 38 and has an elliptical base having a short axis L 1 and a long axis L 2 .
  • the pillar has a uniform cross section up its height i.e. a uniform cross section in the x-y plane.
  • the difference in length between the long axis L 2 and the short axis L 1 provides magnetic shape anisotropy.
  • the ratio of the short axis L 1 length to the long axis L 2 length is 1:2. Therefore, each MTJ 37 has a magnetic easy axis parallel to the long axis, i.e. parallel to the x-axis, and a magnetic hard axis parallel to the short axis, i.e. parallel to the y-axis.
  • each MTJ 37 is connected to the underside of a bit line 31.
  • the assist current line 33 is above the bit line 31.
  • the MTJs 37 are electrically isolated from the assist current lines 33.
  • An underside of each MTJ 37 is connected to a bottom electrode 39.
  • a via 41 connects each bottom electrode 39 to an active region 43 in a substrate 45.
  • the active regions 43 define areas within which diffusion of charge carriers can occur in the substrate 45.
  • the active regions 43 are isolated from one another in the substrate 45 by shallow trench isolation (STI) regions 47.
  • STI shallow trench isolation
  • a sense line 49 runs parallel to and underneath each bit line 31.
  • the sense lines 49 are separated from the bit lines 31, the bottom electrodes 39, and vias 41 by an insulating matrix 50.
  • a via 51 connects each active region 43 to the sense line 49 above it.
  • the word lines 53 are provided on the substrate 45 and are isolated therefrom by a gate oxide 53a.
  • the word lines 53 are arranged perpendicular to the bit lines 31, the assist current lines 33, and the sense lines 49.
  • the word lines 53 are separated from the sense lines 49 by an insulating matrix 55.
  • MTJs 37 are provided alternately between neighbouring pairs of the word lines 53.
  • a first MTJ 37 1 is provided between a first word line (not shown) and a second, adjacent word line 53 2
  • a second MTJ 37 2 is provided between third and fourth word lines 53 3 , 53 4
  • a third MTJ 37 3 is provided between fifth and sixth word lines 53 5 , 53 6 .
  • a fourth MTJ 37 4 is provided between second and third words lines 53 2 , 53 3 , a fifth MTJ 37 5 is provided between fourth and fifth bit lines 53 4 , 53 5 and a sixth MTJ 37 6 is provided between a sixth word line 53 6 and a seventh, adjacent word line (not shown).
  • Neighbouring MTJs 37 on each bit line 31 are arranged into pairs 59.
  • each pair of MTJs 59 has an active region 43 1 running between the respective vias 41 1 , 41 2 of two MTJs 37a, 37b.
  • STI regions 47 separate the active region 43 1 for each pair 59.
  • the via 51 1 connecting the active region 43 1 to the sense line 49 is provided between the word lines 53 2 , 53 3 that are in area defined by the pair 59.
  • a source region 61 is provided in the active region 43 below each via 41 connecting the bottom electrode 39 to the active region 43.
  • a drain region 63 is provided in the active region 43 below each via 51 connecting the sense line 49 to the active region 43. Therefore, each active region 43 provides two source regions 61 and one drain region 63. Conduction between each source region 61 and the drain region 63 occurs through the word line 53 between said regions. Therefore, said word line 53 serves as a gate 65 of an isolation transistor 81, and one isolation transistor 81 is provided for each MTJ 37.
  • a memory cell 66 is defined by one MTJ 37 and a respective transistor.
  • the drain region 63 of the transistor is shared between neighbouring memory cells 66.
  • the memory cell 66 has an area 8F 2 .
  • the feature size F of the memory array may be 100 nm or less.
  • the separation between the bit line 31 and the assist current line 33 is in the range 20 nm to 100 nm.
  • the bit line 31 and the assist current line 33 are made of a conductive material, such as copper or tungsten.
  • the insulating matrix 35 is silicon dioxide (SiO 2 ).
  • the MTJ 37 comprises a sequence of layers, including a capping layer 82, a free layer 83, a tunnel barrier layer 84, a pinned layer 85, a pinning layer 87, and a buffer layer 89.
  • the capping layer 82 is furthest from the substrate 45 and the buffer layer 89 is closest to the substrate 45.
  • the free layer 83 is formed magnesium oxide (MgO) and is sufficiently thin that electrons can tunnel through it.
  • MgO magnesium oxide
  • the pinned layer 85 is a synthetic antiferromagnet (SAF).
  • SAF 85 comprises a first ferromagnetic sub-layer 91, having a first magnetisation, and a second ferromagnetic sub-layer 93, having a second magnetisation, separated by an antiferromagnetic layer 95.
  • the first magnetisation and the second magnetisation are unequal in magnitude, and are antiparallel to one another.
  • the second ferromagnetic sub-layer 93 is a thicker than the first ferromagnetic sub-layer 91, therefore the second magnetisation has a larger magnitude than the first magnetisation.
  • the antiferromagnetic layer 95 couples the first ferromagnetic sub-layer 91 and the second ferromagnetic sub-layer 93.
  • the first magnetisation and the second magnetisation are aligned parallel to the easy axis of the MTJ 37 i.e. parallel to the x-axis. Therefore, the SAF has a small net magnetisation in the x-direction.
  • the pinned layer 85 has a relatively high coercivity.
  • the pinning layer 87 comprises an antiferromagnetic material.
  • the pinning layer 87 pins the magnetisation of the pinned layer 85, to prevent the magnetisation of the pinned layer 85 from switching on application of a magnetic field or a switching current.
  • the MTJ 37 When the magnetisation of the free layer 83 is parallel to the magnetisation of the first ferromagnetic sub-layer 91 of the pinned layer 85, the MTJ 37 has a relatively low magnetoresistance. When the magnetisation of the free layer 83 is anti-parallel to the magnetisation of the first ferromagnetic sub-layer 91 of the pinned layer 85, the MTJ 37 has a relatively high magnetoresistance.
  • the capping layer 82 is formed of a non-magnetic metal, for example copper (Cu) or tantalum (Ta), and has a thickness of about 10 nm.
  • the capping layer 82 may be formed of two layers of tantalum each having a thickness of 5 nm separated by a layer of copper having a thickness of 10 nm i.e. Ta(5 nm)/Cu(10 nm)/Ta(5 nm).
  • the free layer 83 is formed of cobalt iron boron (CoFeB) and has a thickness of about 3 nm.
  • the tunnel barrier layer 84 is formed of magnesium oxide (MgO).
  • MgO magnesium oxide
  • other dielectric materials such as aluminium oxide (AlO x ), silicon dioxide (SiO 2 ), and aluminium nitride (A1N)
  • AlO x aluminium oxide
  • SiO 2 silicon dioxide
  • A1N aluminium nitride
  • the tunnel barrier layer 84 has a thickness of 2 nm. In other examples, the thickness of the tunnel barrier layer 84 can be in the range 1 nm to 2 nm.
  • the first ferromagnetic sub-layer 91 is formed of cobalt iron boron (CoFeB) and has a thickness of about 4 nm.
  • the coupling layer 95 is formed of rubidium (Ru) and has a thickness of about 0.8 nm.
  • the second ferromagnetic sub-layer 93 is formed of cobalt iron (CoFe) and has a thickness of about 6 nm.
  • the pinning layer comprises platinum manganese (PtMn) and has a thickness of about 15 nm.
  • PtMn is preferred because it has a high blocking temperature and a high exchange biasing field, which improve the thermal stability of the MTJ 37.
  • other antiferromagnetic materials such as iridium manganese (IrMn), nickel manganese (NiMn) and palladium manganese (PdMn) can be used.
  • the buffer layer 89 is formed of at least one non-magnetic conductive layer and has a thickness between 10 nm and 20nm.
  • the buffer layer 89 can be formed of two layers of tantalum each having a thickness of 5 nm separated by a layer of copper having a thickness of 10 nm, and an overlying layer of nickel-iron having a thickness of 5 nm separated from the copper layer by one of the tantalum layers i.e. Ta(5 nm)/Cu(10 nm)/Ta(5 nm)/NiFe(5 nm).
  • the two tantalum layers may be separated by a gold layer having a thickness of 10 nm i.e.
  • the buffer layer 89 may be formed of a layer of tantalum having a thickness of 5 nm and a layer of nickel-iron having a thickness of 5nm i.e. Ta(5 nm)/NiFe(5 nm).
  • the nickel-iron layer is a seed layer for the pinning layer 87.
  • the long and short axes of the elliptical cross section of the MTJ 37 in the x-y plane have dimensions 100 nm and 50 nm respectively.
  • the ratio of magnetoresistance for the relatively high resistance state and the relatively low resistance state can approach 3:1 for the above-described MTJ 37. This can provide an MRAM having a high signal to noise ratio.
  • the assist current line 33 and the free layer 83 are separated by a distance dependent upon the anisotropy magnetic field of the free layer 83, and the current through the assist current line 33.
  • the anisotropy magnetic field can be determined by measuring the hysteresis loop of the free layer 83 when a magnetic field is applied to the magnetic hard axis of the free layer 83.
  • the magnitude of the assist magnetic field may be one tenth of the anisotropy magnetic field.
  • the anisotropy magnetic field of the free layer 83 is typically 300 to 400 Oe. Therefore, the assist magnetic field is 30 to 40 Oe.
  • H A the assist magnetic field
  • I A the current in the assist current line 33
  • r the distance between the assist current line 33 and the free layer 83.
  • the maximum current density that can be provided by a copper wire is of the order of 10 6 A/cm 2 .
  • I A is of the order of 10 -10 A.
  • the distance between the assist current line 33 and the MTJ 37 is of the order of 100 nm.
  • control circuitry for the memory array is shown.
  • a write driver 67 and a sense amplifier 68 are provided for each row of the memory array.
  • Each bit line 31 is connected to a first output 69 of a respective write driver 67.
  • Each sense line 49 is connected to a second output 70 of the respective write driver 67.
  • Each bit line 31 is also connected to a first input/output port 71 of the respective sense amplifier 68.
  • a connection 72 is provided between a second output of the sense amplifier 68 and a first input of the respective write driver 67.
  • the write driver 67 has a second input 73 for applying a write amplifier enable (WAE) voltage.
  • WAE write amplifier enable
  • the sense amplifier 68 has a second input 74 for receiving a sense amplifier enable (SAE) voltage.
  • the sense amplifier 68 has a third input/output port 75 for applying a sense amplifier input/output (SAIO) voltage.
  • An assist driver 78 is provided for each row of the array.
  • Each assist driver 78 has a first input connected to an assist current line 33.
  • a single word line driver 80 is provided. Each word line 53 is connected to a respective output of word line driver 80.
  • Each MTJ 37 connects a bit line 31 to the sense line 49 in the same row, through a single isolation transistor 81.
  • the base of the isolation transistor 81 is connected to a single word line 53.
  • Current will flow through the MTJ 37 when a bias is applied to the word line 53 defining the column of the MTJ 37, and a bias is applied to the bit line 31 or sense line 49 defining the row of the MTJ 37.
  • each MTJ 37 is addressable by a single word line 53 and a single bit line 31 or sense line 49.
  • Figure 6 illustrates biases which are applied to and measured in the memory array during a read cycle.
  • a first plot 101 is of a word line bias against time.
  • a second plot 103 is of a sense amplifier enable (SAE) bias applied to the second input 74 of the sense amplifier 68 against time.
  • a third plot 105 1 and a fourth plot 105 2 are of the voltage response on the bit line 31 against time and the sense amplifier input/output (SAIO) bias against time respectively, when the magnetisation of the free layer 83 and the magnetisation of the pinned layer 85 are parallel.
  • a fifth plot 107 1 and a sixth plot 107 2 are of the voltage response on the bit line 31 against time and the SAIO bias against time respectively, when the magnetisation of the free layer 83 and the magnetisation of the pinned layer 85 are antiparallel.
  • V W is applied by the word line driver 80 to the word line (WL) 53 corresponding to the column of the memory cell 66.
  • V W may be in the range 1 V to 3 V. This opens the isolation transistors 81 in the column of the array.
  • a bias V B is applied by the write driver 67 to the bit line (BL) 31 corresponding to the row of the memory cell.
  • V B is about 0.4 V.
  • the sense line (SL) 49 corresponding to the row of the memory cell is held a ground.
  • the bias V B is removed.
  • the voltage response on the bit line 31 decreases to ground in about 1 ns. This is because, when the magnetisation of the free layer 83 and the magnetisation of the pinned layer 85 are parallel, the magnetoresistance of the MTJ 37 (and thus the measured voltage response) is relatively low, thus the voltage response is relatively fast.
  • the voltage response on the bit line 31 decreases to ground in about 2 to 3 ns. This is because, when the magnetisation of the free layer 83 and the magnetisation of the pinned layer 85 are anti-parallel, the magnetoresistance of the MTJ 37 (and thus the measured voltage response) is relatively high, thus the voltage response is relatively slow.
  • V ref may be about 0.5 V B . In this example, V ref is 0.2V.
  • the sense amplifier input/output (SAIO) at the third input/output port 75 of the sense amplifier 68 is set to be low.
  • t R1 is 1 ns
  • t R2 is 2.5 ns
  • t R3 is 3.5 ns
  • t R4 is 7.5 ns
  • t R5 is 9 ns
  • t R6 is 10 ns.
  • the direction of magnetisation of the free layer 83 determines the output of the third input/output port 75 of the sense amplifier 68. If the free layer 83 is parallel to the pinned layer 85, the output of the sense amplifier 68 is '0'. If the free layer 83 is anti-parallel to the pinned layer 85, the output of the sense amplifier 68 is '1'.
  • Figure 7 illustrates biases which are applied to the memory array during a write cycle.
  • a seventh plot 109 is of an assist current line (AL) bias against time.
  • An eighth plot 111 is of a word line (WL) bias against time.
  • a ninth plot 113 is of a write amplifier enable (WAE) bias against time.
  • a tenth plot 115 and an eleventh plot 117 are of an SAIO bias applied to the memory cell 66 against time and of biases applied to the bit line (BL) and sense line (SL) against time respectively, when the magnetisation of the free layer 83 switches from anti-parallel to the magnetisation of the pinned layer 85 to parallel to the magnetisation of the pinned layer 85 (AP to P switching).
  • a twelfth plot 119 and a thirteenth plot 121 are of an SAIO bias applied to the memory cell 66 against time and of biases applied to the bit line (BL) and sense line (SL) against time respectively, when the magnetisation of the free layer 83 switches from parallel to the magnetisation of the pinned layer 85 to anti-parallel to the magnetisation of the pinned layer 85 (P to AP switching).
  • V A is applied by the assist driver 78 to the assist current line 33 that corresponds to the row of the memory cell 66.
  • the magnitude of V A is chosen to provide the required assist magnetic field in the free layer 83. A value of V A can be found by routine experiment.
  • V W is applied by the word line driver 80 to the word line 53 that corresponds to the column of the memory cell 66.
  • V W may be in the range 1V to 3V. This opens the isolation transistors 81 in the column of the array.
  • the SAIO bias is applied to the third input/output port 75 of the sense amplifier 68 corresponding to the row of the memory cell 66.
  • the SAIO bias is held at ground.
  • the SAIO bias is held at V S .
  • the connection 72 transmits this signal from the second output of the sense amplifier 68 to the first input of the write driver 67.
  • the WAE bias is applied to the write driver 67 corresponding to the row of the memory cell 66. This enables the write driver 67 to apply a bias to either the bit line 31 or the sense line 49, depending on the output SAIO of the sense amplifier 68.
  • the write driver 67 when SAIO is held at ground, at time t W3 the write driver 67 applies a bias V B to the bit line 31, and the sense line 49 is held at ground. Therefore, the write driver 67 drives current from the sense line 49 to the bit line 31. This causes the free layer 83 to switch from AP to P.
  • the write driver 67 when SAIO is held at V S , at time t W3 the write driver 67 applies a bias V B to the sense line 49, and the bit line 31 is held at ground. Therefore, the write driver 67 drives current from the bit line 31 to the sense line 49. This causes the free layer 83 to switch from P to AP.
  • V B may be in the range 1 V to 1.5 V, and has approximately the same value for P to AP switching as for AP to P switching.
  • the AL bias is removed.
  • the BL or SL bias is removed.
  • the WL bias is removed.
  • t W1 is 1 ns
  • t W2 is 2 ns
  • t W3 is 3 ns
  • t W4 is 4 ns
  • t W5 is 8 ns
  • t W6 is 9 ns
  • t W7 is 10 ns.
  • Figures 8A and 8B illustrate the current I A through the assist current line 33 ( Figure 4) and the current I MTJ through the MTJ 37 ( Figure 4) at times of the write cycle for AP to P switching and P to AP switching respectively.
  • Figures 9A and 9B illustrate magnetisations M 1 , M 2 of the free layer 83 at times of the write cycle for AP to P switching and P to AP switching respectively.
  • I A1 may be of the order of 100 ⁇ A.
  • the current I A in the assist current line 33 is held at I A1 between time t W2 and t W4 .
  • the current I A induces an assist magnetic field H A in the free layer 83.
  • the magnetic field H A is parallel to the magnetic hard axis of the free layer 83.
  • application of the field H A causes the magnetisation M 1 of the free layer 83 to rotate anticlockwise by an angle ⁇ in the plane of the free layer 83.
  • the current I MTJ in the MTJ 37 is ramped up to a magnitude I MTJ1 .
  • the current I MTJ in the MTJ 37 is held at I MTJ1 between time t W3 and t W6 .
  • the current I MTJ flows from the free layer 83 to the pinned layer 85. Therefore, electrons that are spin-polarised by the pinned layer 85 are injected into the free layer 83.
  • the spin transferred by these electrons causes precession of the magnetisation M 1 of the free layer 83 about a precession axis P 1 . Therefore, the magnetisation M 1 rotates around the precession axis P 1 .
  • the precession axis P 1 and therefore the time average of the magnetisation M 1 , is rotated further anticlockwise in the plane of the free layer 83. This rotation is assisted by the magnetic field H A .
  • the magnetisation M 1 of the free layer 83 continues to rotate around the precession axis P 1 .
  • the precession axis P 1 of the magnetisation M 1 is perpendicular to the initial direction of the magnetisation M 1 i.e. it is parallel to the magnetic hard axis of the free layer 83 and to the assist magnetic field H A .
  • the angle of the magnetisation M 1 around the precession axis P 1 gradually increases, and the precession axis P 1 suddenly rotates further anticlockwise.
  • the current I MTJ still causes the precession axis P 1 to rotate clockwise. Therefore, it is preferable that the assist current I A is removed so that it does not act to prevent the precession axis P 1 rotating further anticlockwise.
  • the current I A in the assist current line 33 is ramped down to zero.
  • the assist current I A is zero, therefore there is no assist magnetic field H A .
  • the switching current I MTJ remains, causing the precession axis P 1 of the magnetisation M 1 of the free layer 83 to rotate further anticlockwise.
  • the current I A in the assist current line 33 is ramped up to a magnitude I A2 .
  • the current I A2 has the same magnitude as I A1 , but is in the opposite direction.
  • the current I A in the assist current line 33 is held at I A2 between time t W2 and t W4 .
  • the current I A induces an assist magnetic field H A in the free layer 83.
  • the magnetic field H A is parallel to the magnetic hard axis of the free layer 83.
  • application of the field H A causes the magnetisation M 1 of the free layer 83 to rotate anticlockwise by an angle ⁇ in the plane of the free layer 83.
  • the current I MTJ in the MTJ 37 is ramped up to a magnitude I MTJ2 .
  • the current I MTJ in the MTJ 37 is held at I MTJ2 between time t W3 and t W6 .
  • I MTJ2 has approximately the same magnitude as I MTJ1 .
  • the current I MTJ flows from the pinned layer 85 to the free layer 83. Therefore, spin-polarised electrons are scattered from the pinned layer 85 and injected into the free layer 83. The spin transferred by these electrons causes precession of the magnetisation M 1 of the free layer 83. Therefore, the magnetisation M 1 rotates around the precession axis. The precession axis P 1 , and therefore the time average of the magnetisation M 1 , is rotated further anticlockwise in the plane of the free layer 83. This rotation is assisted by the magnetic field H A .
  • the magnetisation M 1 of the free layer 83 continues to rotate around the precession axis P 1 .
  • the precession axis P 1 of the magnetisation M 1 is perpendicular to the initial direction of the magnetisation M 1 i.e. it is parallel to the magnetic hard axis of the free layer 83 and to the assist magnetic field H A .
  • the angle of the magnetisation M 1 around the precession axis P 1 gradually increases, and the precession axis P 1 suddenly rotates further anticlockwise.
  • the current I MTJ still causes the precession axis P 1 to rotate anticlockwise. Therefore, it is preferable that the assist current I A is removed so that it does not act to prevent the precession axis P 1 rotating further anticlockwise.
  • the current I A in the assist current line 33 is ramped down to zero.
  • the assist current I A is zero, therefore there is no assist magnetic field H A .
  • the switching current I MTJ remains, causing the precession axis P 1 of the free layer 83 to rotate further clockwise.
  • the current required to cause STT switching is related to the duration of the current pulse, as described above, and to the initial direction of the magnetisation of the free layer 83.
  • the assist current I A can be applied before the STT switching current I MTJ , to rotate the magnetisation of the free layer and thus lower the STT switching current.
  • the leading or rising edge of the assist current line bias occurs before the leading or rising edge of the bit line or sense line bias and the trailing or falling edge of the assist current line bias occurs after the leading or rising edge of the bit line bias or sense line bias.
  • the assist current I A is switched off during the STT switching process. This is because if the assist magnetic field H A is present after STT switching ends, the domain structure of the free layer 83 becomes unstable. This causes an increase in the probability distribution of the STT switching current in the nanosecond regime, and a narrow current margin for the STT writing process. Therefore, in this example the trailing or falling edge of the assist current line bias occurs before the trailing or falling edge of the bit line or sense line bias.
  • the direction of the assist magnetic field H A can be aligned in either of two directions parallel to the magnetic hard axis of the free layer 83depending on the direction of the switching current I MTJ .
  • the switching current I MTJ induces an Ampere field in the free layer 83 and aligning the assist magnetic field H A to eliminate the Ampere field in the free layer 83 can result in a more favourable (e.g. more stable) domain structure in the free layer 83 for STT switching. Therefore, the assist magnetic field H A for AP to P switching can be arranged to be in the opposite direction to the assist magnetic field H A for P to AP switching.
  • the effect of the Ampere field is not significant, and so the assist magnetic field H A can be aligned in the opposite direction, i.e. without counteracting the Ampere field, for STT switching.
  • FIGS. 10A and 10B respective simulation results for STT switching with and without an assist magnetic field are shown.
  • the simulation is of STT switching at a temperature of 300K, using a spin-polarised current having a polarisation of 0.5.
  • the simulation results show normalised current I/I c0 -1 required for STT switching against the inverse of the pulse duration t p -1 .
  • a switching current 127 for a given pulse duration when an assist magnetic field pulse of magnitude 80 Oe is used can be up to 50% less than a switching current 129 when no assist magnetic field is used.
  • a switching current 131 for a given pulse duration when an assist magnetic field pulse of magnitude 80 Oe is used can be up to 100% less than a switching current 133 when no assist magnetic field is used.
  • Figures 11A, 11C, 11E and 11G show a cross section of the memory array shown in Figure 3A taken along line B-B' during stages of the fabrication process.
  • Figures 11B, 11D, 11F and 11H show a cross section of the Figure 3A memory array taken along line C-C' during stages of the fabrication process.
  • an STI etch process is used to create shallow trenches 47 in the silicon substrate 45, which are filled with dielectric material. Areas of the substrate that do not comprise the STI regions define the active regions 43.
  • Gate insulating layers 53a and word lines 53 are sequentially stacked to form gate stacks on the substrate and STI regions.
  • Gate spacers 53b are formed on the sidewalls and on top of the gate stack.
  • Impurity ions are implanted into the substrate 45 to form source region 61 and drain regions 63 for isolation transistors.
  • a first insulating matrix 55 is formed on the entire surface of the substrate.
  • the first insulating matrix 55 is successively patterned and etched to open vias 51 that expose a portion of each drain region 63.
  • One or more conductive layers are then formed on the substrate and fill the vias 51.
  • the upper portion of the conductive layer is then removed, typically using a planarisation process, to remove all of the conductive layer except that formed in the vias 51, and expose a top surface of the first insulating matrix 55.
  • Another conductive layer is then formed on the first insulating matrix 55.
  • the conductive layer is patterned then etched to form sense lines 49 running perpendicular to the word lines and contacting the conductive layer in the via 51.
  • a second insulating matrix 50 is then formed on the structure.
  • vias 41 are formed in the first insulating matrix and the second insulating matrix to contact the surface of each source region 61.
  • a conductive layer is formed on the substrate.
  • the conductive layer is then patterned and etched to form bottom electrodes 39 contacting vias 41.
  • the MTJs 37 are then fabricated according to the following steps.
  • the buffer layer 89 and the antiferromagnetic pinning layer 87 are deposited in series.
  • the magnetisation of the pinning layer 87 is set by heating it and applying an external magnetic field to it, which is maintained as the pinning layer 87 cools.
  • the first ferromagnetic sub layer 91, antiferromagnetic coupling layer 95 and second ferromagnetic sub-layer 93 are then deposited in series over the pinning layer 87.
  • the barrier material is then deposited.
  • The can be achieved by r-f sputtering the material, or depositing magnesium and then oxidising the magnesium by a process such as plasma oxidation.
  • the ferromagnetic free layer 83 is then deposited.
  • the capping layer 82 is deposited on the ferromagnetic free layer 83.
  • Patterning may be performed by depositing a layer of photoresist on the protective capping layer, using photolithography to pattern the photoresist, and removing the unprotected material.
  • a third insulating matrix 123 is then formed over the upper surface of the substrate including the MTJ 37.
  • the third insulating matrix 123 is patterned to form a bit line contact holes 125 that exposes the surfaces of the capping layers 82.
  • a conductive layer is then formed on the substrate and in bit line contact holes 125.
  • the conductive layer is then patterned and etched to form bit lines 31 that cover the bit line contact holes 125, and are parallel to the sense lines 49.
  • a fourth insulating matrix 35 is formed on the entire surface of the substrate.
  • a conductive layer is formed on the substrate, and is subsequently patterned and etched to form assist current lines 33 above and parallel to the bit lines 31.
  • the conductive layers can be formed using a method well known in the art such as chemical vapour deposition, physical vapour deposition, plasma enhanced chemical vapour deposition, or sputtering.
  • the memory array is an MRAM.
  • bit lines 201 are arranged in a first direction, herein defined as the x-axis.
  • the bit lines 201 define a first dimension of the array, in this example rows of the array.
  • An assist current line 203 overlies each bit lines 201, and is electrically isolated from the respectivebit line 201 by an insulating matrix 205.
  • a plurality of MTJs 207 are provided.
  • the MTJs 207 have the same structure as the MTJs 37 described above with respect the first embodiment.
  • the MTJs 207 are arranged with the magnetic easy axis parallel to the bit lines 201, i.e. parallel to the x-axis.
  • Each MTJ 207 is connected to the underside of a bit line 201.
  • the MTJs 207 are electrically isolated from the assist current lines 203.
  • each MTJ is connected to a bottom electrode 209.
  • the bottom electrode 209 is a rectangle in the x-y plane having long and short sides.
  • the long and short sides of the bottom electrode 209 are approximately the same size as the long and short axes of the MTJ 207.
  • a via 211 connects each bottom electrode 209 to an active region 213 on a substrate 215.
  • the active regions 213 are electrically isolated from one another on the substrate 215 by STI regions 216.
  • a sense line 217 runs underneath each bit line.
  • the sense line 217 does not contact the bit lines 201, the MTJs or the bottom electrodes 209.
  • a via 219 connect the sense line 217 to the active region 213.
  • each sense line 217 weaves side to side about a longitudinal axis.
  • the longitudinal axis is parallel to the x-axis.
  • Each active region 213 also weaves side to side about a longitudinal axis that is parallel to the x-axis.
  • the pitch of the weave of the sense line 217 is the same as the pitch of the weave of the active region 213.
  • the weaves are 180° out of phase such that the weave of the sense line 217 and the weave of the active layer 213 coincide at and are contacted by vias 219.
  • the vias 211 connecting the bottom electrodes 209 to the active region 213 are provided. Therefore, the sense line 217 is spaced apart from the vias 211 connecting the bottom electrode 209 to the active region 213.
  • a plurality of word lines 221 are provided on the substrate 215 and are isolated therefrom by a gate oxide 221a.
  • the word lines 221 are perpendicular to the bit lines 201.
  • the word lines 221 are arranged in a second direction, herein defined as the y-axis.
  • the word lines 221 are isolated from the sense lines by an insulating matrix 223.
  • Each word line 221 is provided between the vias 219 connecting the sense line 217 to the active region 213 and the vias 211 connecting the bottom electrode 209 to the active region 213.
  • the word lines 221 define a second dimension of the array, in this example columns of the array. Two word lines 221 are provided for each MTJ 207. Therefore, each column of the array is defined by the two word lines 221 on either side of a column of MTJs 207.
  • a source region 227 is provided in the active region 213 below each via 211 connecting the bottom electrode 209 to the active region 213.
  • a drain region 229 is provided in the active region 213 below each via 219 connecting the sense line 217 to the active region 213. Conduction between each source region 227 and the drain region 229 occurs through the word line 221 between said regions. Therefore, said word line 221 serves as a gate 231 of an isolation transistor 233.
  • each memory cell 235 is defined by one MTJ 207 and two transistors 233.
  • the drain region 229 of each transistor 233 is shared between neighbouring memory cells 235.
  • the area of each memory cell 235 is 8F 2 .
  • the feature size F of the memory array is between 50 nm and 100 nm.
  • control circuitry for the memory array is shown.
  • a write driver 236 and a sense amplifier 237 are provided for each row of the memory array.
  • Each bit line 201 is connected to a first output 238 of the respective write driver 236.
  • Each sense line 217 is connected to a second output 239 of the respective write driver 237.
  • Each bit line 201 is also connected to a first input/output port 240 of the respective sense amplifier 237.
  • a connection 241 is provided between a second output of the sense amplifier 237 and a first input of the respective write driver 236.
  • the write driver 236 has a second input 242 for applying a write amplifier enable (WAE) voltage.
  • WAE write amplifier enable
  • the sense amplifier 237 has a second input 243 for applying a sense amplifier enable (SAE) voltage.
  • the sense amplifier 237 has a third input/output port 244 for applying a sense amplifier input/output (SAIO) voltage.
  • An assist driver 246 is provided for each row of the array. Each assist driver 246 has a first input connected to an assist current line 203.
  • a single word line driver 245 is provided. Each word line 221 is connected to a respective output of word line driver 245.
  • Each MTJ 207 connects a bit line 201 to the sense line 217 in the same row, through one of two isolation transistors 233 either side of the MTJ 207.
  • the base of each isolation transistor 233 is connected to a single word line 221.
  • Current will flow through the MTJ 207 when a bias is applied to both of the word lines 221 defining the column the memory cell 235, and a bias is applied to the bit line 201 or sense line 203 defining the row of the MTJ 207.
  • each MTJ 207 is addressable by two word lines 221 and a single bit line 201 or sense line 217.
  • Reading and writing of the memory cell shown in Figures 12A to 12C is the same as that described earlier with respect to the memory cell shown in Figures 3A to 3D.
  • MTJ 247 taken through the x-z plane is shown.
  • the MTJ 247 can be used instead of MTJ 37 in the first embodiment or MTJ 207 in the second embodiment.
  • the MTJ 247 comprises a sequence of layers, including a free layer 249, a tunnel barrier layer 251, and a pinned layer 253.
  • the free layer is furthest from the substrate and the pinning layer is closest to the substrate.
  • the free layer 249 comprises a ferromagnetic material.
  • the free layer 249 has a relatively low coercivity, so that it can be switched on application of a switching current or magnetic field.
  • the tunnel barrier layer 251 is formed of an insulating material, such as magnesium oxide (MgO), and is sufficiently thin that electrons can tunnel through it.
  • MgO magnesium oxide
  • the pinner layer 253 comprises a ferromagnetic material.
  • the pinned layer 253 is thicker than the free layer 249. This provides it with a higher coercivity than the free layer 249. Therefore, the free layer 249 is able to switch upon the application of the switching current and assist magnetic field, and the pinned layer 253 is not able to switch upon application of the switch current and assist magnetic field.
  • MTJ 255 a cross section in the x-z plane of another alternative MTJ 255 is shown.
  • the MTJ 255 can also be used instead of the MTJ 37 in the first embodiment or the MTJ 207 in the second embodiment.
  • the MTJ 255 comprises a sequence of layers, including a free layer 257, a tunnel barrier layer 259, a pinned layer 261, and a pinning layer 263.
  • the free layer is furthest from the substrate and the pinning layer is closest to the substrate.
  • the free layer 257 comprises a ferromagnetic material.
  • the free layer 257 has a relatively low coercivity, so that it can be switched on application of a switching current or magnetic field.
  • the tunnel barrier layer 259 is formed of an insulating material, such as magnesium oxide (MgO), and is sufficiently thin that electrons can tunnel through it.
  • MgO magnesium oxide
  • the pinner layer 261 comprises a ferromagnetic material.
  • the pinned layer 261 has a relatively high coercivity, so that it is not switched on application of a switching current or magnetic field.
  • the pinning layer 263 comprises an antiferromagnetic material.
  • the pinning layer 263 pins the magnetisation of the pinned layer 261, to prevent the magnetisation of the pinned layer 261 from switching on application of a magnetic field or a switching current.
  • the alternative MTJs 247, 255 have the advantage of a simpler structure than the MTJ 37 used in the first embodiment and the MTJ 207 used in the second embodiment. Therefore, the alternative MTJs 247,255 are simpler to fabricate. However, the alternative MTJs 247, 255 do not exhibit a magnetoresistance ratio has high as that exhibited as the MTJ 37 and the MTJ 207.
  • the MTJ is provided with an additional ferromagnetic layer overlying the free layer.
  • the additional ferromagnetic layer is separated from the ferromagnetic layer by a non-magnetic conductor.
  • the additional ferromagnetic layer can increase the proportion of spin-polarised electrons injected into the free layer when current flows from the pinned layer to the free layer.
  • a spin valve is provided instead of an MTJ.
  • the spin valve comprises a sequence of layers, including a ferromagnetic free layer and a ferromagnetic pinned layer separated by a nonmagnetic conductor.
  • the strength and width of the assist current pulse can be adjusted depending on the magnetic properties of the free layer.
  • the orientation of the MTJs with respect to the bit line and sense line can be varied.
  • the assist current line should be parallel to the magnetic easy axis of the MTJs.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)
EP06113534A 2006-05-04 2006-05-04 Magnetic memory device Withdrawn EP1852873A1 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
EP06113534A EP1852873A1 (en) 2006-05-04 2006-05-04 Magnetic memory device
PT06118378T PT1863034E (pt) 2006-05-04 2006-08-03 Memória magnética de acesso aleatório
EP06118378A EP1863034B1 (en) 2006-05-04 2006-08-03 Magnetic memory device
DE602006019389T DE602006019389D1 (de) 2006-05-04 2006-08-03 Magnetspeichervorrichtung
TW095146660A TWI332662B (en) 2006-05-04 2006-12-13 Magnetic memory device and method of operating magnetic memory device
US11/638,379 US7738286B2 (en) 2006-05-04 2006-12-14 Magnetic memory device
CN2006101694759A CN101068036B (zh) 2006-05-04 2006-12-15 磁性存储装置
KR1020060128494A KR100856985B1 (ko) 2006-05-04 2006-12-15 자기 메모리 장치 및 자기 메모리 장치의 동작 및 기입 방법
JP2007090269A JP5295513B2 (ja) 2006-05-04 2007-03-30 磁気メモリ素子

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP06113534A EP1852873A1 (en) 2006-05-04 2006-05-04 Magnetic memory device

Publications (1)

Publication Number Publication Date
EP1852873A1 true EP1852873A1 (en) 2007-11-07

Family

ID=36889293

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06113534A Withdrawn EP1852873A1 (en) 2006-05-04 2006-05-04 Magnetic memory device

Country Status (4)

Country Link
EP (1) EP1852873A1 (pt)
CN (1) CN101068036B (pt)
DE (1) DE602006019389D1 (pt)
PT (1) PT1863034E (pt)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013071129A1 (en) * 2011-11-10 2013-05-16 Micron Technology, Inc. Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines
EP3123474A4 (en) * 2014-03-28 2017-11-29 Intel Corporation 6f2 non-volatile memory bitcell

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201027715A (en) * 2008-12-23 2010-07-16 Ibm Memory element
KR101161745B1 (ko) * 2009-06-05 2012-07-02 에스케이하이닉스 주식회사 반도체 메모리 장치
US8890266B2 (en) 2011-01-31 2014-11-18 Everspin Technologies, Inc. Fabrication process and layout for magnetic sensor arrays
US8450722B2 (en) * 2011-07-15 2013-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Magnetoresistive random access memory and method of making the same
KR102353133B1 (ko) * 2015-06-19 2022-01-19 인텔 코포레이션 캡핑된 자기 메모리
US10068945B2 (en) * 2015-09-30 2018-09-04 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure integrated with magnetic tunneling junction and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030007398A1 (en) * 2001-05-15 2003-01-09 Nve Corporation Current switched magnetoresistive memory cell
US6639830B1 (en) * 2002-10-22 2003-10-28 Btg International Ltd. Magnetic memory device
US20030214862A1 (en) * 2002-04-22 2003-11-20 Yoshiaki Asao Magnetic random access memory
US6753562B1 (en) * 2003-03-27 2004-06-22 Sharp Laboratories Of America, Inc. Spin transistor magnetic random access memory device
US20040228198A1 (en) * 2003-03-13 2004-11-18 Yuui Shimizu Semiconductor memory device including reference memory cell and control method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030007398A1 (en) * 2001-05-15 2003-01-09 Nve Corporation Current switched magnetoresistive memory cell
US20030214862A1 (en) * 2002-04-22 2003-11-20 Yoshiaki Asao Magnetic random access memory
US6639830B1 (en) * 2002-10-22 2003-10-28 Btg International Ltd. Magnetic memory device
US20040228198A1 (en) * 2003-03-13 2004-11-18 Yuui Shimizu Semiconductor memory device including reference memory cell and control method
US6753562B1 (en) * 2003-03-27 2004-06-22 Sharp Laboratories Of America, Inc. Spin transistor magnetic random access memory device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013071129A1 (en) * 2011-11-10 2013-05-16 Micron Technology, Inc. Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines
US8681529B2 (en) 2011-11-10 2014-03-25 Micron Technology, Inc. Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines
TWI494926B (zh) * 2011-11-10 2015-08-01 Micron Technology Inc 與具有各別選擇線之電阻式記憶體單元陣列相關聯之裝置及操作方法
US9378818B2 (en) 2011-11-10 2016-06-28 Micron Technology, Inc. Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines
US9548335B2 (en) 2011-11-10 2017-01-17 Micron Technology, Inc. Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines
EP3123474A4 (en) * 2014-03-28 2017-11-29 Intel Corporation 6f2 non-volatile memory bitcell

Also Published As

Publication number Publication date
PT1863034E (pt) 2011-04-11
CN101068036B (zh) 2010-08-11
DE602006019389D1 (de) 2011-02-17
CN101068036A (zh) 2007-11-07

Similar Documents

Publication Publication Date Title
EP1852874B1 (en) Magnetic memory device
EP1863034B1 (en) Magnetic memory device
KR102375641B1 (ko) 자기 랜덤 액세스 메모리 보조 디바이스 및 제조 방법
US7190611B2 (en) Spin-transfer multilayer stack containing magnetic layers with resettable magnetization
US8670271B2 (en) Magnetic stack having assist layers
US7755933B2 (en) Spin transfer MRAM device with separated CCP assisted writing
US7369428B2 (en) Methods of operating a magnetic random access memory device and related devices and structures
US7965543B2 (en) Method for reducing current density in a magnetoelectronic device
US20070085068A1 (en) Spin transfer based magnetic storage cells utilizing granular free layers and magnetic memories using such cells
US20120058575A1 (en) Low switching current dual spin filter (DSF) element for STT-RAM and a method for making the same
US7705340B2 (en) Inflected magnetoresistive structures and memory cells having inflected magnetoresistive structures
EP2320425B1 (en) Selection device for a spin transfer torque magnetoresistive random access memory
CN111834521A (zh) 磁性隧道结器件
EP1852873A1 (en) Magnetic memory device
JP2008066606A (ja) スピンメモリ及びスピンｆｅｔ

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA HR MK YU

AKX Designation fees paid
REG Reference to a national code

Ref country code: DE

Ref legal event code: 8566

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20080508