EP1844542B1 - Detecteur de phase numerique destine a une boucle a phase asservie - Google Patents
Detecteur de phase numerique destine a une boucle a phase asservie Download PDFInfo
- Publication number
- EP1844542B1 EP1844542B1 EP06717679A EP06717679A EP1844542B1 EP 1844542 B1 EP1844542 B1 EP 1844542B1 EP 06717679 A EP06717679 A EP 06717679A EP 06717679 A EP06717679 A EP 06717679A EP 1844542 B1 EP1844542 B1 EP 1844542B1
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- EP
- European Patent Office
- Prior art keywords
- digital
- phase
- signal
- detector
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- Prior art date
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- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000007812 deficiency Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/02—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal
- H03D3/24—Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
- H03D13/003—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
Definitions
- the present invention is generally in the field of electrical circuits. More particularly, the invention is in the field of phase locked loops.
- Phase locked loops are often used as frequency synthesizers in applications, such as communication systems, that require a precise signal frequency.
- the typical components of a phase locked loop include a phase detector, a frequency-controllable oscillator, and a loop filter.
- Phase detectors such as a charge pump phase detector and a sample-and-hold phase detector, are commonly implemented using analog circuitry.
- analog phase detectors suffer from the traditional limitations of analog circuitry, such as variation with process, temperature dependence, sensitivity to substrate coupling, and limitations caused by parasitics.
- phase detectors that use analog circuitry.
- conventional digital phase detectors often require multi-Gigahertz clocks or other types of circuit blocks that are undesirable.
- An example of a digital fractional phase detector is provided by EP 1 178 609 A2 to realize a frequency synthesizer architecture that naturally combines transmitter modulation capability with a wideband all-digital phase locked loop modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase domain.
- That known digital fractional phase detector is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the voltage controlled oscillator output clock and a reference clock by using a time-to-digital converter to express the time difference as a digital word for use by the frequency synthesizer.
- the present invention is directed to a digital phase detector for a phase locked loop.
- the present invention resolves the need in the art for a digital phase detector for a phase locked loop that overcomes the deficiencies of conventional phase detectors.
- a digital phase detector according to the invention is defined in claim 1.
- a digital phase detector includes a phase/frequency detector, where the phase/frequency detector is configured to receive a reference signal and a divided oscillator feedback signal and output a first pulse-width modulated signal and a second pulse-width modulated signal.
- the first pulse-width modulated signal can indicate that a phase of the divided oscillator feedback signal leads a phase of the reference signal, for example.
- the second pulse-width modulated signal can indicate that a phase of the divided oscillator feedback signal lags a phase of the reference signal, for example.
- An output of the digital phase detector can control a frequency of an output signal of a digitally controlled oscillator, for example.
- the digital phase detector also includes a first time-to-digital converter, where the first time-to-digital converter is coupled to the phase/frequency detector.
- the first time-to-digital converter is configured to receive and convert the first pulse-width modulated signal to a first digital number.
- the digital phase detector further includes a second time-to-digital converter coupled to the phase/frequency detector, where the second time-to-digital converter is configured to receive and convert the second pulse-width modulated signal to a second digital number.
- the digital phase detector further includes a summation element, where the summation element is configured to subtract the second digital number from the first digital number and output a digital phase error signal. A difference between the first digital number and the second digital number is proportional to a phase difference between the reference signal and the divided oscillator feedback signal.
- the present invention is directed to a digital phase detector for a phase locked loop.
- the following description contains specific information pertaining to the implementation of the present invention.
- the present invention provides an innovative digital phase detector for a phase locked loop, such as a digital phase locked loop.
- a phase locked loop including a digitally controlled oscillator is utilized in the present embodiment to illustrate the invention, the present invention's digital phase detector can also be used in phase locked loops that comprise other types of oscillators, such as voltage controlled oscillators.
- Phase locked loop 100 includes digital phase detector 102, loop filter 104, digitally controlled oscillator 106, and feedback divider 108.
- Phase locked loop 100 can be an all-digital phase locked loop.
- phase locked loop 100 can be a phase locked loop comprising one or more digital components, such as digital phase detector 102.
- Phase locked loop 100 can be configured to receive reference signal 110 and provide output signal 112, which is phase locked to reference signal 110.
- reference signal 110 which can be a digital reference signal
- digital phase detector 102 comprises a phase/frequency detector (not shown in Figure 1 ) coupled to two time-to-digital converters (not shown in Figure 1 ).
- Digital phase detector 102 can be configured to receive reference signal 110 at one input and receive a divided oscillator output signal outputted by feedback divider 108 at another input and output a digital phase error signal on line 116.
- the digital phase error signal outputted by digital phase detector 102 which corresponds to a difference in phase between reference signal 110 and the divided oscillator output signal outputted by feedback divider 108, is a digital number that is used to control the frequency of digitally controlled oscillator 106.
- the present invention provides a digital phase detector that advantageously avoids analog charge pumps, an analog filter, and analog control signals and is easy to implement.
- the present invention's digital phase detector will be discussed below in relation to Figure 2 .
- Loop filter 104 can be a digital loop filter, which can be an elliptical filter, and can be configured to receive the digital phase error signal outputted by digital phase detector 102, appropriately filter the digital phase error signal, and provide a digital tuning control signal on line 118.
- An elliptical filter provides a sharp roll-off, which advantageously increases noise attenuation and allows a wider bandwidth.
- a digital loop filter will not vary significantly with process or temperature and that has a filter area (on a semiconductor die) that will advantageously scale with technology.
- the output of loop filter 104 is coupled to the input of digitally controlled oscillator 106 via line 118.
- Digitally controlled oscillator 106 can be configured to receive a digital tuning control signal outputted on line 118 by loop filter 104, utilize the digital tuning control signal to appropriately adjust oscillator frequency, and provide output signal 112, which is phase locked to reference signal 110.
- output signal 112, which is outputted by digitally controlled oscillator 106 is coupled to the input of feedback divider 108 via line 120.
- Feedback divider 108 can be configured to receive output signal 112 on line 120, divide output signal 112 by an appropriate integer value in a manner known in the art, and output a divided oscillator feedback signal to digital phase detector 102 on line 114.
- FIG. 2 shows a block diagram of an exemplary digital phase detector in accordance with one embodiment of the present invention.
- Digital phase detector 202 and reference signal 210 in Figure 2 correspond, respectively, to digital phase detector 102 and reference signal 110 in phase locked loop 100 in Figure 1 .
- Digital phase detector 202 comprises phase/frequency detector 220 time-to-digital converters 222 and 224, and summation element 229.
- Phase/frequency detector 220 is configured to receive reference signal 210 at one input and divided oscillator feedback signal 226, which is outputted by feedback divider 108 in Figure 1 , at another input and compare the phase of reference signal 210 with the phase of divided oscillator feedback signal 226.
- Phase/frequency detector 220 can be further configured to output a pulse-width modulated up signal on line 228 when the phase of divided oscillator feedback signal 226 is leading the phase of reference signal 210 and to output a pulse-width modulated down signal when the phase of divided oscillator output signal 226 is lagging the phase of reference signal 210.
- the difference between the pulse-width modulated up signal and the pulse-width modulated down signal is proportional to the phase difference between reference signal 210 and divided oscillator feedback signal 226.
- phase/frequency detector 220 is coupled to time-to-digital converter 222 and time-to-digital converter 224 via respective lines 228 and 230.
- Time-to-digital converter 222 can be configured to receive and convert the pulse-width modulated up signal outputted by phase/frequency detector 220 to a digital number, and output the digital number on line 232.
- time-to-digital converter 224 can be configured to receive and convert the pulse-width modulated down signal outputted by phase/frequency detector 220 to a digital number, and output the digital number on line 234. Also shown in Figure 2 , time-to-digital converter 222 and time-to-digital converter 224 are coupled to summation element 229 via respective lines 232 and 234.
- Summation element 229 is configured to subtract the digital number on line 234, which corresponds to the pulse-width modulated down signal, from the digital number on line 232, which corresponds to the pulse-width modulated up signal, and output digital phase error signal 236, which is a digital representation of the phase difference between reference signal 210 and divided oscillator feedback signal 226.
- Phase/frequency detector 220 compares the phase of reference signal 210 to the phase of divided oscillator feedback signal 226 and outputs pulse-width modulated up and down signals on respective lines 228 and 230.
- Time-to-digital converter 222 converts the pulse width of the pulse-width modulated up signal into a digital number, which is inputted into summation element 229, while time-to-digital converter 224 similarly converts the pulse width of the pulse-width modulated down signal into a digital number, which is also inputted into summation element 229.
- digital phase error signal 236, is a digital number that is proportional to the phase difference between reference signal 210 and divided oscillator feedback signal 226.
- Digital phase error signal 236 is utilized to control the frequency of output signal 112, which is outputted by digitally controlled oscillator 106.
- the present invention combines a phase/frequency detector and time-to-digital converters to advantageously achieve a digital phase detector.
- the present invention achieves a digital phase detector that advantageously avoids undesirable conventional analog charge pumps, filters, and control signals and is easy to implement.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
Claims (13)
- Détecteur de phase numérique (102, 202) comprenant :un détecteur de phase/de fréquence (220), ledit détecteur de phase/de fréquence (220) étant configuré de façon à recevoir un signal de référence (110, 210) et un signal de rétroaction d'oscillateur divisé (226) et à délivrer en sortie un premier signal modulé en largeur d'impulsion et un second signal modulé en largeur d'impulsion ;un premier convertisseur temps-numérique (222) couplé à une sortie dudit détecteur de phase/de fréquence (220) ;un second convertisseur temps-numérique (224) couplé à la sortie dudit détecteur de phase/de fréquence (220) ; etun élément de sommation (229) ;dans lequel ledit premier convertisseur temps-numérique (222) est configuré de façon à recevoir et à convertir ledit premier signal modulé en largeur d'impulsion en un premier nombre numérique ;dans lequel ledit second convertisseur temps-numérique (224) est configuré de façon à recevoir et à convertir ledit second signal modulé en largeur d'impulsion en un second nombre numérique ; etdans lequel ledit élément de sommation (229) est configuré de façon à soustraire ledit second nombre numérique dudit premier nombre numérique et à délivrer en sortie un signal d'erreur de phase numérique (236).
- Détecteur de phase numérique (102, 202) selon la revendication 1, dans lequel ledit premier nombre numérique correspond à un changement de phase entre ledit signal de référence (210) et ledit signal de rétroaction d'oscillateur divisé (226).
- Détecteur de phase numérique (102, 202) selon la revendication 1, dans lequel la différence entre ledit premier nombre numérique et ledit second nombre numérique est proportionnelle à la différence de phase entre ledit signal de référence (210) et ledit signal de rétroaction d'oscillateur divisé (226).
- Détecteur de phase numérique (102, 202) selon la revendication 1, dans lequel ledit premier signal modulé en largeur d'impulsion indique que la phase dudit signal de rétroaction d'oscillateur divisé (226) est en avance par rapport à la phase dudit signal de référence (210).
- Détecteur de phase numérique (102, 202) selon la revendication 1, dans lequel ledit second signal modulé en largeur d'impulsion indique que la phase dudit signal de rétroaction d'oscillateur divisé (226) est en retard par rapport à la phase dudit signal de référence (210).
- Détecteur de phase numérique (102, 202) selon la revendication 1, dans lequel une sortie dudit détecteur de phase numérique (102, 202) commande la fréquence d'un signal de sortie (112) d'un oscillateur à commande numérique (106).
- Détecteur de phase numérique (102, 202) selon la revendication 6, dans lequel un filtre de boucle numérique (104) couple ladite sortie dudit détecteur de phase numérique (102, 202) audit oscillateur à commande numérique (106).
- Détecteur de phase numérique (102, 202) selon la revendication 7, dans lequel ledit filtre de boucle numérique (104) est un filtre elliptique.
- Boucle à verrouillage de phase (100) comprenant :le détecteur de phase numérique (102, 202) selon l'une quelconque des revendications 1 à 5, ledit détecteur de phase numérique (102, 202) étant configuré de façon à recevoir le signal de référence (210) et le signal de rétroaction d'oscillateur divisé (226) et à délivrer en sortie le signal d'erreur de phase numérique (236) ;dans laquelle ledit premier nombre numérique correspond à un changement de phase entre ledit signal de référence (210) et ledit signal de rétroaction d'oscillateur divisé (226).
- Boucle à verrouillage de phase (100) selon la revendication 9, comprenant en outre un filtre de boucle numérique (104) couplé audit détecteur de phase numérique (102, 202), dans laquelle ledit filtre de boucle numérique (104) est configuré de façon à recevoir ledit signal d'erreur de phase numérique (236) et à délivrer en sortie un signal de commande d'accord numérique.
- Boucle à verrouillage de phase (100) selon la revendication 10, dans laquelle ledit filtre de boucle numérique (104) comprend un filtre elliptique.
- Boucle à verrouillage de phase (100) selon la revendication 10, comprenant en outre un oscillateur à commande numérique (106) couplé audit filtre de boucle numérique (104), dans laquelle ledit signal de commande d'accord numérique commande la fréquence d'un signal de sortie (112) dudit oscillateur à commande numérique (106).
- Boucle à verrouillage de phase (100) selon la revendication 12, comprenant en outre un diviseur de rétroaction (108), dans laquelle ledit diviseur de rétroaction (108) est configuré de façon à recevoir ledit signal de sortie (112) dudit oscillateur à commande numérique (106) et à délivrer en sortie ledit signal de rétroaction d'oscillateur divisé (226).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/048,571 US7706496B2 (en) | 2005-01-31 | 2005-01-31 | Digital phase detector for a phase locked loop |
PCT/US2006/000511 WO2006083487A2 (fr) | 2005-01-31 | 2006-01-06 | Detecteur de phase numerique destine a une boucle a phase asservie |
Publications (3)
Publication Number | Publication Date |
---|---|
EP1844542A2 EP1844542A2 (fr) | 2007-10-17 |
EP1844542A4 EP1844542A4 (fr) | 2010-09-22 |
EP1844542B1 true EP1844542B1 (fr) | 2012-04-11 |
Family
ID=36756549
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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EP06717679A Active EP1844542B1 (fr) | 2005-01-31 | 2006-01-06 | Detecteur de phase numerique destine a une boucle a phase asservie |
Country Status (5)
Country | Link |
---|---|
US (1) | US7706496B2 (fr) |
EP (1) | EP1844542B1 (fr) |
KR (1) | KR100884170B1 (fr) |
AT (1) | ATE553532T1 (fr) |
WO (1) | WO2006083487A2 (fr) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9197226B2 (en) | 2013-07-08 | 2015-11-24 | Analog Devices, Inc. | Digital phase detector |
US9417944B2 (en) | 2011-10-05 | 2016-08-16 | Analog Devices, Inc. | Two-wire communication system for high-speed data and power distribution |
US9772665B2 (en) | 2012-10-05 | 2017-09-26 | Analog Devices, Inc. | Power switching in a two-wire conductor system |
US9946679B2 (en) | 2011-10-05 | 2018-04-17 | Analog Devices, Inc. | Distributed audio coordination over a two-wire communication bus |
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US7577225B2 (en) * | 2005-07-28 | 2009-08-18 | Agere Systems Inc. | Digital phase-looked loop |
US7403073B2 (en) * | 2005-09-30 | 2008-07-22 | International Business Machines Corporation | Phase locked loop and method for adjusting the frequency and phase in the phase locked loop |
US7443251B2 (en) * | 2005-12-15 | 2008-10-28 | International Business Machines Corporation | Digital phase and frequency detector |
US7847641B2 (en) * | 2005-12-15 | 2010-12-07 | International Business Machines Corporation | Digital phase and frequency detector |
JP4531104B2 (ja) * | 2006-02-17 | 2010-08-25 | 富士通株式会社 | 信号処理方法、信号処理装置及びアナログ/デジタル変換装置 |
TWI327823B (en) * | 2006-11-15 | 2010-07-21 | Realtek Semiconductor Corp | Phase-locked loop capable of dynamically adjusting a phase of an output signal according to a detection result of a phase/frequency detector, and method thereof |
WO2010041163A2 (fr) * | 2008-10-08 | 2010-04-15 | Nxp B.V. | Convertisseur de fréquence de phase en nombre numérique |
US7973578B2 (en) * | 2008-12-01 | 2011-07-05 | Samsung Electronics Co., Ltd. | Time-to-digital converter and all-digital phase-locked loop |
KR101292669B1 (ko) * | 2008-12-02 | 2013-08-02 | 한국전자통신연구원 | 타임투디지털컨버터의 오차 보정 장치 |
KR101658632B1 (ko) * | 2009-03-17 | 2016-09-23 | 삼성전자주식회사 | 디지털 위상 검출기 및 이를 포함하는 디지털 위상 고정 루프 |
US8076960B2 (en) * | 2009-04-29 | 2011-12-13 | Qualcomm Incorporated | Digital phase-locked loop with two-point modulation using an accumulator and a phase-to-digital converter |
DE102009047860B3 (de) * | 2009-09-30 | 2011-04-28 | Infineon Technologies Ag | Schaltungsanordnung, Analog-Digital-Wandler und Verfahren zum Wandeln von Zeitintervallen |
US8446191B2 (en) | 2009-12-07 | 2013-05-21 | Qualcomm Incorporated | Phase locked loop with digital compensation for analog integration |
US8339165B2 (en) * | 2009-12-07 | 2012-12-25 | Qualcomm Incorporated | Configurable digital-analog phase locked loop |
US8248106B1 (en) | 2010-07-21 | 2012-08-21 | Applied Micro Circuits Corporation | Lock detection using a digital phase error message |
KR101494515B1 (ko) * | 2013-04-22 | 2015-02-23 | 고려대학교 산학협력단 | 디지털 위상 고정 루프 회로 |
GB2545752B (en) * | 2015-12-23 | 2019-07-24 | Cirrus Logic Int Semiconductor Ltd | Phase locked loops |
KR102430227B1 (ko) | 2020-07-17 | 2022-08-08 | 고려대학교 산학협력단 | 듀얼-도메인 서브 샘플링 위상 고정 루프 |
CN112290940B (zh) * | 2020-10-19 | 2023-12-08 | 珠海格力电器股份有限公司 | 一种时钟分频方法和装置 |
EP4260465A1 (fr) * | 2020-12-14 | 2023-10-18 | Telefonaktiebolaget LM Ericsson (publ) | Appareil de représentation numérique de différence angulaire |
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JP3193805B2 (ja) * | 1993-05-26 | 2001-07-30 | 三菱電機株式会社 | Pll回路 |
SE513576C2 (sv) * | 1996-07-02 | 2000-10-02 | Celsiustech Electronics Ab | Förfarande och anordning för styrning av en oscillator |
JP4015254B2 (ja) * | 1998-01-16 | 2007-11-28 | 富士通株式会社 | ロック検出回路及びpll周波数シンセサイザ |
JP2944607B2 (ja) | 1998-02-12 | 1999-09-06 | 日本電気アイシーマイコンシステム株式会社 | ディジタルpll回路とクロックの生成方法 |
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US6100721A (en) * | 1999-02-01 | 2000-08-08 | Motorola, Inc. | Circuit and method of extending the linear range of a phase frequency detector |
KR100311046B1 (ko) | 1999-05-15 | 2001-11-02 | 윤종용 | 시간/디지털 변환기, 이를 이용하는 동기 회로 및 동기 방법 |
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US6429693B1 (en) * | 2000-06-30 | 2002-08-06 | Texas Instruments Incorporated | Digital fractional phase detector |
US8306176B2 (en) * | 2002-06-19 | 2012-11-06 | Texas Instruments Incorporated | Fine-grained gear-shifting of a digital phase-locked loop (PLL) |
GB2401498B (en) * | 2003-05-07 | 2006-02-22 | Zarlink Semiconductor Ltd | Tuner |
-
2005
- 2005-01-31 US US11/048,571 patent/US7706496B2/en active Active
-
2006
- 2006-01-06 WO PCT/US2006/000511 patent/WO2006083487A2/fr active Application Filing
- 2006-01-06 KR KR1020077018236A patent/KR100884170B1/ko active IP Right Grant
- 2006-01-06 AT AT06717679T patent/ATE553532T1/de active
- 2006-01-06 EP EP06717679A patent/EP1844542B1/fr active Active
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9417944B2 (en) | 2011-10-05 | 2016-08-16 | Analog Devices, Inc. | Two-wire communication system for high-speed data and power distribution |
US9875152B2 (en) | 2011-10-05 | 2018-01-23 | Analog Devices, Inc. | Methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system |
US9946679B2 (en) | 2011-10-05 | 2018-04-17 | Analog Devices, Inc. | Distributed audio coordination over a two-wire communication bus |
US9772665B2 (en) | 2012-10-05 | 2017-09-26 | Analog Devices, Inc. | Power switching in a two-wire conductor system |
US9946680B2 (en) | 2012-10-05 | 2018-04-17 | Analog Devices, Inc. | Peripheral device diagnostics and control over a two-wire communication bus |
US9197226B2 (en) | 2013-07-08 | 2015-11-24 | Analog Devices, Inc. | Digital phase detector |
Also Published As
Publication number | Publication date |
---|---|
WO2006083487A3 (fr) | 2007-10-04 |
EP1844542A2 (fr) | 2007-10-17 |
KR20070100350A (ko) | 2007-10-10 |
ATE553532T1 (de) | 2012-04-15 |
US7706496B2 (en) | 2010-04-27 |
US20060171495A1 (en) | 2006-08-03 |
WO2006083487A2 (fr) | 2006-08-10 |
KR100884170B1 (ko) | 2009-02-17 |
EP1844542A4 (fr) | 2010-09-22 |
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