EP1831662A1

EP1831662A1 - Micromechanical capacitive sensor element

Info

Publication number: EP1831662A1
Application number: EP05813635A
Authority: EP
Inventors: Hubert Benzel; Stefan Finkbeiner; Frank Fischer; Helmut Baumann; Lars Metzger; Roland Scheuerer; Peter Brauchle; Andreas Feustel; Matthias Neubauer
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2004-12-22
Filing date: 2005-11-04
Publication date: 2007-09-12
Also published as: JP2008524617A; US20110108932A1; DE102004061796A1; CN101087999A; WO2006066997A1

Abstract

The invention relates to a method for producing a micromechanical sensor element, which can be configured with a monolithic integrated construction and is capable of the capacitive detection of a physical variable. In addition to said production method, the invention also relates to a micromechanical device containing a sensor element of this type, such as a pressure sensor or an acceleration sensor.

Description

Micromechanical capacitive sensor element

State of the art

The invention is based on the production of a micromechanically produced in monolithic construction capacitive sensor element or a micromechanical device with such a sensor element having at least a first and a second electrode, a membrane and a cavity.

Capacitive surface micromechanical (OMM) pressure sensors are known in various embodiments. In contrast to piezoresistive sensors, capacitive sensors have the advantage that they can evaluate the contained measuring capacities practically without power. This is mainly due to the fact that stress transducers are avoided in the form of piezoresistors, which would otherwise flow large currents. In addition, capacitive pressure sensors offer the advantage that they are largely independent of temperature.

For many applications, capacitive pressure sensors (or other capacitive sensor elements) are desired, which can be constructed monolithically integrated as part of an IC manufacturing process, such as a CMOS process.

Usually, capacitive pressure sensors have a cavity bounded by two electrodes, one of the electrodes being formed by an elastic, electrically conductive membrane and the other electrode by a capacitor plate lying opposite the electrically conductive membrane. A pressure difference between the In the cavity prevailing pressure and the external pressure leads to a bending of the membrane and thus to a change in the distance between the electrically conductive membrane and the membrane plate opposite this membrane. From the concomitant change in capacitance of the capacitor formed from the electrically conductive membrane and the capacitor plate is on the capacitive

Pressure sensor acting external pressure determined. Such a typical capacitive pressure sensor is known, for example, from EP 0 714 017 B1, in which the cavity between two electrodes is produced by means of a sacrificial layer etching.

In DE 101 21 394 Al a capacitive pressure sensor is described, which is a second

Electrode, which largely encloses the first electrode and is placed on the same electrical potential. It is thereby achieved that the electric field or measuring field existing between the (third) membrane electrode and the first electrode of the capacitive pressure sensor is largely shielded from electrical interference fields which may surround a micromechanical pressure sensor. As a result, influencing the capacity to be detected as a measure of the detected pressure is largely suppressed.

From DE 40 04 179 Al an integrable capacitive pressure sensor is known in which a first electrode in a semiconductor substrate and a second electrode through the

Depositing and doping a polycrystalline semiconductor layer is generated. In this case, a spacer layer is applied, which determines the later pressure sensor cavity. This spacer layer is removed at a subsequent time by means of an etching process.

Advantages of the invention

The invention describes a production method for producing a micromechanical sensor element, which can be produced in monolithically integrable construction and has a capacitive detection of a physical quantity. In addition to the manufacturing method, a micromechanical device is also described, which contains such a sensor element, such as a pressure sensor or an acceleration sensor. It is provided that the manufacturing method consists of different process steps, wherein at least one first electrode is produced in or on the semiconductor substrate. Furthermore, it is provided that a first layer is applied to the first electrode, it being provided in particular that the first layer also covers parts of the semiconductor substrate or an insulating layer located below the first electrode and extending laterally beyond the first electrode. It is then provided to apply a first sacrificial layer, which consists of a first sacrificial material and is generated at least partially above the first electrode on the semiconductor substrate. A second layer is then applied to the first sacrificial layer, in which a first through-hole is produced, so that access to the first sacrificial layer is created. On the second layer, a second electrode is applied. With a second sacrificial material, the first through-hole is closed, so that a second sacrificial layer preferably forms on the second layer. Thereafter, the membrane layer is applied to the second electrode and at least a portion of the second layer adjacent to the second electrode. In this case, the second sacrificial layer can be covered. Subsequently, a second through-hole is produced in the membrane layer, by means of which access to the second sacrificial layer is made possible. Through the second and then through the first through hole, the second and the first

Sacrificial material are removed. This is preferably done by a plasmalosen etching. Subsequently, a third layer is applied to the membrane layer, which closes at least the second through hole and thus generates a cavity in the region of the first sacrificial layer between the first and the second electrode.

The decisive advantage of the known state of the art is the unbundling of the mechanical function of the membrane and the electrical function of the upper capacitance electrode. Furthermore, the upper capacitor electrode can be formed by a thin, conductive film which can be deposited at moderate temperatures and structured independently of the membrane layer. By using the two sacrificial layers, the etching process can be terminated in a controlled manner. In addition, the dry, plasmalose sacrificial layer etching prevents etching residues from remaining.

It is likewise advantageous to apply an insulating layer to the semiconductor substrate before generating the first electrode. Thus, it can be prevented that at the first electrode in

Measuring operation Leakage currents occur that falsify the measuring signal. Such leakage currents can occur, for example, in the case of a pn junction, when an n-electrode is produced in a p-type substrate. In addition, in the case of a first electrode isolated from the substrate - A -

These can be set to any potential, without having to pay attention to the interaction with the substrate.

In one development of the invention, it can be provided that the first electrode has an n- or p-type doped semiconductor material or poly-silicon. Furthermore, it can be provided that at least the first or the second layer comprises an oxide, a nitride or TEOS. While Si or SiGe may be provided for the first sacrificial material, SiGe or poly-silicon is provided for the second sacrificial material. In addition, it can be provided that the second electrode likewise comprises Si, SiGe or poly-silicon, while the membrane layer preferably comprises nitride, oxide or a dielectric material.

Finally, it can be provided that the third layer has nitride.

Advantageously, the first layer has a layer thickness of 40-250 nm, the first sacrificial layer has a layer thickness of 0.3-1 μm, the second layer has a layer thickness of 50-250 nm and the membrane layer has a layer thickness of 100-1000 nm. Overall, by using the thin layers, a layer stack with a very low topography can be achieved. Thus, layer stacks are conceivable which are thinner than 1.7 microns and have a topography of <0.5 microns.

In order to bring about closure of the second through-hole, the layer thickness of the third layer should be selected larger than the layer thickness of the second sacrificial layer. Thus, enough material can be provided to close the second through hole.

In order to obtain the most uniform and even membrane layer, it is possible to provide the layer thickness of the second sacrificial layer as a function of the layer thickness of the second

Electrode to choose. In particular, it is provided to apply both layers in the same thickness.

Advantageously, the fabrication of the micromechanical sensor element takes place within the framework of a standard IC process (for example a CMOS process). It can be on the

Sensor element circuit parts are generated, which are used for contacting the sensor element but also for detecting and / or evaluation of the sensor signals of the sensor element. In this case, the sacrificial layer etching may, as a classical micromechanical process, be shifted to the end of the process (before a passivation). Thus, no cavity would have in the CMOS line can be processed, since the processes operfschichtätzen, passivation and optionally opening the passivation for contacting the sensor element can be performed with the micromechanical process. In addition, there would be no moving part in the CMOS processing line, thereby reducing particle risk.

By means of the proposed manufacturing method, a capacitive sensor element can be produced which has a parasitic capacitance reduced by at least one order of magnitude compared to known sensor elements. Thus, a higher signal / noise ratio is possible, so that a smaller area requirement for the sensor element is made possible. In addition, the reduced parasitic capacity results in a reduced current consumption for the evaluation circuits. One way to further reduce parasitic capacitances is to increase the isolation distance between the two electrodes. In addition to the choice of a thicker first sacrificial layer, this can also be done by applying a fourth insulating layer between the first and the second layer, it being possible in particular for this fourth layer to be arranged only partially between the first and the second electrode. However, it is particularly advantageous if the fourth layer is applied next to the first sacrificial layer and has a comparable layer thickness therewith. As a result, the third layer can be at least in the region of the first and / or the second electrode without pronounced

Stage are generated.

In a particular embodiment of the invention, the plasmalose etching process for dissolving out the first and the second sacrificial layer is carried out with a fluorine-containing etching material such as ClF ₃ and / or XeF ₂ . By using a plasmaless etching process, the dissolution of the two sacrificial layers after the formation of circuit elements can be accomplished by a CMOS process. Thermal destruction of the thin interconnects within such circuit elements can thus be avoided. Typically, such etching processes can be used at temperatures between -20 ⁰ C and 60 ⁰ C.

In general, the described layers of the sensor element can be produced with standard equipment. The layer stress of the membrane can optionally be adjusted with an RTA process (rapid thermal annealing process). In addition to the sensor element, a reference measuring element can be produced on the semiconductor substrate, which can advantageously also be produced by the described method of the main claim. It is provided that in the first sacrificial layer of the reference element for forming support points of the membrane at least a third through hole is produced, which allows access to the first layer. In a

Development of the invention can then be provided to expire this at least one third through hole with the material of the second electrode and / or with the material of the membrane layer. Thus, after the dissolution of the first and the second sacrificial layer, a cavity is formed underneath a membrane, which, however, stands on columns in comparison to the sensor element. A movement of the membrane can thus be reduced, if not prevented. Of course, the residual movement of the membrane depends on how many through holes or support points / columns are generated and how they are spatially distributed in the space between the two electrodes.

By an additional conductive layer, which forms a third electrode, over the entire

Sensor element, a shielding of the measuring electrode (s) against external interference fields can be achieved (Faraday cage). Such a third electrode can for example consist of a further poly-silicon layer but also of a metal layer. In conjunction with the CMOS process, the layer may consist of one of the CMOS metal levels. In order to avoid possible temperature effects, the shielding electrode may e.g. be structured grid-like. However, a shielding effect can also be achieved by keeping the second (upper) electrode at ground potential.

In a further embodiment of the invention, it is provided above the first and second electrodes to bring a mass element with in particular a defined seismic mass onto the membrane or onto a passivation layer adjoining the membrane. In this case, the mass element can be produced by means of a local deposition method, a dispensing method, a screen printing method or a known micromechanical structuring method.

With such a mass element on the membrane, an acceleration sensor can be generated using a capacitive sensor element in a simple construction. The sensitivity can be adjusted easily on the one hand on the choice of mass and on the other via the control and evaluation of the two electrodes, for example. By an offset adjustment during the initialization of the sensor element. In addition, by using a plurality of membrane cells with mass elements of different mass, a wider range of possible acceleration values can be covered. Advantageously, each membrane cell consists of two electrodes, a cavity located between the electrodes and a membrane, wherein support means are provided in the cavity, which prevent the membrane from breaking when excessively bent.

By means of such an acceleration sensor can be dispensed with a costly capping otherwise customary acceleration sensors for protection against sawing, singling or assembly. Another advantage is the simple adjustment of

Sensitivity due to the defined choice of the mass, wherein as shown also simply multi-channel elements can be generated.

In general, in the interaction of CMOS processes and micromechanical process steps for producing the sensor element according to the invention, the layers and the planes can be matched to one another and thus used together. This results in a more efficient and thus cheaper manufacturing process.

Advantageously, the capacitive sensor elements according to the invention can be used at high temperatures by the use of polysilicon electrodes which are separated by oxide layers from the substrate as well as from further layers. This has advantages, for example, when used as a tire pressure sensor, since in addition also a low power consumption is necessary, and as a combustion chamber pressure sensor.

Further advantages will become apparent from the following description of

Embodiments or from the dependent claims.

drawings

Figure Ia to k process steps for generating the capacitive according to the invention

Sensor element Figure 2 Top view of the capacitive sensor element

Figure 3a and b Inserting an additional insulating layer Figure 4a and b Reference element with support columns Figure 5a to c acceleration sensor Figure 6a and b. Change of the membrane enclosure Figure 7a to h Alternative process flow to produce a capacitive sensor element according to the invention

embodiments

FIGS. 1 a to k show a possible manufacturing process of a monolithically integrated capacitive sensor element according to the invention by means of micromechanical method steps. In this case, according to FIG. 1 a, a first electrode 110 is initially produced in or on a semiconductor substrate 100, for example by an n-type doping. In addition, terminal regions 104 or isolation regions 105 can be created on or in the semiconductor substrate 100. In other areas of the semiconductor substrate can

Gates are formed with gate oxide, poly etc.

In FIG. 1b, a first layer 115 with a thickness of 40-250 nm is applied over the entire circuit. The deposition of the first layer takes place at temperatures <900 ⁰ C and serves to the first electrode 110 and the areas 104 and 105 against attack by

ClF ₃ , XeF ₂ or the like. Preferably, the first layer 115 of oxide or nitride, but preferably of a TEOS layer which is applied at 400 ⁰ C with an ozone support in a preferred thickness of 100 nm on the surface. When using thermal oxide (eg, thick gate oxide) for the first layer 115, 40 nm (or less) is already sufficient. The main use of the first layer 115 is, in addition to the isolation of the first electrode 110, a protection against the subsequent plasmalose etching, for example by ClF ₃ . Therefore, a requirement of the first layer 115 is that it be dense and resistant to the etch materials used therein. As shown in FIG. 1c, a first sacrificial layer 125 of Si or SiGe having a thickness of 0.3-1 μm is deposited on the first layer 115. For this purpose, a deposition method is selected, which can be used at temperatures below 900 ° C. The first sacrificial layer 125 can be made, for example, with PECVD as an amorphous or partially crystalline Si layer, but preferably with LPCVD at a temperature <680 ° C. with a layer thickness of 450 μm.

550 nm are deposited. It should be noted that the surface roughness (R _a ) of the first sacrificial layer 125 is less than 100 nm. The first sacrificial layer 125 is subsequently structured in such a way that at least part of the first sacrificial layer 125 is located above the first electrode 110. On the other surface, however, the first sacrificial layer 125 can be removed. The structuring step or the lithographic technique is preferably performed such that no sharp edge, but relatively soft structural edges arise. As a result, the stability of the pressure membrane under extreme pressure overloads can be further increased.

FIG. 1 d shows the generation of a second layer 130 which extends over the entire area over the first

Sacrificial layer 125 and the remaining surface of the substrate is deposited. The layer thickness of the second layer 130 is preferably between 50 and 250 nm and is deposited at temperatures below 900 ⁰ C. With this second layer 130 of nitride or oxide, a layer resistant to the subsequent plasmaless etching process is to be produced. Another possibility is to form the second layer 130 from a 100 nm thick, ozone-supported TEOS layer. Such TEOS: O ₃ layers generally have dense surfaces and resistance to C1F ₃ etching. Furthermore, such layers show very good edge coverages and the property of smoothing surface roughness very efficiently, so that the roughness of the first sacrificial layer 125 is partially compensated. Furthermore, it is advantageous if not absolutely necessary if the layer tension of the second layer 130 is small or the second layer 130 has a slight tensile stress. If a difference in the coefficient of thermal expansion between the second layer 130 and the membrane layer 140 still to be applied leads to an undesirable temperature drift in the sensitivity or in the sensor offset, the second layer can be in the same material as the membrane layer

140 (e.g., both in LPCVD nitride).

In order to obtain access to the first sacrificial layer 125 for the subsequent etching process, in another example, by means of a suitable dry etching process Step in the second layer 130, a first through hole 155 (see Figure Ie). The first through-hole 155 may be attached to one or more locations of the second layer 130. In the structuring of the second layer 130, the etching process ends on the first sacrificial layer 125, but it does not harm the further process flow, if a part of the first sacrificial layer 125 in the region of the first through-hole is also formed by the etching process

155 is attacked and dissolved. With an unfavorable etching ratio, the etching process can also be time-controlled. In general, it should be noted that in structuring, i. in the formation of the first through-hole 155, the edges of the first sacrificial layer region 125 remain sufficiently covered with photoresist in order to avoid an uncontrolled attack of the second layer 130 on the structure flanks.

In the next method step (see FIG. If), an electrode layer is deposited on the second layer 130 to form a second electrode 135. The electrode layer is preferably made of poly-silicon, which is produced by means of a suitable method at moderate temperatures below 900 ⁰ C and made conductive. The conductivity of the second electrode 135 does not have to be very high in order to fulfill the desired function in the capacitive sensor element. One way to make the electrode layer conductive is to produce the layer by doping by ion implantation. The necessary annealing step can then be combined with annealing for lower poly layers from the CMOS processing (eg poly-gate). However, this electrode layer 135 can also be made of metal, in which case a different closure technique than described below must be applied.

When using poly-silicon or poly-SiGe as the material for the second electrode

135 may be generated simultaneously with the electrode layer in the region of the first through-hole 155, a poly-track, which can be used later as etch access for the subsequent plasmalose etching process. Generally, a second sacrificial layer 170 is formed of a second sacrificial material that both fills the first via 155 and covers a portion of the second layer 130 adjacent the first via 155.

As a result, by means of a second through-hole 160, an offset etching access 175 with access to the first sacrificial layer 125 can be produced (see FIGS. 1 and 1). The layer thickness of the second sacrificial layer is preferably adapted to the layer thickness of the first sacrificial layer in order to avoid steps on the surface of the membrane layer. As shown in FIG. 1g, a membrane layer 140 is applied above the electrode layer to form the second electrode 135, which diaphragm, together with the second layer 130 and the third layer 145 to be subsequently applied, adjusts the supporting function of the membrane. For this purpose, the membrane layer 140 is designed at deposition temperatures <900 ° C to tensile stress. The preferred choice of an LPCVD nitride as the material of the membrane layer 140 makes it resistant to the plasmaless etching process. In addition, however, the use of other nitride or oxide layers is possible, which can be reproducibly deposited in terms of tensile stress and layer thickness. It is generally provided, the membrane layer 140 with a

Layer thickness of 100 nm to 1 micron, wherein in the case of the choice of LPCVD nitride, a layer thickness of 200 to 500 nm is sufficient. To improve the resistance of the membrane layer 140 to the plasma-free etching process, a very thin oxide layer can be deposited on the membrane layer 140 (not shown). In preparation for the detachment of the first and second sacrificial material or the first and second sacrificial layer, a second through-hole 160 is produced in the membrane layer 140, which leads to the second sacrificial layer and has an opening offset from the first through-hole 155. This opening 160 establishes the etch access 175 to the first sacrificial layer 125 via the second sacrificial layer 170 and the first via 155. Experiments have shown that a plasmaless etching process using ClF _{3 has} reaction-limited etch rates and is almost independent of the layer thickness of the poly sacrificial layer. When XeF _{2 was used} , however, transport-limited etching rates with a strong layer thickness dependence were observed. Thus, the etch rates for very thin layers are increased by up to 800% compared to layers with thicknesses> 20 μm. The thickness of the two sacrificial layers therefore has no negative influence on the layer thicknesses used in the present method

Sacrificial.

In sacrificial layer etching using ClF ₃ or XeF ₂ , all exposed poly silicon layers are etched very rapidly (see FIG. 1 h). The back of the substrate may or may not be protected with an oxide or nitride. ClF ₃ passes via the "Ätzventil" 175 to the sacrificial layers 170 and 125 and removed at rates of up to 10 microns / the poly-silicon and the sacrificial material min in the two layers. The plasma-less etching process by means of ClF _3, a temperature may range from -20 ° C to 60 ⁰ C during the etching step be used, which already processed circuit parts in a previous CMOS process does not be affected. In addition, resist layers of photoresist can be used to protect certain areas.

Since Al is not etched by ClF ₃ , the sacrificial layer etching process can also take place after deposition and structuring of the last metal level in the CMOS process. In this

Embodiment initially no cavity is generated, which would otherwise be protected during the CMOS wiring. Thus eliminates the risk of mechanical destruction by the process handling or by cleaning in the ultrasound. The generation and closure of the cavity in this embodiment occurs at the end of the CMOS process through the last passivation layer, which closes the etch access 175.

In general, according to FIG. 1j, the etching access 175 can be closed by means of a third layer 145 at temperatures <900 ° C. In this case, the second through-hole 160 is filled with the material of the third layer 145 in such a way that a plug 180 is created, which encloses a definable reference pressure prevailing in the cavity 120 during closure.

The lateral offset of the two through holes prevents the material of the third layer 145 from penetrating into the cavity 120 and filling it. If the layer thickness of the third layer 145 is selected such that it is slightly larger than the layer thickness of the second sacrificial layer, the hermetic seal of the etch access 175 occurs because of the sufficient material supply since the deposition of the third layer 145 and the

Edge covering or embracing the deposition leads to a large-scale closure with sufficient closure depth. For the third layer 145, an LPCVD but also a PECVD process may be used. Preferably, the third layer 145 of nitride with low defect density, since this is known for good long-term stability based on the gas tightness. In addition, in one of the metal levels of the CMOS process, further enhancement of the

Sealing in the range 180 can be achieved.

After closing the cavity 120, the further creation of the wiring levels in the CMOS process takes place. Approachally, a metal pad 150 is shown in FIG. 1C, which is connected to the second electrode 135 via a contact hole through the membrane layer 140 and the third layer 145. The first electrode 110, on the other hand, was contacted by an earlier CMOS process step (not shown). If the sacrificial layer etching occurs after the last metal processing level, the contacting must be be completed before. Then, the passivation formed by the third (shutter) layer 145 is on the metal pad 150 and needs to be opened.

FIG. 2 shows a schematic plan view of a capacitive sensor produced by the method described with the first electrode 110, the polygonal sensor located above it.

Sacrificial layer 125 (or the cavity 120), the second electrode 135 and the overlying membrane layer 140 which is cantilevered in the region of the first sacrificial layer 125 by sacrificial layer etching. The second electrode 135 is guided via a conductor track 185 next to the self-supporting membrane, where it can be connected to a metal track or a metal pad 150. In the right-hand area of FIG. 2, the etching valve 175 is shown.

With the present exemplary embodiment of the invention, the parasitic capacitances can be reduced compared to the known solutions in the production of capacitive sensor elements. This is u.a. Remember that only a very narrow conductor 185 is led away from the membrane and not as in known capacitive sensors, the upper

Lead electrode in full with a very wide overlay on the outer terminal regions in the substrate, since the electrode is also the supporting diaphragm design in known sensors. Moreover, the isolation distance consisting of the layers 115 and 130 can be made much larger in the present capacitive sensing element. In addition, a further insulating layer 300 (see Figure 3b in comparison to Figure 3a) of oxide or nitride over the first layer 115 may be used to further increase the isolation distance. It may be advantageous to introduce this insulating layer 300 only in the region of the contacting 310 and / or to adapt its layer thickness to the layer thickness of the first sacrificial layer 125.

In a further exemplary embodiment, provision can be made for a reference element to be generated in addition to the already described capacitive sensor element. For the formation of a reference element, by means of which, for example, the offset of the sensor element can be determined, through holes are produced within the first sacrificial layer 125 down to the first layer 115. By means of these through-holes, non-positive but electrically insulated supports 400 and 410 can be formed under the pressure membrane, which mechanically connect the membrane to the substrate. As a result of the sacrificial layer etching, a cavity 420 which is supported by supports or pillars thus forms. As shown in FIGS. 4a and 4b, the electrode material of the second electrode 135 can be provided in the depression the support 400 to integrate or provide a corresponding recess, so that the support 410 generates a lower parasitic capacitance than the support 400.

A further exemplary embodiment is shown by way of example with reference to FIGS. 6a and 6b. In this case, a plurality of micromechanical sensor elements are shown, which by means of a

Process combination with a CMOS process have been generated. In the two figures, such a CMOS transistor 665, a CMOS capacitor 670 and a corresponding to the figures Ia to k described sensor element 675 are shown. The essential difference between the sensor element of the figure Ik and the sensor element 675 of Figure 6a, however, is that on the (semiconductor) substrate 600, an insulating (oxide) layer 610 has been applied, the lower or first electrode 620 largely from Substrate 600 thermally and / or electrically isolated. An influence of the measurement result, for example by a leakage current into the substrate, can thus be prevented. Moreover, by using such an insulating layer 610, the potential at this first electrode 620 can be arbitrarily selected. Otherwise, the sensor element 675 also has a cavity

630 between the first electrode 620 and the overlying second electrode 640, both of which may be made of poly-silicon, for example. The support frame 650 of the second electrode 640 is preferably made of nitride, so that, just as in the sensor element according to FIG Ik, a unbundling of the mechanical function of the membrane and the electrical function of the second, upper capacitance electrode takes place.

In the structure of Figure 6a, several layers are shown, which will not be explained in detail below. These are mainly insulating oxide layers 615 and metal layers 685, which are used for the function of the individual micromechanical components 665, 670 and 675 or serve as pure contacts. Finally, it is usually provided in such a sequence of layers to protect the layers or metal layers produced from environmental influences with a passivation layer 660, for example of nitride. In addition to the supply of the medium to the membrane, certain surface areas of the layer stack can remain open as contact points for external circuits.

A further improvement or stabilization of the measured value detection by the capacitive sensor element described can be achieved by the use of (shield) shielding. By such (shield) shielding, the influence of the measurement signal by external Interference fields, external objects, dirt or other layers are reduced in the manufacturing process. For this purpose, the outer or second electrode 640 of the sensor element can be set to ground potential, for example by electrical connection to the substrate wafer or by low-resistance clamping. As a result, the lower or first electrode 620 is shielded from external interference fields (Faraday cage). The evaluation of the

Measurement capacitor 675 formed of the two electrodes may be e.g. This is done by placing a charge on the bottom electrode 620, which is converted into a voltage signal by a charge amplifier (switched capacitor circuit). This output voltage is proportional to the capacitance of the measuring capacitor 675. Due to the shielding effect of the sensor chip is independent of external interference fields but also of external objects that have a different dielectric or conductive. Such articles may e.g. Dirt, more layers in the process or the sensor housing. A shielded capacitor is also insensitive to external approaches or media placed on the sensor, as they can not affect the field of the measuring capacitor.

Another way to achieve shielding is to apply an additional conductive layer over the entire pressure measuring capacitor. Such a layer may for example consist of a further polysilicon layer or of a metal. In conjunction with the CMOS process, the layer may consist of one of the CMOS metal levels. In order to avoid possible temperature effects, the shielding electrode may e.g. be structured grid-like.

The function of the capacitive sensor element depends strongly on the different thermal expansion coefficients of the different layers of membrane and

Membrane clamping off. The layer stress creates a warping of the membrane, which is superimposed on the actual measurement signal. If materials with approximately the same thickness are used for the membrane, the layer stress has a particularly strong effect (bimetallic effect). Another major influence is the membrane clamping on the sensor function. The same effects as just described for the membrane, also occur in the field of

Membrane clamping on. If the geometry of the clamping changes over the temperature, the force and moment change along the clamping. This leads to a disturbing deflection of the membrane as a function of the temperature. While this may be one Most be compensated in the evaluation, but this is associated with higher-grade effects consuming and with additional costs.

An embodiment in which the negative effect of the membrane clamping is reduced is shown in FIG. 6b. The membrane is mainly due to the greater thickness

Polysilicon defined. The layers above and below the poly-silicon layer 640 are constructed approximately symmetrically, so that the stress compensates. The membrane in Figure 6b is clamped only by the membrane material at the edge, while defining the cavity below the membrane edge. Thus, the membrane is defined by the lateral boundary of the first sacrificial layer or the cavity, so that thermal length changes by different coefficients of thermal expansion have no influence. In addition, the membrane restraint 680 is disturbed by no other materials. The polysilicon membrane is connected only via an oxide layer with the bulk silicon, which has the same coefficient of thermal expansion.

An alternative way of removing the various oxide and nitride layers over the membrane is to have no nitride but BPSG deposited over the second, upper electrode 640 (not shown). BPSG is the next isolation layer in the CMOS process that is deposited. If the first metal (e.g., 685) is not etched away on the membrane, it may end up etching the oxide and nitride layers

Etching stop be used. Subsequently, the metal is removed and the passivation is deposited. As a further embodiment, the polysilicon membrane of Figure 6b may be used in etching the oxide-nitride stack as an etch stop layer.

In a further exemplary embodiment, the micromechanical capacitive sensor element according to the invention, as shown in FIG. 5a, is used as an output element for the generation of an acceleration sensor. In addition to the already known first electrode 510, the second electrode 535, the cavity 520 located between the electrodes and the membrane 540, an already mentioned insulation layer 505 has been applied to the (semiconductor) substrate 500. To realize the

Acceleration sensor is applied to the membrane 540 a mass element 570, as shown in Figure 5b. By increasing the mass of the membrane, the sensor element is sensitive to accelerations, ie it can be used in particular perpendicular to the chip plane. In this spring-mass system, the stiffness is due to the expansion and the determined mechanical properties of the membrane. Moreover, if three such acceleration sensors are each operated at a right angle, all spatial directions can be covered.

The mass element 570 can be applied after completion of the integrated capacitive membrane sensor with a defined mass. For this purpose, local deposition can be used, as they are known for example in the inkjet printing process from DE 103 15 963 Al. Furthermore, it is conceivable to use dispensing methods in which minute amounts of paints can be applied in a controlled manner. In addition, however, known screen printing methods are also usable. The deposition can be

Tempering follow, in which the applied substance hardens. As the substance for the mass element 570, simple dyes, paints, polymers, suspensions or similar materials can be used, which can be processed in a controlled manner.

Alternatively, it is also possible to apply a layer over the entire surface, which is structured in a subsequent step by means of a known (micromechanical) masking method so that a defined mass element 570 remains above the dielectric membrane 540.

FIG. 5c shows the distribution of mass elements 570 and 580 with different masses over a plurality of membrane cells. Due to the lateral extent and the mass assignment of the capacitive sensor membrane, the sensitivity of the intertial sensor can be determined. In this way, low-g to high-g applications can be covered with sufficient accuracy. The membrane shape of the spring ensures high overload resistance. Transverse accelerations in x- and y-directions (in-plane to

Chip) have a small influence on the sensor signal. A high overload safety can additionally be achieved in that the membrane can rest in the event of an overload, whereby the membrane center is supported.

A further embodiment is shown in FIGS. 7a to h. With this

Embodiment, another process is described in which the integration of a pressure sensor element and a CMOS evaluation circuit is monolithic on a substrate. By using synergies in the layer sequence of the pressure sensor element and the CMOS evaluation circuit are required for the production of the sensor element - compared to the CMOS process - only a few additional layers and Fotolithographieschritte.

The basis for the process flow to be described in FIGS. 7a to h is a CMOS process in which by inserting a sacrificial silicon layer in front of the metal layers of the

CMOS process, a pressure sensor element 675 is formed with a dielectric membrane and embedded poly-silicon electrode. This is made possible, inter alia, by a silicon sacrificial layer etching step with ClF ₃ and separation of the mechanical and electrical functionality of the membrane layer. The process flow is therefore optimized from the viewpoint that the steps changed at the CMOS process are the functionality of the CMOS circuit elements

(Transistor 665, capacitor 670) not or only slightly changed.

The starting point for the process is a (semiconductor) substrate 700, on which a structured approximately 700 nm thick LOCOS layer 710 for thermal and electrical insulation is deposited, as shown in FIG. 7a. On this LOCOS layer 710 is for the lower

Electrode of the capacitor, an approximately 300 nm thick layer 720 and formed for the lower electrode of the pressure sensor element an equally thick layer 725 of poly-silicon. To form the subsequent transistor, an approximately 40 nm thick sacrificial oxide layer 730 (layer from which the gate oxide 735 is later formed) is produced on the substrate 700. On the layer 725, a layer 740 of gate oxide is deposited, as shown in Figure 7b, which is the lower electrode of the

Pressure sensor element separated from the deposited in the subsequent step silicon-containing sacrificial layer 750 (see Figure 7c). The gate oxide makes passivation of the lower electrode 725 for the subsequent C1F ₃ etching attack. As a sacrificial layer in the present embodiment, an approximately 1000 nm thick PolyO layer 750 is used. The thickness of the layer 750 is dependent on the desired sensitivity range, but is typically of the order of 1 .mu.m to avoid excessive additional topography. An ONO layer system 755, which is produced in the CMOS process by thermal oxidation, deposition of SiN and reoxidation, encloses the sacrificial layer 750 and forms a boundary of the sacrificial layer 750 to the upper electrode of the pressure sensor element. In the same process step, an ONO layer system 754, which serves as a dielectric, can likewise be applied to the lower electrode of the CMOS capacitor 670. In structuring the ONO layer 755, the etch access 764 to the sacrificial layer 750 is exposed. This is followed by the formation of the gate oxide, which is then immediately protected by a thin poly-silicon layer (thinPoly). After deposition of the thinPoly layer An additional paint and etch step is performed which exposes the etch access 764 to the sacrificial silicon layer 750. As shown in FIG. 7d, an approximately 300 nm thick second poly-silicon layer subsequently forms, which forms both the gate electrode 737 of the transistor 665 and the upper electrode 760 of the capacitor 670 in the CMOS process. In addition, with this second poly-silicon layer, the upper electrode 785 of the

Pressure sensor element 675 generates, which defines in combination with the lower electrode, the electrical functionality of the pressure sensor. At the same time, the etching access 764 is also closed with a poly-silicon layer 745, via which the subsequent etching access to the sacrificial layer 750 is guided. In FIG. 7f, the three elements (transistor 665, capacitor 670 and pressure sensor element 675) are shown in cross-section after deposition and structuring of an SiN layer 775 which is about 200 nm thick. Clearly, the second etch access 765 can also be seen on the second poly-silicon layer 745, which forms the etch channel on the sacrificial layer 750. SiN is used in the CMOS process flow to make spacers around the gate electrode. These spacers are needed for a subsequent self-aligned implantation of the drain and source regions. For the pressure sensor, SiN is used as a membrane layer, which assumes the mechanical functionality in the final sensor element. FIG. 7e shows a plan view of a possible implementation of the pressure sensor. The central circular region represents the pressure deflectable region. The top 780 terminal 780 and the bottom terminal 770 terminal 770 and the etch access 765 are also shown. As shown in FIG. 7g, in the next

Alternating Process Steps Using a TEOS Process SiO ₂ insulating layers 800, 810, 820 and 830 and metal layers 790, 835, 840 and 845 serving to wire the CMOS elements are deposited and patterned. Typically, the metal layers have layer thicknesses of 600 nm (for example in the case of the metal layer 790) up to layer thicknesses of 1000 nm (for example for the metal layer 840). A preferred process variant would leave the SiO ₂ layers in the pressure sensor area, but remove the metal layers. It is also conceivable here to open individual or some SiO ₂ layers already in order to reduce the topography above the pressure sensor and to simplify the subsequent exposure of the etch access 765 via the access 860 and / or the SiN membrane via the access 870. After separation of the wiring and isolation levels, first of all the access 860 to the etch access 765, later also the access 870 to the membrane has to be opened. Both etch access and membrane area are freed from the overlying SiO ₂ layers by a combined wet / dry etch. A prerequisite for this is a sufficient selectivity of the etching step with respect to SiN. Subsequently, the second Poly-silicon layer 745 via the Ätzzugang 765 and the silicon-containing sacrificial layer 750 via the resulting etching channel using a dry chemical (plasmalosen) etching process (eg C1F ₃ etch process) dissolved out. The final passivation from the CMOS process (for example by means of an approximately 600 nm thick layer 880 of SiO ₂ combined with an approximately 750 nm thick layer 890 of SiN, as described in US Pat Figure 7h) is used for the pressurized can process to close the etch access 765. If the deposition of the passivation layers 880 and 890 on the membrane during the pressure sensing has a disruptive effect, these can be etched back in a last step.

Alternatively, the etching access 765 could also first be opened, the sacrificial layer etching carried out with ClF ₃ and the etching access reclosed. Only then could access 870 to the membrane be uncovered.

Another way to open or expose etch access and membrane is not to remove in the pressure cell area in the previous CMOS process, the metal layers from which the wiring elements 790, 835, 840 and 845 are formed and in turn the SiO ₂ Passivation layers (comparable to a via contact). The metal stack located above the pressure cell could be etched wet-chemically and highly selectively against SiN. The sacrificial layer etching and the closure of the etch access proceed as already described.

Claims

claims

1. A method for producing a micromechanically monolithically integrated capacitive sensor element detecting a physical quantity, wherein the production of the

steps

Generating a first electrode (110, 510, 620, 725) on a semiconductor substrate (100, 600, 700),

Producing a first layer (115, 740) at least on the first electrode (110, 620, 725),

Depositing a first sacrificial layer (125, 750) of a first sacrificial material above at least a portion of the first electrode (110, 510, 620, 725),

Producing a second layer (130, 755) on the first sacrificial layer (125, 750),

Creating a first through-hole (155, 764) through the second layer (130, 755) on the first sacrificial layer (125, 750),

Generating a second electrode (135, 535, 640, 785) on the second layer (130, 755),

Closing the first through-hole (155, 764) with a second sacrificial material, wherein it is provided that the second sacrificial material covers at least part of the second layer (130, 755) in the region of the first through-hole and - a second sacrificial layer (170, 745) forms,

Depositing a membrane layer (140, 650, 775) on the second electrode (135, 535, 640, 785) and at least a portion of the second layer (130, 640) adjacent to the second electrode (135, 535, 640, 785) , 785), - generating a second through-hole (160, 765) through the membrane layer (140, 650,

775) on the second sacrificial material,

Detaching the first and second sacrificial material, preferably by means of a plasma-free etching method, through the first and the second through-hole, - Applying a third layer (145, 615, 880) on the membrane layer (140, 650, 775), wherein it is provided that the third layer (145, 615, 880), the second through hole (160, 765) closes and through the Closing the second through-hole (160, 765) has a cavity (120, 520, 630, 900) in the region of the first sacrificial layer (125, 750) is generated between the first and the second electrode comprises.

2. The method according to claim 1, characterized in that before generating the first electrode (510, 620, 725), an insulating layer (505, 610, 710) is applied to the semiconductor substrate.

3. The method according to claim 1, characterized in that

the first electrode is an n- or p-type doped semiconductor material or poly-silicon, and / or

the first layer of oxide, nitride or TEOS and / or

the first sacrificial material Si or SiGe and / or

the second layer is oxide, nitride or TEOS and / or

the second electrode Si, SiGe or poly-silicon and / or the second sacrificial material SiGe or poly-silicon and / or

the membrane layer nitride or oxide or a dielectric material and / or

- The third layer has nitride.

4. The method according to claim 1, characterized in that

the first layer has a layer thickness of 40-250 nm and / or

the first sacrificial layer has a layer thickness of 0.3-1 μm and / or

the second layer has a layer thickness of 50-250 nm and / or

- The membrane layer has a layer thickness of 100-1000 nm.

5. The method according to claim 1, characterized in that the layer thickness of the third layer (145, 615, 880) is selected to be greater than the layer thickness of the second sacrificial layer.

6. The method according to claim 1, characterized in that the layer thickness of the second sacrificial layer is selected as a function of the layer thickness of the second electrode, wherein it is provided in particular that both layer thicknesses largely correspond.

7. The method according to claim 1, characterized in that on the micromechanical

Sensor element at least a portion of a circuit is preferably generated in a CMOS process, which

- For contacting the sensor element and / or

- Is provided for detecting and / or evaluation of sensor signals of the sensor element, wherein in particular is provided to generate the circuit before the dissolution of the first and second sacrificial layer.

8. The method according to claim 1, characterized in that between the first and the second layer, a fourth insulating layer (300) is applied, wherein it is provided in particular that the fourth layer is comparable to the first sacrificial layer

Has layer thickness and / or at least partially disposed between the first and second electrode.

9. The method according to claim 1, characterized in that the etching process for dissolving out the first and the second sacrificial layer

- By means of a fluorine-containing etching material in particular ClF ₃ or XeF ₂ and / or

- At a temperature between -20 ⁰ C and 60 ⁰ C takes place.

1 O.Verfahren for producing a Referenzmesselements according to a manufacturing method described in claim 1, characterized in that for forming support points in the first sacrificial layer at least a third through hole on the first layer (115, 740) is generated, wherein in particular it is provided that by the expiration of the at least one third through-hole with the material - the second electrode and / or

- The membrane layer is generated in the extraction of the first and second sacrificial layer of the column-supported cavity.

11. The method according to claim 1, characterized in that above the second electrode, a third electrode is generated, wherein it is provided that the third electrode

- Is electrically isolated from the second electrode and

- At least the first and the second electrode covering, wherein it is provided in particular that the third electrode

- Poly-silicon or a metal and / or

- structured in a grid-like manner.

12.Verfahren according to claim 1, characterized in that above the first (510) and second (535) electrode, a mass element (570) is applied to the membrane with a defined mass, wherein it is provided that the mass element by means of a local Abscheideverfahrens, a Dispensing method, a screen printing method or a micromechanical structuring method is generated.

13.A method according to claim 12, characterized in that a plurality of membrane cells, consisting of a first (510) and a second electrode (535), a lying between the electrodes cavity (520) and a membrane (540), on the semiconductor substrate (500 ) are generated, wherein on each membrane a different sized mass element (570) is applied.

14.Mikromechanische device, produced according to one of the methods described in claims 1 to 13, with a micromechanically monolithically integrated capacitive sensor element for detecting a physical quantity, in particular for detecting a pressure variable and / or an acceleration variable, wherein the sensor element at least

a first (110, 510, 620, 725) and a second electrode (135, 535, 640, 785) and

- A membrane (145, 540) and

- A cavity (120, 520, 630, 900).

15. Micromechanical device according to claim 14, characterized in that the micromechanical device has a reference element in addition to the micromechanically monolithically integrated sensor element, it being provided that the membrane of

Reference element support portions (400, 410), by means of which an electrically isolated mechanical connection of the membrane or the second electrode is generated to the substrate.

lό.Mikromechanische device according to claim 14, characterized in that for detecting the physical size

- The second electrode (135, 535, 640, 785) has the ground potential and the detection of the physical quantity in dependence on the charges on the first electrode (110, 510, 620, 725) takes place or

- The third electrode has the ground potential and the detection of the physical quantity in dependence on the charge of one of the other two electrodes.

17.Mikromechanische device according to claim 14, characterized in that for detecting an acceleration variable, the membrane has a mass element (570) (120, 520, 630, 900) (135, 535, 640, 785) above the cavity, wherein in particular provided in that the mass element is rigidly connected to a layer forming the membrane.

The micromechanical device according to claim 17, characterized in that a plurality of membrane cells, consisting of a first and a second electrode, an intermediate cavity and a membrane, are produced on the semiconductor substrate, wherein each membrane is associated with a different sized mass element.