EP1780791A2 - Gehäuse für Leistungsschaltung und dessen Herstellungsverfahren - Google Patents

Gehäuse für Leistungsschaltung und dessen Herstellungsverfahren Download PDF

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Publication number
EP1780791A2
EP1780791A2 EP06255421A EP06255421A EP1780791A2 EP 1780791 A2 EP1780791 A2 EP 1780791A2 EP 06255421 A EP06255421 A EP 06255421A EP 06255421 A EP06255421 A EP 06255421A EP 1780791 A2 EP1780791 A2 EP 1780791A2
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EP
European Patent Office
Prior art keywords
substrate
power semiconductor
electrical interconnects
membrane
circuit package
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EP06255421A
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English (en)
French (fr)
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EP1780791B1 (de
EP1780791A3 (de
Inventor
Eladio Clemente Belgado
Richard Alfred Beaupre
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General Electric Co
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General Electric Co
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Publication of EP1780791A3 publication Critical patent/EP1780791A3/de
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
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    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
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    • H01L2924/11—Device type
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    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
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    • H05K1/145—Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit

Definitions

  • the invention relates generally to power circuit packages and fabrication methods.
  • High power semiconductor modules are generally packaged with brazed or direct bond copper to ceramic substrates. Such packaging is expensive and thus typically limited to high performance applications. Some expense has been mitigated by reducing the amount of substrate material, and some reliability has increased when power overlay assemblies such as described in commonly assigned Ozmat et al. US6377461 are used to replace wire bonds. Additional costs savings and reliability improvements would be desirable.
  • a power circuit package comprises a base and a power semiconductor module.
  • the base comprises a substrate and a plurality of interconnect circuit layers over the substrate.
  • Each interconnect circuit layer comprises a substrate insulating layer patterned with substrate electrical interconnects.
  • the base further includes via connections extending from a top surface of the substrate to at least one of the substrate electrical interconnects.
  • the power semiconductor module comprises power semiconductor devices each comprising device pads on a top surface of the respective power semiconductor device and backside contacts on a bottom surface of the respective power semiconductor device with the power semiconductor devices being coupled to a membrane structure.
  • the membrane structure comprises a membrane insulating layer and substrate electrical interconnects over the membrane insulating layer and selectively extending to the device pads.
  • the backside contacts are coupled to selected substrate electrical interconnects or via connections.
  • a method for fabricating a power circuit package comprises: providing a base comprising a substrate, a plurality of interconnect circuit layers over the substrate with each comprising a substrate insulating layer patterned with substrate electrical interconnects, and via connections extending from a top surface of the substrate to at least one of the electrical interconnects; providing a power semiconductor module comprising power semiconductor devices each comprising device pads on a top surface and backside contacts on a bottom surface, the power semiconductor devices being coupled to a membrane structure, the membrane structure comprising a membrane insulating layer and membrane electrical interconnects over the membrane insulating layer and selectively extending to the device pads; and mounting the power semiconductor module to selected electrical interconnects or via connections of the base.
  • FIG. 1 is a sectional expanded view of components 11 for a power circuit package in accordance with various embodiments of the present invention.
  • FIG. 2 is a sectional side view of a soldering stage in accordance with one embodiment of the present invention
  • FIG. 3 is a sectional side view of a soldering stage in accordance with another embodiment of the present invention
  • FIG. 4 is a sectional side view of a power circuit package 10 in accordance with one embodiment of the present invention which uses the components shown in FIG. 1.
  • power circuit package 10 comprises a base 12 and a power semiconductor module 26.
  • Base 12 comprises a substrate 14, a plurality of interconnect circuit layers 16 over substrate 14 with each comprising a substrate insulating layer 18 patterned with substrate electrical interconnects 20.
  • Base 12 further comprises via connections 22, 24 extending from a top surface of substrate 14 to at least one of the substrate electrical interconnects 20.
  • Power semiconductor module 26 comprises power semiconductor devices 28 each comprising device pads 30 on a top surface of the respective power semiconductor device and backside contacts 31 on a bottom surface of the respective power semiconductor device.
  • Power semiconductor devices 28 are coupled to a membrane structure 32 which comprises a membrane insulating layer 34 and membrane electrical interconnects 36 over membrane insulating layer 34 and selectively extending to device pads 30.
  • Backside contacts 31 are coupled to selected substrate electrical interconnects 20 or via connections 22, 24.
  • Substrate 14 may comprise any structurally appropriate material and typically comprises a material which is not electrically conductive or an electrically conductive material which is coated by an electrically insulating material. It is also beneficial to select substrates with low thermal impedances to allow heat to pass from power semiconductor devices 28.
  • substrate 14 comprises a structure that is known in the trade as an insulated metal substrate (IMS).
  • IMS insulated metal substrate
  • the conductive portion of the IMS comprises copper or an aluminum silicon carbide metal matrix composite.
  • Substrate insulating layers 18 typically comprise a non-electrically conductive material such as a ceramic filled epoxy based laminate, a polyimide, or a ceramic. In one example, the thickness of a substrate insulating layer 18 is about 0.008 inches (0.2 millimeters). A substrate insulating layer adjacent to a an electrically conductive substrate may act as the insulation for the electrically conductive substrate. As used in the context of interconnect circuit layer 16, a substrate insulating "layer” 18 means "at least one layer" (that is, layer 18 may comprise a single layer or several overlying layers).
  • Substrate electrical interconnects 20 are patterned to provide desired electrical paths and typically comprise a material such as copper.
  • Substrate electrical interconnects 20 may comprise a uniform material or layers of material if desired to improve adhesion or finishing.
  • a substrate electrical interconnect has a thickness of about 0.0058 inch (0.15 millimeters).
  • a via connection 22 or 24 is used to provide an electrical path, a thermal path, or an electrical and thermal path.
  • Typical materials for via connections 22, 24 include materials such as copper.
  • the diameter size and number of via connections per component will also vary according to the component with diameter size, number of via connections, or both increasing as thermal or electrical needs increase. If desired, additional buried via connections may be used to interconnect intermediate substrate electrical interconnects as shown by via connection 23 in FIG. 1.
  • via connections when spanning multiple substrate insulating layers, are formed by removing the desired portion of the substrate insulating layer and applying the electrically conductive material on an insulating-layer by insulating-layer basis.
  • via connection portion 17 is formed directly over and coupled to via connection portion 15
  • via connection 19 is formed directed over and coupled to via connection portion 17.
  • filler material (not shown) can be applied to an interior portion of the via connection to prevent voids.
  • any such filler material typically comprises a thermally conductive material.
  • Power semiconductor devices 28 of power semiconductor module 26 include devices such as diodes, transistors, integrated gate bipolar transistors, or any type of power semiconductor or other semiconductor having multiple functions for control or sensing.
  • Power shims may be used to couple connections from a top side of a power semiconductor device 28 down to base 12.
  • One such power shim 29 is shown for purposes of example.
  • Membrane structure 32 may comprise either a single layer structure (as shown) or a multi-layer structure (not shown for the membrane structure but of the type shown with respect to the interconnect circuit layers 16 of base 12).
  • Membrane insulating layer 34 typically comprises an organic dielectric material such as a polymer or, in an even more specific embodiment, a polyimide.
  • organic dielectric material such as a polymer or, in an even more specific embodiment, a polyimide.
  • polyetherimide such as ULTEM ® polyetherimides (General Electric) or UPIMOL ® resins (UBE Industries).
  • ceramic filler materials may be included, as described in aforementioned US6377461 .
  • Membrane electrical interconnects 36 typically comprise a metal such as copper.
  • the embodiment of FIG. 1 illustrates a more specific layered electrical interconnect embodiment comprising a starter layer 39, a primary layer 41, and a finish layer 43.
  • starter layer 39 comprises titanium
  • primary layer 41 comprises copper with a thickness of about 0.005 inches (0.13 millimeters)
  • finish layer 43 comprises nickel-gold.
  • the membrane electrical interconnects have spaces 37 therebetween to separate electrical paths.
  • power semiconductor devices 28 are attached to membrane structure 32 with an adhesive 35 such as a glue or a partially cured polymer resin.
  • the membrane structure may further include integral passive elements (not shown) of the type described in commonly assigned Wojnarowski et al. US5683928 , US 5849623 , US5872040 , and US 6040226 .
  • Backside contacts 31 are coupled to selected substrate electrical interconnects 20 or via connections 22, 24.
  • "or” means either one or both.
  • coupling is achieved by use of any suitable solder 52.
  • the solder comprises a screen printed solder paste.
  • Applying power semiconductor module 26 to base 12 which already has substrate electrical interconnects 20 thereon provides many advantages including, for example, enabling a simple technique for increased reliability and functionality by integrating a low thermal impedance base with interconnections, which may be used for power and signal purposes, in combination with the power semiconductor module.
  • surface mount components 38, 40, and 42 are coupled to selected substrate electrical interconnects 20 or via connections 22, 24. This embodiment gains even more benefit from having the interconnect circuit layers 16 of base 12 because surface mount components 38 and 40 are positioned on a common plane as power semiconductor module 26.
  • surface mount components 38 and 40 are soldered simultaneously along with power semiconductor module 26 as represented by use of a common solder 52 in FIG. 2.
  • a multi-step soldering process is used. Multi-step embodiments are useful, for example, in mounting a specific layer of components first, and then, with a lower temperature solder, adding additional components to another layer of the structure.
  • at least two types of solder are used for coupling of the power semiconductor module and the surface mount components.
  • one type of solder 52 is used for coupling the power semiconductor module having a higher reflow temperature than another type of solder 54 which is used for coupling at least one surface mount component.
  • Surface mount components 38 and 40 typically comprise at least one component selected from the group consisting of passive surface components and active surface components.
  • passive surface components include resistors, capacitors, and inductors.
  • active surface components include gate drive circuits, current sensors, voltage sensors, thermal sensors, processing electronics (which may be wired or wireless and may include components such as level shifters, converters, filters, and preamplifiers, for example), optoelectronics, and conditioning electronics.
  • potting material 58 at least partially surrounds power semiconductor module 26.
  • appropriate potting materials include epoxies and silicones.
  • One useful technique for applying the potting material is to use a frame 50.
  • frame 50 is coupled to the top surface of the substrate for supporting the potting material as it is poured or injected into the cavity formed by base 12 and frame 50.
  • underfill material (not shown) is provided in the spaces between power semiconductor devices 28 under power semiconductor module 26 prior to application of potting material 58 by any appropriate technique with capillary action filling being one example.
  • Frame 50 may remain in position for fabrication ease or structural support. Alternatively, frame 50 may be removed after the potting material has been provided. If frame 50 remains in position, it is useful to provide frame 50 with frame pathways 50 to line up to any base pathways 13.
  • Output connectors 44 may additionally be coupled to selected substrate electrical interconnects 20 or via connections 22, 24. Typically output connectors 44 are provided before the application of potting material 58 so that the potting material partially surrounds the output connectors in a manner that output connectors 44 remain accessible for external coupling. In one example, output connectors 44 include output connector pathways 46 for receiving external plugs (not shown).
  • Surface mount components 42 may further include components which are mounted to a top surface of power semiconductor module 26 (typically with solder 56). Or, in an alternative embodiment, cooling is provided on both sides of the power semiconductor module by thermal and electrical via connections 22 on a bottom surface and by a cooling mechanism on the top surface. In one top surface cooling example, as shown in FIG. 5, a heat exchanger 62 is coupled to a top surface of the membrane structure by a thermal interface material 60.
  • Thermal interface material 60 comprises a thermally conductive material which is either electrically insulating or, if electrically conductive, includes an electrical insulator layer (not shown) as its top surface for positioning adjacent heat exchanger 62.
  • thermal interface material 50 comprises a ceramic filled polymer pad such as SARCON XR-M TM available from Fujipoly America Corp.
  • Other example materials for thermal interface material 60 include ceramic filled silicone, carbon fiber filled pads, and conventional thermal greases.
  • Heat exchanger 62 may comprise an air cooled or liquid cooled heat exchanger, for example.
  • substrate 14 comprises a metal or metal composite material and includes embedded channels 70 therein to permit incorporation of a heat exchanger and to avoid needing any other cooling structures for the package.
  • the channels within the substrate can be designed to provide channels for cooling using fluids, gasses or phase changing material. Exemplary embodiments for integrated cooling channels are described in commonly assigned Stevanovic et al., US Patent Application Number 10/998707 filed 24 November 2004 .
  • substrate 14 it is useful to attach substrate 14 to a heat exchanger (not shown) to facilitate power semiconductor device cooling.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
EP06255421.7A 2005-10-26 2006-10-23 Gehäuse für Leistungsschaltung und dessen Herstellungsverfahren Active EP1780791B1 (de)

Applications Claiming Priority (1)

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US11/259,992 US7518236B2 (en) 2005-10-26 2005-10-26 Power circuit package and fabrication method

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EP1780791A2 true EP1780791A2 (de) 2007-05-02
EP1780791A3 EP1780791A3 (de) 2011-01-19
EP1780791B1 EP1780791B1 (de) 2019-11-27

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EP (1) EP1780791B1 (de)
JP (1) JP5129472B2 (de)
KR (1) KR101323416B1 (de)
CN (1) CN100561735C (de)
CA (1) CA2563480C (de)
IL (1) IL178737A0 (de)

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US8232637B2 (en) * 2009-04-30 2012-07-31 General Electric Company Insulated metal substrates incorporating advanced cooling
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CN1956192A (zh) 2007-05-02
IL178737A0 (en) 2007-02-11
EP1780791B1 (de) 2019-11-27
CN100561735C (zh) 2009-11-18
US20070090464A1 (en) 2007-04-26
EP1780791A3 (de) 2011-01-19
CA2563480C (en) 2016-02-02
KR101323416B1 (ko) 2013-10-30
US7518236B2 (en) 2009-04-14
JP2007123884A (ja) 2007-05-17
JP5129472B2 (ja) 2013-01-30
CA2563480A1 (en) 2007-04-26
KR20070045122A (ko) 2007-05-02

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