EP1726038A1 - Procede de production d'un transistor bipolaire dote d'une borne de base amelioree - Google Patents

Procede de production d'un transistor bipolaire dote d'une borne de base amelioree

Info

Publication number
EP1726038A1
EP1726038A1 EP05706930A EP05706930A EP1726038A1 EP 1726038 A1 EP1726038 A1 EP 1726038A1 EP 05706930 A EP05706930 A EP 05706930A EP 05706930 A EP05706930 A EP 05706930A EP 1726038 A1 EP1726038 A1 EP 1726038A1
Authority
EP
European Patent Office
Prior art keywords
layer
emitter
dopant
base
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05706930A
Other languages
German (de)
English (en)
Inventor
Gerald Meinhardt
Jochen Kraft
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram AG
Original Assignee
Austriamicrosystems AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Austriamicrosystems AG filed Critical Austriamicrosystems AG
Publication of EP1726038A1 publication Critical patent/EP1726038A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66242—Heterojunction transistors [HBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H01L29/66287—Silicon vertical transistors with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation

Definitions

  • the invention relates to a method for producing a bipolar transistor with an emitter, a collector and with a base layer divided into an intrinsic and an extrinsic base, and a method for producing the transistor.
  • the invention also uses the principle of a differential base, with a usually weakly doped, crystalline semiconductor layer being initially provided as the base layer.
  • a region of this base layer intended for the later extrinsic base is made conductive by the diffusion of a dopant from the first?
  • Type of doped from a dielectric layer deposited above so that a low-resistance base connection can be realized from it.
  • the low resistance of the base connection or the extrinsic base enables a transistor with only short switching times or with a high maximum switching frequency. Since the intrinsic base has a lower doping than the extrinsic one, the disadvantages associated with a high doping are avoided. In particular, this suppresses the tunnel current between a later, highly doped emitter and the (not here) highly doped intrinsic base.
  • the diffusion from the dopant-containing dielectric layer has the advantage that there are no implant-related defects and imperfections in the base layer that could promote the diffusion beyond the desired extent and thus results that are difficult to reproduce would deliver.
  • the transistor produced according to the invention is preferably designed as an npn bipolar transistor. This means that the base layer, like the dielectric layer, is p-doped, or that the dopant of the first conductivity type can produce p-doping, while the dopant of the second conductivity type can produce n-doping.
  • the transistor according to the invention is also possible to design the transistor according to the invention as a pnp bipolar transistor.
  • a semiconductor layer is applied for the emitter layer, in particular a polycrystalline, amorphous or monocrystalline layer, which is doped with a dopant of the second conductivity type. However, it is also possible to let the emitter layer grow epitaxially.
  • the emitter layer is then structured.
  • the implantation mask can then be produced over the emitter layer or the structured emitter and consists, for example, of a photoresist layer and, if appropriate, further layers arranged below it, for example oxide and / or nitride layers.
  • a photoresist layer is preferably used for structuring the emitter, which initially remains on the emitter and can later be used as an implantation mask for doping the dielectric layer.
  • a semiconductor which is lightly doped with a dopant of the first conductivity type is then deposited as a base layer over the semiconductor wafer with the defined transistor regions.
  • the growth or deposition takes place under epitaxial conditions, the base layer also growing monocrystalline directly over a crystalline substrate material, while growing over the oxide regions or other non-crystalline regions in polycrystalline or amorphous form. It is possible to apply and structure further dielectric intermediate layers between the semiconductor wafer and the epitaxial base layer before the epitaxy. These can serve for additional electrical insulation of the base layer from the semiconductor wafer.
  • the intermediate layer or intermediate layers are then structured such that a corresponding opening is provided at least in the active transistor region.
  • the dopant is then diffused into the base layer in a controlled thermal step.
  • the diffusion can be managed in such a way that the dopant diffuses out of the dielectric layer into the base layer to a desired depth.
  • An undesirable lateral diffusion of the Dopant can be minimized within the base layer, so that the distribution of the dopant originally specified by the implantation mask can also be transferred to the base layer and thus leads to a desired structuring of the transistor.
  • the dielectric layer can be removed, for example by etching.
  • transistor layers and, if appropriate, the layer provided with germanium can, in addition to the dopant and the optionally present second semiconductor, also have further doping, which determine the properties of the semiconductor.
  • one or more of the transistor layers can have a defined content of carbon and / or nitrogen.
  • FIG. 7 shows a finished bipolar transistor in a schematic cross section
  • Figure 1 shows the arrangement according to the definition of the transistor areas.
  • a conductive connection to the collector connection region can also be created outside the active transistor region via a doping called sinker.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

L'invention concerne un procédé de production d'un transistor bipolaire amélioré pourvu d'une borne de base de basse impédance. Ce procédé consiste à déposer une couche diélectrique sur le substrat semi-conducteur et à effectuer un fort dopage par un masque d'implantation. Dans une étape thermique contrôlée consécutive, le dope est diffusé à l'intérieur du substrat semi-conducteur à partir de la couche diélectrique qui sert de dépôt de dope. Cela permet de faire apparaître une zone de basse impédance qui définit avec soin la base extrinsèque.
EP05706930A 2004-03-18 2005-01-19 Procede de production d'un transistor bipolaire dote d'une borne de base amelioree Withdrawn EP1726038A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004013478A DE102004013478B4 (de) 2004-03-18 2004-03-18 Verfahren zur Herstellung eines Bipolartransistors mit verbessertem Basisanschluss
PCT/EP2005/000500 WO2005098926A1 (fr) 2004-03-18 2005-01-19 Procede de production d'un transistor bipolaire dote d'une borne de base amelioree

Publications (1)

Publication Number Publication Date
EP1726038A1 true EP1726038A1 (fr) 2006-11-29

Family

ID=34960327

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05706930A Withdrawn EP1726038A1 (fr) 2004-03-18 2005-01-19 Procede de production d'un transistor bipolaire dote d'une borne de base amelioree

Country Status (4)

Country Link
US (1) US7618871B2 (fr)
EP (1) EP1726038A1 (fr)
DE (1) DE102004013478B4 (fr)
WO (1) WO2005098926A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004013478B4 (de) * 2004-03-18 2010-04-01 Austriamicrosystems Ag Verfahren zur Herstellung eines Bipolartransistors mit verbessertem Basisanschluss
US7807539B1 (en) 2007-03-26 2010-10-05 Marvell International Ltd. Ion implantation and process sequence to form smaller base pick-up
EP2202784B1 (fr) * 2008-12-29 2017-10-25 Imec Procédé de fabrication d'une jonction
US8927379B2 (en) * 2012-09-26 2015-01-06 International Business Machines Corporation Method to bridge extrinsic and intrinsic base by selective epitaxy in BiCMOS technology

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3886569A (en) * 1970-01-22 1975-05-27 Ibm Simultaneous double diffusion into a semiconductor substrate
EP0219243A2 (fr) * 1985-10-11 1987-04-22 Advanced Micro Devices, Inc. Procédé pour la fabrication d'un transistor bipolaire
EP0430274A3 (en) * 1989-12-01 1993-03-24 Seiko Instruments Inc. Method of producing bipolar transistor
JPH03265131A (ja) * 1990-03-15 1991-11-26 Fujitsu Ltd 半導体装置の製造方法
JPH05110079A (ja) * 1991-10-18 1993-04-30 Fujitsu Ltd 半導体装置の製造方法
US5541121A (en) * 1995-01-30 1996-07-30 Texas Instruments Incorporated Reduced resistance base contact method for single polysilicon bipolar transistors using extrinsic base diffusion from a diffusion source dielectric layer
DE69841435D1 (de) * 1997-07-11 2010-02-25 Infineon Technologies Ag Ein herstellungsverfahren für hochfrequenz-ic-komponenten
US6248650B1 (en) * 1997-12-23 2001-06-19 Texas Instruments Incorporated Self-aligned BJT emitter contact
FR2779573B1 (fr) 1998-06-05 2001-10-26 St Microelectronics Sa Transistor bipolaire vertical comportant une base extrinseque de rugosite reduite, et procede de fabrication
DE19840866B4 (de) 1998-08-31 2005-02-03 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik Verfahren zur Dotierung der externen Basisanschlußgebiete von Si-basierten Einfach-Polysilizium-npn-Bipolartransistoren
US6239477B1 (en) * 1998-10-07 2001-05-29 Texas Instruments Incorporated Self-aligned transistor contact for epitaxial layers
SE517833C2 (sv) * 1999-11-26 2002-07-23 Ericsson Telefon Ab L M Metod vid tillverkning av en bipolär kiseltransistor för att bilda basområden och öppna ett emitterfönster samt bipolär kiseltransistor tillverkad enligt metoden
US6506659B2 (en) 2001-03-17 2003-01-14 Newport Fab, Llc High performance bipolar transistor
US6699765B1 (en) * 2002-08-29 2004-03-02 Micrel, Inc. Method of fabricating a bipolar transistor using selective epitaxially grown SiGe base layer
US6686250B1 (en) * 2002-11-20 2004-02-03 Maxim Integrated Products, Inc. Method of forming self-aligned bipolar transistor
US6965133B2 (en) * 2004-03-13 2005-11-15 International Business Machines Corporation Method of base formation in a BiCMOS process
DE102004013478B4 (de) * 2004-03-18 2010-04-01 Austriamicrosystems Ag Verfahren zur Herstellung eines Bipolartransistors mit verbessertem Basisanschluss
JP2006080508A (ja) * 2004-08-27 2006-03-23 Asahi Kasei Microsystems Kk 半導体デバイス及びその製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2005098926A1 *

Also Published As

Publication number Publication date
WO2005098926A1 (fr) 2005-10-20
US20070269953A1 (en) 2007-11-22
DE102004013478B4 (de) 2010-04-01
DE102004013478A1 (de) 2005-10-06
US7618871B2 (en) 2009-11-17

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