EP1723523A1 - Procede et circuit integre permettant d'ameliorer la resistance aux interferences - Google Patents

Procede et circuit integre permettant d'ameliorer la resistance aux interferences

Info

Publication number
EP1723523A1
EP1723523A1 EP05716727A EP05716727A EP1723523A1 EP 1723523 A1 EP1723523 A1 EP 1723523A1 EP 05716727 A EP05716727 A EP 05716727A EP 05716727 A EP05716727 A EP 05716727A EP 1723523 A1 EP1723523 A1 EP 1723523A1
Authority
EP
European Patent Office
Prior art keywords
error
chip
integrated circuit
time
filter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05716727A
Other languages
German (de)
English (en)
Inventor
Wolfgang Fey
Micha Heinz
Adrian Traskov
Frank Michel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Continental Teves AG and Co OHG
Original Assignee
Continental Teves AG and Co OHG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Continental Teves AG and Co OHG filed Critical Continental Teves AG and Co OHG
Publication of EP1723523A1 publication Critical patent/EP1723523A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0772—Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0736—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0736—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function
    • G06F11/0739—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function in a data processing system embedded in automotive or aircraft systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G06F11/1645—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components and the comparison itself uses redundant hardware

Definitions

  • the invention relates to integrated circuits, in particular in electronic control units, which are preferably components of motor vehicle control units.
  • the control units are control units for motor vehicle brake systems.
  • Such control devices are suitable, among other things, for carrying out safety-critical regulations.
  • the motor vehicle control units preferably contain control programs such as ABS, ASR, ESP and the like. Due to the high safety requirements, the control systems which are formed by the integrated circuits include safety circuits which help to identify a failure or an error and initiate suitable measures, such as switching off the entire system or emergency operation, by measures which partially maintain the operation of the controlled system.
  • Control systems with integrated circuits that contain microprocessors are common for the tasks outlined above. In order to prevent malfunctions or to recognize them, it makes sense to provide at least two processor cores. Although three or more processor cores would further increase security, this is not always desirable for reasons of cost in connection with the very high number of pieces common in the field of automotive technology. There is therefore a need for inexpensive circuits with a high level of security.
  • error-relevant communication is preferably carried out via two error lines ERR and ERR_N.
  • the invention is based on and improves on the above system in order to further improve the immunity to interference.
  • the control system can also have one or more monitoring circuits, which are accommodated in particular on one or more further separate chips (watchdog).
  • the processor chip and power chip are preferably connected via the lines ERR and ERR_N ⁇ .
  • the inventive method w: j.rd ensures that there is no restriction on the error monitoring of the processor chip by the power chip compared to the previous, unfiltered solution. This means that no error pulses are lost.
  • the integrated circuit comprises at least one microprocessor chip or multiprocessor microcontroller and at least one further module, in particular one is an integrated module.
  • the integrated component preferably comprises power components and is therefore, in particular, a mixed-signal component.
  • the invention can also be carried out in particular in the following way:
  • microcontroller processing chip
  • mixed signal chip power chip
  • FIG. 1 shows a system overview of the interconnected chips
  • Fig. 2 is an illustration of the filter characteristic in connection with the error lines and
  • Fig. 3 is a diagram showing the time behavior of the signals (timing diagram).
  • FIG. 1 A system overview is given in FIG. 1:
  • the microcontroller 1 (processor chip) is connected to the mixed signal IC 2 (power chip) via the error lines 3 and 4 and via the SPI interface 5.
  • the microcontroller 1 consists of two independent processor cores (Core A and Core B), the operations of which are continuously checked in terms of hardware by the comparison blocks Compare A and Compare B. If an error is detected during this comparison operation, then this error information must be reliably transmitted to power chip 2 via lines 3 ERR and 4 ERR_N.
  • an error is preferably signaled by changing the level on an error line (e.g. from logic "high” to “low”).
  • each of the lines 3 ERR and 4 ERR_N changes the signal level once for each error.
  • the levels at ERR and ERR_N are preferably opposite or complementary.
  • the mixed signal IC 2 generally works and preferably considerably slower than the microcontroller. For this reason, it must be ensured that the minimum pulse width T min on the signal lines ERR and ERR_N is not is exceeded. Otherwise it is possible that module 2 "overlooks" an error.
  • the mixed signal IC filters the ERR / ERR_N signals each with a filter device 7, 7 '. This filtering is done digitally in particular.
  • a filter time constant Tpii te r is preferably provided.
  • the minimum pulse width T min is preferably much larger than the internal system clock of the power chip 2.
  • the filtering of the signals ERR / ERR_N advantageously suppresses external interference (electrostatic, magnetic or electromagnetic interference), thereby increasing the reliability and availability of the system.
  • Level Compare In the "Level Compare ,, 8, 8 'blocks, a redundant check is carried out to determine whether both error signals have opposite levels. Equal levels on ERR and ERR_N lead to an error and are output outside of a test routine on the signals "Error Detected ,, 9, 9 '.
  • the "Pulse Detect ,, 10, 10 'block searches for edges on the filtered ERR / ERR_N signals.
  • the signal outputs of block "Level Compare” 8 and “Pulse Detect” 10 are logically linked by an OR block and form the output "ERR Detected A" 9. The same applies to the redundant path 11 '.
  • a watchdog test routine with artificial error transmission is signaled at regular intervals T oop via the SPI interface 5 from processor chip 1 to power chip 2.
  • this test routine the error detection in the microcontroller and the connections via the error lines between the power chip and the processor chip are tested.
  • An error is generated in the microcontroller via software-controlled test structures, which leads to a single level change on the ERR / ERRN lines at the output of the "Toggle and Delay" blocks.
  • test routine (“watchdog transmission") is active
  • power chip 1 defines a time window in block 50 via bus 5.
  • a valid error signal for testing is considered in particular a signal which consists of exactly one edge change on the filtered ERR and ERR_N- Management exists.
  • An error is detected by the block "Pulse Detect" 10 (or 10 'in redundant branch B) if no or more than one edge occurs on the filtered signals ERR filter or ERR_N filter within the time window (see timing diagram in Fig. 2).
  • the level monitor 8 is switched off during the watchdog transmission by means of line 18 (18 'in the redundant branch B), since the level change to ERR and ERR_N cannot take place absolutely synchronously due to different signal propagation times.
  • block 50 At the end of the time window defined by block 50, the signals ERR / ERR_N must again have opposite levels, since level monitoring of the filtered signals now starts again. If there is a level change on the filtered signals ERR or ERR_N outside the watchdog time window, this is recognized directly as an error by the block "Pulse Detect" 10 and output on line "Err Detected" 9. To achieve this functionality, block 50 is connected to block 10 via a control line.
  • Block "Level Compare” 8 is also provided redundantly (see block 8 '). Block 8 checks whether the error signals of the complementary error lines are both present. If this is not the case, for example if one of the error lines is defective, an error is output.
  • the fault detection for lines 3 ERR and 4 ERR_N in power chip 2 is basically designed redundantly.
  • a separate error detection circuit 11 and 11 ', each with its own error line 9 "ERR-Detected A" and 9'"Err-DetectedB", is therefore preferably provided for each computer core.
  • filter 7 is preferably only available for one of the existing fault lines 3 and 4.
  • circuit 11 ' there is also only one filter circuit 7'.
  • the output of the filter 7 or 7' with the connection points 12 and 12 'via cross lines 13 and 13' becomes the inputs of the "level compare" circuits 8 and 8 'in addition to the error signals 3 and 4 fed on the input side.
  • ERR filter 7 is preferably designed as a digital up / down counter, which changes its counter reading depending on the input signal. If there is a signal with the digital low level at the input of the filter, the counter reading is reduced by one. If there is a high level, the counter reading is increased by one.
  • the possible meter readings are limited to the range from 0 to Z Ma ⁇ count. A possible signal curve is shown in FIG. The same applies to the filter 7 '.
  • FIG. 3 shows a timing diagram which shows the logic levels of the existing control lines as a function of time.
  • a possible definition of a watchdog time window in block 50 will now be explained with reference to this figure.
  • the watchdog time window in block "watchdog window” 50 is determined by processor chip 1 through SPI interface 5.
  • the watchdog time window 17 begins after the first rising edge 14 on the clock signal of the SPI carry SPICLK.
  • the delay TSync includes signal runtimes and the synchronization time between the external clock of the SPI interface and the internal power chip system clock.
  • the watchdog time window 17 ends after the rising edge 15 of CSWD_N. However, it must be ensured that the edges of the filtered signals ERR or ERR_N are still recognized within the active watchdog time window. For this reason, the time of edge 15 is followed by a delay time TinoDeia, in which the expected edge is still processed.
  • processor chip 1 only has to guarantee that the minimum pulse length T MI T on the signals ERR or ERR_N is not undercut.
  • processor chip 1 During an error check routine (watchdog transfer) in which a time window is defined via bus 5, it must be guaranteed that, in addition to the error caused by the test procedure, any additional error is reliably detected by power chip 2.
  • processor chip 1 must change the levels on the error lines ERR / ERR_N once for the first error that occurs. If another error occurs in processor chip 1 during the time T M , then this error must be delayed until the time T M m has elapsed. Then processor chip 1 must change the signal level again to ERR / ERR_N. This is done by means 6 or 6 '("toggle and delay"). In this case, power chip 2 either detects the double level change during the watchdog time window 17, or a level change is outside the time window 17. In both cases, power chip 2 recognizes the additional error.
  • a two level change at a distance of T Min is therefore sufficient in all cases to detect an error in the power chip.
  • the block "Toggle & Delay ,, 6 or 6 'therefore only has to transmit another error delayed by T Mln to the power chip in addition to the first error that occurs.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Hardware Redundancy (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Debugging And Monitoring (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)

Abstract

Selon ce procédé d'amélioration de la résistance d'un circuit (16) aux interférences, on transmet des signaux d'erreur entre au moins une puce d'un microprocesseur ou une microcommande (1) à processeurs multiples et au moins une autre composante (2) sous la forme d'un ou plusieurs signaux d'erreurs. A des fins de transmission, une longueur minimale d'impulsion indépendante de la fréquence d'horloge du microprocesseur ou des microprocesseurs est définie, à partir de laquelle un signal sur une ligne de transmission d'erreurs ayant une longueur déterminée d'impulsion est interprété comme une erreur. L'invention concerne également un circuit intégré conçu pour mettre en oeuvre ce procédé et comprenant au moins une puce d'un microprocesseur ou une microcommande (1) à processeurs multiples, ainsi qu'une autre composante (2) qui comprend notamment des composantes séparées de puissance, et un ou plusieurs dispositifs de propagation d'impulsions et/ou de retardement de signaux pour émettre successivement des impulsions d'erreur (6, 6') par au moins une ligne (3, 4) de transmission d'erreurs.
EP05716727A 2004-02-20 2005-02-17 Procede et circuit integre permettant d'ameliorer la resistance aux interferences Withdrawn EP1723523A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004008809 2004-02-20
PCT/EP2005/050707 WO2005081107A1 (fr) 2004-02-20 2005-02-17 Procede et circuit integre permettant d'ameliorer la resistance aux interferences

Publications (1)

Publication Number Publication Date
EP1723523A1 true EP1723523A1 (fr) 2006-11-22

Family

ID=34877079

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05716727A Withdrawn EP1723523A1 (fr) 2004-02-20 2005-02-17 Procede et circuit integre permettant d'ameliorer la resistance aux interferences

Country Status (6)

Country Link
US (1) US8578258B2 (fr)
EP (1) EP1723523A1 (fr)
JP (1) JP2007535234A (fr)
KR (1) KR20060131842A (fr)
CN (1) CN1922581A (fr)
WO (1) WO2005081107A1 (fr)

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US8650440B2 (en) 2008-01-16 2014-02-11 Freescale Semiconductor, Inc. Processor based system having ECC based check and access validation information means
DE102016211124A1 (de) * 2016-06-22 2017-12-28 Robert Bosch Gmbh Verfahren und Vorrichtung zum Bearbeiten von Binärcodedaten
CN109088621B (zh) * 2018-07-27 2022-07-05 天津经纬恒润科技有限公司 一种信号滤波方法及装置
CN113193812B (zh) * 2021-05-08 2024-04-26 中国北方车辆研究所 一种变频驱动电机电磁兼容滤波系统
CN114759780B (zh) * 2022-06-15 2022-09-02 无锡硅动力微电子股份有限公司 开关电源中集成控制器的抗干扰方法、装置及集成控制器

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Also Published As

Publication number Publication date
US20070205930A1 (en) 2007-09-06
WO2005081107A1 (fr) 2005-09-01
KR20060131842A (ko) 2006-12-20
JP2007535234A (ja) 2007-11-29
US8578258B2 (en) 2013-11-05
CN1922581A (zh) 2007-02-28

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