Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • G—PHYSICS
  • G02—OPTICS
  • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
  • G02B1/00—Optical elements characterised by the material of which they are made; Optical coatings for optical elements
  • G02B1/02—Optical elements characterised by the material of which they are made; Optical coatings for optical elements made of crystals, e.g. rock-salt, semi-conductors
• • G—PHYSICS
  • G02—OPTICS
  • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
  • G02B5/00—Optical elements other than lenses
  • G02B5/18—Diffraction gratings
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02367—Substrates
  • H01L21/0237—Materials
  • H01L21/02373—Group 14 semiconducting materials
  • H01L21/02381—Silicon, silicon germanium, germanium
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02439—Materials
  • H01L21/02441—Group 14 semiconducting materials
  • H01L21/0245—Silicon, silicon germanium, germanium
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02494—Structure
  • H01L21/02496—Layer structure
  • H01L21/02505—Layer structure consisting of more than two layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02494—Structure
  • H01L21/02513—Microstructure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02521—Materials
  • H01L21/02524—Group 14 semiconducting materials
  • H01L21/02532—Silicon, silicon germanium, germanium
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
  • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T428/00—Stock material or miscellaneous articles
  • Y10T428/29—Coated or structually defined flake, particle, cell, strand, strand portion, rod, filament, macroscopic fiber or mass thereof

Definitions

• the present invention relates to the manufacture of a layer comprising iconductrice monocrystalline nanostructures or "quantum dots" of a first monocrystalline semiconductor material of a second material "monocrystalline semiconductor. More particularly, the present invention relates to the production of nanostructures in a silicon substrate Presentation of the prior art Such nanostructures or "quantum dots” are, for example, described in the document “Ge / Si self-assembled quantum dots gro n on Si (100) in an industrial high-pressure chemical vapor deposition reactor "by C. Hernandez, Y. Campidelli, D. Simon, D. Bensahel, I. Sagnes, G. Patriarche, P. Boucaus and S. Sauvage, published in J. Appl.
• the energy band gap of silicon between its valence and conduction bands is relatively small and the transitions are of the "indirect” type.
• indirect is meant that the passage of an electron from the valence band to the conduction band takes place in several jumps and not in a single jump as in the case of the material combinations of columns III and V.
• the silicon is then almost unusable as an emitter, that is to say converter of electrical energy into light energy. Indeed, due to the indirect nature of electronic transitions, they are highly dissipative and very weakly emitting.
• the relatively low energy band gap corresponds to the emission of p otons with a wavelength less than 1 ⁇ m, little used in the telecommunications field. . It has therefore been proposed to improve the optical properties, that is to say of emission and reception, of silicon by forming structures made up of a monocrystalline silicon network comprising germanium nanostructures (quantum dots). To obtain acceptable performance, for example a transmitter / receiver of suitable emissivity / receptivity, it is desirable to be able to produce several superimposed planes each containing several nanostructures. As explained in the article cited above, the formation of nanostructures results from a stress mechanism between crystallographic meshes of different dimensions, but relatively similar, of two semiconductors.
• this growth process causes, for example, the formation of germanium nanostructures on silicon from various deposition processes including molecular epitaxies, chemical vapor deposition under low pressure, or chemical vapor deposition under high vacuum. More particularly, to form quantum dots of germanium in silicon, epitaxy is carried out, for example, by continuous injection of germane (GeH4), on a monocrystalline silicon substrate. The first few atomic thicknesses deposited form a layer whose surface is regular but not homogeneous. Due to the constraints linked to the differences in crystal lattices, the surface has a sinusoidal "wave" shape.
• the upper surface of a germanium layer of a few atomic thicknesses, formed on silicon has hollows and bumps distributed evenly.
• a structure is a wavy plane of germanium.
• the crystallographic constraints - deformations of the natural germanium network cause the growth of nanostructures. This injection must be interrupted when the nanostructures or boxes have reached a desired dimension, before a coalescence of the nanostructures occurs, then the formation of a continuous layer containing dislocations.
• Figure 1 illustrates, in partial and schematic sectional view, the result of the repeated implementation of such a method.
• FIG. 2 illustrates, in partial and schematic top view, any of the corrugated planes 3 of FIG. 1.
• the current implementation of the constrained growth process of Stranski-Krastanow leads to nanostructure structures in particular as regards the dispersion of the dimensions (diameter) of the nanostructures when the number of wavy planes formed increases.
• the choice of the conditions of the epitaxy must then satisfy a compromise.
• a "optimal" temperature which corresponds to a maximum “controllable” growth rate, that is ie a speed as fast as possible to avoid the aforementioned defects, and slow enough to allow the epitaxy to be interrupted precisely at a desired stage (for example a few tens of monoatomic layers).
• the present inventors have already proposed to regularize the distribution of nanostructures from one plane to another and to reduce the dispersion of their dimensions by forming privileged nucleation sites by injection at the substrate 1 surface of a puff of germane before the growth of the foreground of nanostructures.
• the present invention aims to propose a monocrystalline semiconductor layer comprising monocrystalline semiconductor nanostructures distributed regularly.
• the present invention aims to provide such a layer in which the nanostructures have a dispersion of restricted dimensions.
• the present invention provides a monocrystalline layer of a first semiconductor material comprising monocrystalline nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystal lattice network. centered tetragonal.
• the first semiconductor material is silicon and the second semiconductor material germanium.
• the height of the tetragonal mesh is equal to the sum of two equal elementary values chosen from a range from 60 at 80% of the diameter of the nanostructures up to four times the diameter.
• the planar base of the centered tetragonal mesh is substantially square and has one side with a value between 50 and 300 nm.
• the present invention also provides a light source, comprising a layer according to any one of the preceding embodiments associated with an electrical excitation circuit.
• the source forms a coherent source.
• the source forms a diode.
• the present invention also provides a light trapping device, comprising a layer according to any one of the preceding embodiments.
• the present invention also provides a photodetector, comprising such a device.
• the present invention also provides a light or acoustic wave diffractor, comprising a layer according to any one of the preceding embodiments.
• the present invention also provides an optical or acoustic filter, comprising a layer according to any one of the preceding embodiments.
• FIG. 1 illustrates, in partial and schematic sectional view, a structure according to the state of the art
• Figure 2 described above illustrates, in partial and schematic top view, one of the planes of the structure of Figure 1
• Figure 3 illustrates, in partial and schematic sectional view, a semiconductor layer according to the present invention
• FIG. 4 is a simplified dispersion curve for nanostructures as a function of a thickness of silicon
• FIG. 5 illustrates, in partial and schematic perspective view, the mesh of the macro-network of a layer according to the present invention
• FIG. 6 is a simplified curve for the distribution of dimensions of the nanostructures; and FIG. 7 illustrates a mode of application of a layer according to the present invention.
• the present invention takes advantage of the inventors' studies on nanostructures of a first semiconductor material encapsulated in a layer of a second semiconductor material. By studying a structure comprising such germanium nanostructures encapsulated in silicon, the inventors determined a law of variation of the relative positions of the germanium nanostructures of two successive planes as a function of the thickness of silicon separating them.
• FIG. 3 illustrates, in partial and schematic sectional view, wavy planes of germanium nanostructures encapsulated in silicon.
• FIG. 4 illustrates, partially and schematically, a dispersion curve of the nanostructures as a function of the thickness of silicon separating two planes of nanostructures.
• the wavy planes of germanium nanostructures encapsulated in silicon are obtained by the repetition of successive depositions of germanium on a monocrystalline semiconductor substrate (for example, of silicon), then of silicon.
• the silicon deposited second serves as a substrate for the next successive deposition of germanium.
• the conditions for germanium epitaxy are known, for example described by Stranski- Krastanow. The constraints of the epitaxial growth of silicon will be defined later.
• FIG. 1 illustrates, in partial and schematic sectional view, wavy planes of germanium nanostructures encapsulated in silicon.
• FIG. 4 illustrates, partially and schematically, a dispersion curve of the nanostructures as a function of the thickness of
• FIG. 3 illustrates the structure obtained when, for identical conditions of epitaxial growth of germanium nanostructures, the thickness ⁇ QJ_ of silicon deposited thereafter is fixed by epitaxy and separating two wavy Stranski-Krastanow planes at a precise value chosen from a range predetermined.
• the epitaxy conditions are chosen so that the nanostructures have a diameter D of approximately 40 to 200 nm and a height H of approximately 10 to 30 nm.
• the nanostructures rest on a flat layer of germanium a few nanometers thick, typically 2 to 4 nm.
• each nanostructure of an upper plane is then laterally equidistant, in section view, of two nanostructures of the plane inferior.
• the inventors have found that the maximum offset effect appears before the thickness eg-L reaches the value of the diameter D of the nanostructures and is maintained at least up to this value, up to much higher values, double or triple of diameter D and being able to reach the quadruple of the diameter D.
• FIG. 5 partially represents three planes of nanostructures of a layer according to the invention. As illustrated in this figure, when the thickness of silicon eg-j_ is greater than the threshold Tg ⁇ , the nanostructures are self-organized in the volume of the layer according to a regular pattern of macro-network in the layer. Indeed, as has been indicated previously, the distribution of nanostructures or quantum dots of germanium in silicon is then perfectly homogeneous.
• the nanostructures of a given first plane are laterally equidistant from the nanostructures of a second upper plane themselves laterally equidistant from the nanostructures of a third superimposed plane. If one considers a set of three successive planes of nanostructures, these are therefore distributed according to a regular network with centered tetragonal mesh.
• the base surface of the mesh is substantially square, the nanostructures of a plane being equidistant, separated by a distance a substantially equal to the lateral deviation g multiplied by the square root of two.
• the height b of the mesh is substantially equal to twice the thickness egi-
• the side a of the square base of the mesh of the macro-network has a value between 50 and 300 nm.
• the value of the maximum difference g and therefore of the side a of the square base of the mesh of the macro-network is fixed essentially by the dimensions of the germanium nanostructures and in particular by their diameter. As indicated above in connection with FIG. 3, it is considered that successive wavy planes are formed under the same conditions of epitaxial growth. In practice, the inventors' measurements have shown that the value of the difference maximum g is of the order of the diameter D of the nanostructures to within a few percent.
• FIG. 6 illustrates, partially and schematically, the size distribution of the nanostructures.
• the curve in dotted lines represents the size distribution of the nanostructures in the known structure of FIGS. 1 and 2.
• the curve in solid lines represents the size distribution of the nanostructures in a layer according to the present invention. The comparison of these two curves shows that the distribution of the nanostructures in a layer according to the present invention is narrower.
• a monocrystalline semiconductor layer having a regular macro-network of nanostructures of a monocrystalline semiconductor material in another monocrystalline semiconductor material is capable of very numerous applications.
• the layer comprising the macro-network according to the present invention makes it possible to form devices which are sufficiently sensitive and in a range of wavelengths suitable for constituting devices for converting light signal / electrical signal.
• a layer according to the present invention can be used as a detector or as a transmitter of a light signal from an electrical set point.
• a layer according to the present invention can also be used as a light source outside the telecommunications field.
• a layer according to the present invention can be used to form a light emitting diode.
• a layer according to the present invention can be used to form a coherent light source such as a laser source.
• a layer according to the present invention can be used as a light trapping device such as a photodetector.
• the macro-array of quantum dots of the layer according to the present invention can also be used as a filter for a sound or light wave.
• the macro-network of the layer according to the present invention is perfectly stable, homogeneous and reproducible. It can also advantageously be used to diffract a wave.
• such a macro-network can constitute a Bragg diffractor capable of being used to collimate a beam.
• a semiconductor layer comprising corrugated Stranski-Krastanow planes of a first semiconductor material encapsulated in a second semiconductor material so that the thickness of the second material according to the present invention, the semiconductor is comprised between the threshold value Tg_ and the quadruple of the diameter of nanostructures of the first semiconductor material.
• an annealing will be carried out at a temperature of 700 to 900 ° C. Such annealing is intended for allow relaxation, that is to say stabilization and homogenization of the crystal structure.
• Those skilled in the art will also know how to complete the structure to form any desired device.
• a layer according to the present invention is susceptible of other applications.
• a layer comprising a macro-network according to the present invention can be used as an intermediate layer for modifying the crystalline parameters of a substrate.
• the upper silicon surface of a layer comprising a macro-network according to the present invention has a lattice parameter greater than that of a layer of silicon alone.
• the inventors have determined that the average lattice parameter of a layer of silicon encapsulating several wavy planes of germanium is equal to the parameter of a heteroatomic layer of SiGe comprising of the order of 30 to 50% of germanium.
• the inventors have further determined that such a modification of the silicon lattice parameter is carried out on a thickness less than that of a heteroatomic layer of SiGe with a gradually increasing proportion of germanium allowing the same parameter to be obtained.
• a silicon layer comprising a macro-network of germanium nanostructures can then be used as all or part of a pseudosubstrate, that is to say of a constrained silicon substrate (silicon with an enlarged elementary mesh).
• the inventors have determined that the upper surface of such a pseudo-substrate has a reduced defect rate.
• the offset of the germanium nanostructures from one level to the other of the macro-network advantageously makes it possible to reduce the vertical propagation of dislocations. So if a dislocation is created in an intermediate silicon layer between two planes of nanostructures, it tends to propagate vertically in a known manner. During the displacement of the nanostructures on the upper plane, a nanostructure can be placed on the path of propagation of the dislocation and therefore interrupt it.
• Such a pseudo-substrate is capable of very numerous applications.
• FIG. 7 illustrates, in partial and schematic sectional view, the formation, on a substrate 10 of monocrystalline silicon, of a pseudo-substrate 11 and of a layer 12 of silicon in which electronic components must be formed.
• the pseudo-substrate 11 comprises a lower part 14 resting on the substrate 10 and an upper part 16 on which the layer 12 rests.
• the lower part 14 consists of several planes PI, P2 and P3 of germanium nanostructures encapsulated in silicon.
• the upper part 16 consists of a heteroatomic layer of SiGe comprising a gradually increasing proportion of germanium.
• the thickness tl4 of the lower part 14 is less than the thickness of a gradual layer of SiGe having a proportion of 50% germanium at the surface.
• the thickness t16 of the upper part 16 is adjusted to obtain the lattice parameter corresponding to a given proportion of germanium in a silicon network, between 50 and 100%.
• the overall thickness of the pseudosubstrate 11 is therefore advantageously less than that of a simple gradual layer.
• the need to implement Stranski-Krastanow type growth of nanostructure plans does not lengthen the manufacturing times because it can be carried out in the epitaxy reactor used for the growth of the gradual layer.
• the time required to grow the few planes of nanostructures required is less than the time required to grow a pseudo-substrate with the same final lattice parameter.
• the number of planes of nanostructures is of the order of one to fifteen, preferably from one to ten to limit as much as possible the vertical propagation of dislocations.
• the inventors have determined that the surface density of defects in the lower part 14 is then reduced, and is of the order of 10 to 10-Vcm.2 instead of 10 ⁇ to l ⁇ / cm2 for a layer. gradual (2, Figure 1). As will be detailed below in relation to FIGS. 3A-C and 4, such a reduction is linked to a halt in the vertical propagation of the dislocations in silicon on the nanostructures.
• the layer 12 can be formed directly on a layer 11 consisting only of its lower part 14 comprising a macro-network of germanium nanostructures in silicon.
• the last layer of silicon in the lower part 14 can be used directly as a substrate in place of the layer 12.
• the macro-network is reflected above the nanostructures of the last plane by studs having the shape of a truncated faceted pyramid.
• the pyramids are "self-organized" on the surface in a regular form in a regular checkerboard whose dimensions of the boxes are of the order of the diameter D of the nanostructures.
• the self-organization is less regular, the studs or the gaps between the studs having a dimension, in plan view, greater than the diameter D.
• a regular surface can be advantageous in a certain number of applications.
• An example of such an application is the production of memory using MOS type transistors comprising a floating gate.
• the floating gate of the transistor in such a device, it has been found that it is desirable for the floating gate of the transistor to be made up of separate conductive elements embedded in an insulating layer.
• a multi-plane pseudo-substrate according to the present invention.
• the silicon is oxidized and then a conductive material is deposited.
• the irregular shape of the surface comprising truncated faceted pyramidal studs is preserved.
• the pads or depressions between the pads then serve as nucleation points for nanocrystals during subsequent deposition. These nanocrystals then constitute the floating grid.
• the oxide is an insulator with high dielectric permittivity.
• the present invention is susceptible to various variants and modifications which will appear to those skilled in the art.
• the dimensions of the nanostructures and of the layers of silicon separating two planes of nanostructures can be modified in any suitable manner, provided that the thickness of silicon remains within the defined range.
• the present invention is not limited to the specific examples of the preceding description.
• the nature of the materials considered above can be modified.
• the layer according to the invention is formed on a monocrystalline silicon semiconductor substrate.
• the substrate could be a silicon-germanium or germanium substrate.
• we considered a layer comprising germanium nanostructures embedded in silicon however the present invention also relates to a layer of silicon nanostructures embedded in germanium.
• the present invention is not limited to a silicon-based sector, but applies to any technological sector using a layer of monocrystalline semiconductor nanostructures of a given material embedded in another monocrystalline semiconductor material, one of the two materials being a binary or ternary alloy of elements chosen from the materials in column III of the periodic table and the other material being another binary or ternary alloy of elements chosen from the materials of the column
• Such a layer would for example be a layer of nanostructures of an alloy of indium, gallium and arsenic (InGaAs) in a substrate of gallium arsenide (GaAs) or indium phosphide (InP).
• InGaAs indium, gallium and arsenic
• GaAs gallium arsenide
• InP indium phosphide

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