Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/02—Digital function generators
  • G06F1/022—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers

Definitions

• the present invention relates to signal generators, frequency synthesizers, and devices incorporating signal generators and/or frequency synthesizers.
• DDS direct digital synthesizer
• a DDS receives an input clock signal and a control word. Based on the control word and possibly also on subsequent timing (Read, Write, Update control, etc.), the DDS outputs a waveform (e.g., a sine wave) having a known frequency and/or phase with respect to the input clock signal.
• a DDS generally includes a phase accumulator to indicate a phase state of the current output sample and a lookup table to indicate an amplitude corresponding to that phase state.
• the control word may be loaded into a register of the DDS such as, for example, an accumulator.
• the DDS determines the desired frequency and/or phase of the output signal based on the lookup table information associated with the received input control word.
• DDS devices available from integrated circuit suppliers include the AD98XX series products available from Analog Devices, Inc. of Norwood, Massachusetts. Other DDS suppliers include Harris Corporation of Melbourne, Florida; Intersil Corporation of Melbourne, Florida; and Intel Corporation of Santa Clara, California.
• a standard DDS may include a phase accumulator, a phase-to- amplitude converter, and a Digital to Analog Converter (DAC).
• the DDS core described above without the DAC may also be referred to as a Numerically Controlled Oscillator (NCO).
• NCO Numerically Controlled Oscillator
• the phase accumulator, phase-to- amplitude converter, and DAC are the standard building blocks for the DDS, although the implementation of each varies from design to design.
• phase-to- amplitude converter receives the phase at a given sample and outputs a corresponding amplitude.
• the table truncates the X least significant bits (where X may change from design-to-design and part-to-part), using only the Y most significant bits.
• the implementation of the table may change. For example, the amplitude may be repeated in 90 degree increments and only the sign of the amplitude may change according to the quadrant. Therefore many look-up tables use only 90 degrees in the look-up table along with a sign bit(s) to specify what quadrant the phase is in.
• a DDS may be configured as a frequency divider.
• the control word may specify a desired frequency and/or phase of the output signal (where the frequency is processed through the DDS core and any phase offset is summed in) as the ratio of the desired output signal to the input clock signal (where the output frequency is based on the accumulator value and the clock rate).
• DDS based solutions may provide a significant reduction in phase noise as compared to analog based solutions.
• analog solutions may use an error correction loop to determine the phase/frequency of the output.
• the transfer function that determines the extent (e.g., bandwidth) of correction is inversely proportional to the time required to correct, thereby sacrificing speed for phase noise or vice versa.
• DDS based solutions can provide fine tuning resolution of the output frequency (e.g., micro-hertz tuning resolution) as well as sub-degree phase tuning.
• DDS based solutions may provide such advantages as an extremely fast speed in tuning to the output frequency or phase, phase-continuous frequency switching with no over/undershoot, and little or no settling time as may occur for analog based (e.g. loop) solutions. DDS based solutions may also reduce or eliminate the need for manual system tuning and tweaking due to component aging and temperature drift, for example, that are often issues for analog based solutions.
• DDS based solutions may require relatively high input clock speeds and may produce spurious frequency responses in which unwanted components are present in the output frequency spectrum.
• phase truncation error may occur, for example, when the number of entries in the DDS output lookup table is less than the maximum number of possible amplitudes capable of being specified by the digital control word based on, for example, the length of the accumulator register in the DDS which receives the control word for decoding.
• a DDS with a 32-bit phase accumulator is capable of distinctly specifying 2 distinct phases.
• the lookup table may include less than the maximum number of possible amplitudes, and the DDS may resolve or correlate the phase accumulator value resulting from an input control word to that phase which is closest to the exact value specified by the state of the phase accumulator.
• the amplitude of the truncation error spurs may vary periodically over time based on the overflow characteristic of the phase accumulator (also known as the Grand Repetition Rate).
• the change in truncation error amplitude with respect to time may define a periodic waveform having a frequency spectrum of sufficiently high range that higher order harmonics of the truncation error waveform produce aliasing into the Nyquist bandwidth.
• Spurious responses may appear at frequencies relatively close to the output frequency of a DDS. This aspect can be particularly troublesome to system designers.
• the DDS input clock can be set to a single frequency or a very narrow tuning band, for example, to avoid these "close in” responses.
• restricting the range of the input clock also limits the output signal tuning range of the DDS.
• Errors in the digital-to-analog conversion (DAC) process are typically a significant source of spurious responses. Such errors may include quantization error as well as DAC nonlinearities. DAC-introduced error, which may be related to the clock and the output frequencies, is typically highly predictable.
• Embodiments of the present invention include systems and methods for utilizing DDS based signal generator solutions for wideband applications. Such embodiments may also provide systems and methods for reducing or avoiding spurious DDS responses by varying the clock signal input to the DDS.
• At least one embodiment of a signal generator according to the present invention includes a clock generator that has a first direct digital synthesizer (DDS) configured to produce a synthesized signal based on a clock source signal.
• the signal generator further includes a clock divider that has a second DDS configured to produce a divided signal based on (1) the synthesized signal and (2) a control signal indicating a frequency ratio.
• These embodiments may further include selectable filters configured to produce a filtered signal based on the divided signal. The selection among the selectable filters may be based on the control signal, a selected output frequency (e.g.
• the number of selectable filters is four.
• the signal generator may further comprise a frequency translator configured to produce a translated signal based on the filtered signal.
• the translator may be, in some embodiments, a mixer receiving a local oscillator (LO) signal, a frequency doubler, or a multiplier including, for example, a step recovery diode (SRD). Use of a multiplier may result in spurious components also being translated, however.
• LO local oscillator
• SRD step recovery diode
• the clock divider may be configured to produce a divided signal having a principal frequency that is 2.5 times lower than a principal frequency of the synthesized signal with subsequent filtering.
• the clock divider may include a third DDS configured to produce a second divided signal based on (1) the synthesized clock signal and (2) a second control signal indicating a second frequency ratio.
• the selection of one of multiple selectable filters may be provided based on the second control signal. In at least one embodiment, the number of selectable filters is four.
• the second DDS may include a table of output values and the divided signal may be determined based on the table of output values in response to (1) the synthesized clock signal and (2) a control signal indicating a frequency ratio and forgoing the phase to amplitude conversion.
• the second DDS may output changes to the divided signal at a frequency substantially equal to the frequency of the synthesized clock signal without the full phase to amplitude conversion. Because the output divided signal may be an integer or integer +/- a subset (such as, for example, 0.5) of the phase value, the size of the lookup table can be reduced.
• the second DDS (or third DDS) may be preloaded to output the divided signal at a predefined frequency in response to receiving the synthesized clock signal.
• a method of generating a signal according to another embodiment of the invention includes using a first DDS to generate a clock signal and using a second DDS to generate a signal based on the clock signal and having a frequency that is substantially equal to one-half of the clock signal. Such a method may also include providing a phase offset value to the second DDS.
• a method of generating a signal according to another embodiment of the invention includes providing a first signal to a clock input of a DDS and using the DDS to generate an output signal based on the first signal and having a frequency that is substantially equal to one-half of the clock signal. Such a method may also include providing a phase offset value to the DDS.
• a method of generating a signal according to another embodiment of the invention includes using a DDS to generate an output signal having a desired frequency component and a spurious frequency component, monitoring a strength of the spurious frequency component, and changing a phase offset value of the DDS based on a result of said monitoring.
• Further embodiments of the invention include transmitters, receivers, transceivers, test equipment, satellite communications systems, and radar systems that include signal generators as described herein (e.g. employed as local oscillators) and methods of using such devices.
• FIGURE 1 is a block diagram of a frequency synthesizer 100 according to at least one embodiment
• FIGURE 2 is a detailed block diagram describing the clock generator in at least one embodiment
• FIGURE 3 is a detailed block diagram describing the clock divider in at least one embodiment
• FIGURE 3 a is a detailed block diagram of another embodiment of the clock divider and a frequency multiplier
• FIGURE 4 is a detailed block diagram of an embodiment of the first synthesizer stage
• FIGURE 5 is a detailed block diagram of an embodiment of the second synthesizer stage
• FIGURE 6 illustrates an embodiment of a synthesizer including a clock generator coupled to more than one divider;
• FIGURE 7A is a block diagram of another embodiment of a synthesizer
• FIGURE 7B is a block diagram of another embodiment of a synthesizer
• FIGURE 8a is a block diagram of an embodiment of a programmable divider chip
• FIGURE 8b is another block diagram of an embodiment of a programmable divider chip
• FIGURE 9 is a block diagram of a fast tuning, high spectral purity tuner/receiver according to an embodiment
• FIGURE 10 is a block diagram of a DDS chip/chipsets according to an embodiment
• FIGURE 11 is an illustrative information flow diagram for a test and measurement signal generator/spectrum analyzer front end according to an embodiment
• FIGURE 12 is a block diagram of a secure transceiver having a modulation scheme provided in accordance with an embodiment
• FIGURE 13 is a block diagram of a satellite communication system in accordance with an embodiment
• FIGURE 14 is a series of scatter plot diagrams showing examples of the effects of improved phase noise in an embodiment
• FIGURE 15 is an overall block diagram of a radar system according to an embodiment
• FIGURE 16 is a block diagram of at least one embodiment of divider having a variable frequency input source
• FIGURE 17 is a flow diagram of a method according to at least one embodiment
• FIGURE 18 shows a theoretical plot of the output signal produced by at least one embodiment having a divide ratio of 2.990;
• FIGURE 19 shows a theoretical plot of the output signal produced by at least one embodiment having a divide ratio of 2.999;
• FIGURE 20 shows a theoretical plot of the output signal produced by at least one embodiment having a divide ratio of 3.000;
• FIGURE 21 shows a theoretical plot of the output signal produced by at least one embodiment having a divide ratio of 2.5000;
• FIGURE 22 shows a theoretical plot of the output signal produced by at least one embodiment having a divide ratio of 3.1000;
• FIGURE 23 shows a theoretical plot of the output signal produced by at least one embodiment having a divide ratio of 6.1991;
• FIGURE 24 shows a block diagram of a signal generator 10 according to an embodiment of the invention.
• FIGURE 25 shows a block diagram of a DDS having a divide ratio of 2;
• FIGURE 26 shows a block diagram of a DDS having a divide ratio of 2.5;
• FIGURE 27 shows a flowchart of a method according to an embodiment of the invention.
• FIGURE 28 shows a flowchart of a method according to an embodiment of the invention.
• Embodiments of the present invention may include a synthesizer architecture suitable for signal generation, for example, in wideband applications.
• the DDS synthesizer includes a clock generator configured to provide a tunable or varying clock input to one or more other DDSs. Operation of such a device may include selecting the output frequency of the clock generator (which may also include a DDS) to reduce or prevent spurious components in the output of a subsequent DDS or DDSs. Such embodiments may be applied, for example, to produce signals over a wide frequency range.
• FIGURE 24 shows a block diagram of a signal generator 10 according to an embodiment of the invention.
• Clock generator 101 which may include one or more DDSs, generates a synthesized clock signal based on a clock source signal (not shown).
• Divider 105 which may also include one or more DDSs, receives the synthesized clock signal (or a signal based on it) and generates a divided signal based on the synthesized clock signal and a ratio.
• a bank 167 of selectable filters receives the divided signal (or a signal based on it) and a selected one of the filters is applied to filter the signal to produce an output. The selection among the selectable filters is based on the ratio.
• signal generator 10 may include components such as filters, frequency translators, switches, and/or summers in the signal paths between clock generator 101 and divider 105, between divider 105 and selectable filters 167, and/or downstream of one or more of selectable filters 167.
• FIGURE 1 shows a functional block diagram of an synthesizer 100 that includes two implementations 20a,b of signal generator 10.
• Synthesizer 100 may be configured as a wideband local oscillator signal generator, for example, to include a first agile clock generator 101 configured to provide a first clock signal.
• clock generator 101 receives a first clock source signal (and possibly other signals) from a clock distribution unit 110.
• clock distribution unit 110 may generate or receive a 300 MHz clock signal input and output a 300 MHz clock signal based on that signal to the clock generator 101.
• clock generator 101 may include an oscillator configured to generate the first clock signal or a precursor of such signal.
• Such an oscillator may be a crystal oscillator (e.g. a temperature-controlled crystal oscillator or TCXO) or other suitable device.
• the clock generator 101 produces a DDS clock signal input to a clock divider 102.
• Clock generator 101 may include a step recovery diode (SRD) and associated circuitry for clock generation (e.g. by multiplying a clock signal having a lower frequency).
• Clock divider 102 may be configured to output a divided signal based on the DDS clock signal input and the state of a control word.
• SRD step recovery diode
• FIGURES 2 and 3 provide additional details concerning possible implementations of clock generator 101 and clock divider 102, respectively.
• clock generator 101 may include a DDS 151 coupled to a variable bandpass (and/or switched bandpass) filter 153, the output of which may be provided to a frequency translator 155.
• the variable bandpass filter 153 may remove artifacts due to the clock signal as well as other artifacts such as alias and spurious responses.
• Frequency translator includes devices such as frequency multipliers (e.g. circuits including SRDs) and mixers.
• Frequency translator 155 may be implemented as a mixer to receive a first local oscillator signal and produce an upconverted output DDS clock signal.
• the first local oscillator signal is derived from the same base as the clock signal provided by the clock distribution unit 110 to the DDS 151 and may even be the same signal.
• the output DDS clock signal may be implemented as a sine wave that is continuously tunable across a range (for example, to any frequency across the output band of the DDS 151).
• clock divider 102 may include a DDS 161 that receives the output DDS clock signal from clock generator 101.
• the DDS 161 may produce a divided signal which is provided to a variable bandpass (or switched bandpass, or singular) filter 163 coupled to an output of DDS 161.
• the variable bandpass filter 163 may remove artifacts due to the clock signal as well as other artifacts such as alias and spurious responses.
• the divided signal output by the DDS 161 may be, for example, a sine wave that is tunable over a broad frequency range.
• the filtered divided signal may then be provided to a frequency translator 165 configured to produce a translated divided signal (e.g. by mixing the filtered divided signal with a second local oscillator signal).
• the translated (e.g. upconverted) divided signal may be filtered using one of multiple selectable bandpass filters 167 to produce a filtered upconverted divided signal.
• the DDS 161 selects the particular bandpass filter 167 based on the state of the control word.
• the divided signal output by the clock divider 102 has a frequency at least two times but less than three times lower than the DDS clock signal received from the clock generator 101. In at least one embodiment, the divided signal has a frequency that is 2.5 times lower than the DDS clock signal. In such embodiments, it may be sufficient to provide filtering of the output only to suppress the images appearing at 0.5 and 1.5 times the output frequency. Thus, the only dividing restriction nearing an integer value of 2 is the restriction imposed by the sampling nature of the digital architecture, which may cause images to be aliased back into the bandwidth of interest.
• each of the filters of the set of filters 157 and 167 may be constructed using discrete components, which may be separate components for each filter.
• Use of selectable input frequencies to the agile clock generator 101 may be further advantageous in increasing the spurs- free bandwidth of the output of the clock generator 101.
• Each of the filters comprising the set of filters 157 and 167, as well as any other set of selectable bandpass filters herein, may have a different bandpass frequency range as well as a smaller or larger relative bandpass range (i.e., the size of the filter's range calculated as the difference between the high frequency cutoff and the low frequency cutoff for the filter) compared to other filters in the set.
• a smaller or larger relative bandpass range i.e., the size of the filter's range calculated as the difference between the high frequency cutoff and the low frequency cutoff for the filter
• adjacent passbands may overlap or be nonoverlapping.
• One possible arrangements for the passbands of the filters in a set is as a series of octaves.
• filter set 157 may have four filters and be implemented to pass the band 50-200 MHz. If the individual filters were implemented to have passbands of equal width, then the respective passbands might be centered at 50, 100, 150, and 200 MHz, each filter passing a band +/- 25 MHz from the center frequency. Such a distribution would not be suitable for removing images at 0.5x and 1.5x from an output frequency of 50 MHz, however, as the 25 MHz and 75 MHz images would lie within (or at least at the edge of) the passband of the 50-MHz filter. Therefore, another distribution of the center frequencies and/or passbands of the filters might be more desirable.
• the same center frequencies may be used, with the filters having progressively wider passbands as the center frequency increases.
• the filters may have center frequencies that are non- uniformly distributed.
• an octave or semi-octave distribution e.g. 50-70-100-140 may be used instead, with each filter having a passband slightly more narrow than the center frequency.
• the DDSs 151 and 161 may receive one or more control words which cause the DDSs to produce output signals having particular frequencies and phases.
• the control words may include digital phase and frequency information.
• the control words may be stored by the DDSs 151 and 161 in, e.g., an accumulator or other such register for decoding and processing.
• an accumulator of a DDS used in the embodiment may add the digital information contained in the received control words to the binary value already in the accumulator (e.g. using modulo-2 addition) to form a new frequency/phase index value.
• the DDS may then use the newly formed frequency/phase index value to determine from a phase lookup table the frequency and phase of the signal to output from the DDS.
• one or both DDSs is phase continuous. That is, the DDS accumulates from the current value in the phase accumulator when a new accumulator value is written to the accumulator. When a new frequency value (phase accumulator value) is written, it accumulates or adds to the last value in the accumulator unless the DDS is purposely reset to a phase accumulator value of zero.
• the clock divider 102 may be preloaded to output the divided signal at a predefined frequency in response to receiving the DDS clock signal input.
• Table 1 provides a particular example of frequency planning, including control information that may be used to control particular implementations of DDSs 151 ("DDS1") and 161 ("DDS2") to perform signal synthesis operations as described herein.
• control logic is used to control the functioning of the DDSs 151 and 161 to produce particular divided signals according to Table 1. For example, one or more such control words may be loaded into a control register of a DDS.
• This logic may be implemented using, for example, a gate-based logic design embodied in a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), a series of discrete components, and/or processor-executable instructions stored in a memory (which may be a Read-Only Memory (ROM), Programmable ROM (PROM), Erasable PROM (EPROM), nonvolatile random-access memory (NNRAM), flash memory, or any variation thereof).
• ROM Read-Only Memory
• PROM Erasable PROM
• NRAM nonvolatile random-access memory
• the output of DDS 1 151 is upconverted by 300 MHz before input to DDS2 161.
• the DDS2 161 applies a selected divide ratio, and its output signal may be doubled to obtain the desired output signal.
• control logic may be implemented to select the appropriate output frequency for DDS1 151:
• the clock divider 102 includes a look-up table of amplitude values that may be used to directly specify the divided signal output (e.g. without converting phase values). In response to the control word, for example, the outputted value may be determined based on the table of amplitude values. In at least one embodiment, the clock divider 102 outputs new values of the divided signal at a frequency substantially equal to the frequency of the DDS clock signal without the full phase-to-amplitude conversion.
• the lookup table of DDS 151 for the clock generator 101 may also contain entries previously determined to reduce or prevent the generation of spurious components in the frequency spectrum of the DDS clock signal produced by the clock generator 101.
• spurious content is reduced by tuning the Divider DDS to integer or integer +/- 0.X values, where X is a digit.
• X may be equal to 5.
• other values for X are possible (e.g. 1).
• X may be a real number. This selection may have the effect of causing the spurious responses (e.g. images as generated by DAC errors such as quantization and non-linearity) to be masked under the fundamental frequency (output frequency). For exact integer divide values, all spurious content due to DAC error may fall under the fundamental frequency.
• FIGURE 3a shows a further embodiment of clock divider 102 and frequency translator stage 120.
• the clock divider 102 may include a DDS 161 that receives the clock signal output by the clock generator 101.
• the DDS 161 may produce a divided signal which is filtered using one of multiple selectable bandpass filters 167 to produce a filtered divided signal.
• the DDS 161 may select the particular bandpass filter 167 based on the state of the control word.
• the divided signal output by the DDS 161 may be a sine wave tunable over a broad frequency range.
• Frequency translator 121 may be implemented as a multiplier, for example, using a comb generator including a snap or step recovery diode.
• frequency translator 121 may include a mixer configured as a frequency doubler (or "dedicated multiplier"), with the input signal being coupled to both of the RF and LO inputs of the mixer.
• the translated divided signal may be filtered using one of multiple selectable bandpass filters 123 to produce a filtered translated divided signal.
• the number of selectable bandpass filters may be four.
• the DDS 161 may select the particular bandpass filter 123 based on the state of the control word.
• the filtered translated divided signal may then be provided through a driver 125 (e.g. a buffer, amplifier, or impedance-matching network) to one or more frequency translators to produce other frequencies of interest.
• FIGURE 4 shows a detailed functional block diagram of an embodiment of frequency translator stage 130.
• the frequency translator stage 130 that outputs a first portion of the first local oscillator signal may include a frequency translator 131 (which may be coupled to the frequency translator stage 120), the output of which is coupled through switches 132 and 135 to one or more selectable bandpass filters 133 and 134.
• the frequency translator stage 130 selects the bandpass filter 133 or 134 based on the frequency of the received filtered translated divided signal.
• the number of selectable bandpass filters in this stage is two, although more or fewer filters may be used as appropriate.
• the bandpass filters 133 and 134 are selected based on the desired output frequency of the stage or an intermediate frequency needed to perform a conversion to the desired output frequency. For example, in a particular implementation as shown in FIGURE 4, either the 1100- 1300MHz bandpass filter 133 or the 1300- 1500MHz bandpass filter 134 is selected based on the desired output frequency for the first frequency translator stage 130, which ranges from 1100 MHz to 1500 MHz. As shown in FIGURE 4, an intermediate frequency (IF) input of 100-300MHz from the preceding stage 120 may be mixed with either 1000MHz or 1200MHz to produce the above stated output.
• IF intermediate frequency
• control logic may be used to select the filter 133 or 134 based on the desired output frequency.
• the control logic may be implemented using, for example, but not limited to, an FPGA, ASIC, ROM device, or software, as described above.
• the control logic may first determine the output frequency to be provided, and then determine the local oscillator frequency needed to upconvert to the final output. In an embodiment, if the desired output frequency is between 1100-1300MHz, then the 1000MHz local oscillator signal is selected and mixed with 100-300MHz using the frequency translator 131 to yield 1100-1300MHz, as shown in FIGURE 4.
• FIGURE 5 shows a detailed functional block diagram of an embodiment of frequency translator stage 140.
• frequency translator stage 140 may include a pair of switches 144 and 145 which, in a first position, configures the frequency translator stage 140 to provide the received signal to a frequency translator 141 (e.g. a mixer) which may be coupled to one of multiple selectable bandpass filters 142 to produce a filtered signal.
• a frequency translator 141 e.g. a mixer
• the frequency translator stage 140 may select the particular bandpass filter 142 based on the final output frequency required at the output of the frequency translator stage 140.
• the switches 144 and 145 configure the frequency translator stage 140 to output the signal received by the stage.
• the second stage signal through switch 145 is provided through the driver 146 as the first local oscillator final output signal.
• the first local oscillator signal output by this stage has a frequency of between 1100 MHz and 2100 MHz.
• the switch settings for filtering and upconversion selection or bypass are selected by control logic based on a stage output frequency, the desired final output frequency of the first local oscillator LO1 (e.g., 1100-2100MHz), or an intermediate frequency used for upconversion to produce one of these.
• a filter may be selected that has a passband within the range of the output frequency and that attenuates the unwanted terms, such as the local oscillator input in the upconversion case. If the stage 140 is not configured for upconversion (e.g., the output frequency is between 1100- 1500MHz), then the translator 141 is bypassed and the output frequency from the previous stage (e.g., frequency translator stage 130 in FIGURE 4) is used.
• the synthesizer 100 may further include a second signal generator (i.e. a second clock generator 103 coupled to a second divider 104) configured to produce a second local oscillator signal.
• the clock signal received from the clock distribution unit 110 by the second clock generator 103 may have the same frequency as the clock signal received by the first clock generator 101; alternatively, clock distribution unit 110 may provide a signal having a different frequency to generator 103.
• the structure and operation of the second clock generator 103 and the second divider 104 may be substantially the same as described above for the first clock generator 101 and the first divider 102 in FIGURES l-3a.
• the second local oscillator signal may have, for example, a frequency between 48 MHz and 94 MHz.
• the output of the second divider 104 may be coupled to an upconverter and/or one or more synthesizer stages as described above.
• the synthesizer 100 may provide a third local oscillator signal.
• the third local oscillator signal may have, for example, a frequency of one of 300 MHz, 500 MHz or 1100 MHz.
• the clock distribution unit 110 may include one or more step recovery diodes (SRDs) configured to generate the third local oscillator signal.
• SRDs step recovery diodes
• a varying tunable clock source may be constructed using other than DDS methods and devices to provide the clock for the second or subsequent DDS(s).
• An example of such a varying, tunable clock source is a phase-locked loop. While a phase-locked loop may be slower to tune, such a device may provide lower power consumption (down to milliwatts) and/or a smaller size (due e.g. to reduced filtering requirements) in comparison to a DDS.
• the variable-frequency clock signal is received by the clock divider(s), which may be as described earlier with respect to FIGURES l-3a.
• a synthesizer 200 may include a clock generator 201 coupled to more than one divider (for example, dividers 202- 204 as shown in FIGURE 6).
• one or more of dividers 202-204 are implemented using DDSs. Multiple clock dividers may be used, for example, to reduce or eliminate the time it takes to load a new division ratio or control word into a DDS divider.
• one or more of the clock dividers 202-204 are preconfigured (i.e. before being selected into the signal path) with a particular division ratio, control word, and/or output frequency/phase in order to achieve even faster switching time. In an exemplary application, such an architecture may be used to "ping-pong" between or "hop” among different frequencies very rapidly.
• one or more of clock dividers 202-204 may include multiple registers for preloading of different pre-defined divider values, with the divider capable of selecting one of the preloaded divider values in response to a signal provided by control logic external to the divider at a rate faster than the time required to load each divider individually.
• the control signal may be provided upon or prior to the divider being selected into the signal path.
• each of the multiple dividers 202-204 may be preconfigured or preloaded with a single respective divider value, and then each divider may be individually selected (e.g. by switch 205) at a rate faster than the time required to load each divider individually, in order to achieve a very fast tuning speed.
• the dividers 202-204 may have a parallel loading control word register (as opposed to a register that is loaded serially).
• FIGURE 6 shows three dividers 202-204, any number of dividers or divider DDSs may be used in various embodiments.
• the architecture may also be implemented to include a switch between the clock generator 201 and the dividers 202-204.
• a divider chip may have multiple (e.g. four or eight) different pin-selectable profiles, each including its own control word or divide ratio, such that fast frequency switching may be achieved during operation, as described above with respect to FIGURE 6.
• such a divider chip may provide phase-continuous switching between two different frequencies.
• FIGURE 6 may be implemented using a summer in place of (or in addition to) switch 205, such that outputs from multiple dividers (e.g. 202-204) may be combined to provide a modulated output signal or a desired waveform shape.
• multiple dividers e.g. 202-204
• At least one of the dividers 202-204 may be a non-DDS based frequency divider.
• a frequency divider may be constructed as or including a logic chip (e.g. TTL, ECL) or using discrete components, or may otherwise include an integrated circuit capable of outputting a divided frequency.
• a divider may produce a divided signal according to one of several different divide ratios in response to a selection signal.
• Such embodiments may offer a reduced set of available divide ratios, such that the clock generator 201 may be required in certain applications to have a frequency range that is greater than embodiments in which at least one of the dividers 202-204 is implemented using a DDS.
• a synthesizer 700 may include a clock generator 701 coupled to a first divider stage 710, the output of which is in turn coupled to a second divider stage 703.
• the clock generator 701 may comprise a first DDS, which may be coupled to a second DDS implementing first divider stage 710, which may be coupled to a third DDS implementing second divider stage 703.
• the third DDS or second stage divider may, for example, substantially replicate the second DDS or divider in the embodiments described above.
• Advantages of using a third DDS serially coupled to the output of the second DDS may include finer tuning resolution (e.g., micro-hertz resolution) and/or further spurious component suppression.
• a first DDS e.g., agile clock or clock generator DDS
• the spurious components produced by the first DDS may be reduced by, for example, 20 log [(second DDS divide value) x (third DDS divide value)].
• the addition of a third DDS may further reduce spurious responses created by the first DDS (e.g. agile clock generator) while providing finer tuning resolution.
• a first divider stage 722 may be implemented to include more than one divider, such as the dividers 710 and 711. Such dividers may have outputs that are selectable (e.g. via switch 712) or combinable (e.g. to obtain modulated signals or other waveforms).
• the DDS 161 may include a table of amplitude values to be output directly to a DAC at the rate of the input clock.
• Such an architecture bypasses the phase- to-amplitude conversion of current DDS architectures and may thus eliminate the need for a control word input.
• the table of amplitude values may be small (i.e., implemented only for integer or integer +/- 0.5 ratios), such that the control word may be replaced by a signal to specify the integer (+/-0.5) ratio to be applied.
• such an embodiment may use ratios such as, for example, integer values +/- 0.5 and/or integer values +/- .1,.2,.3 or .4.
• Other acceptable solutions may include non-integer ratios of the divider DDS that have been found to provide wide bands free of spurious responses (e.g., as shown in FIGURE 23). This approach is flexible to respond to particular requirements such as application bandwidth, spurious-free dynamic range, size requirements, etc.
• the synthesizers described above may be implemented using an integrated circuit device as a programmable divider chip DDS for use in signal generation.
• the chip may be programmed by sending it a particular divide ratio indicative of a corresponding sine or cosine value to use for each clock cycle.
• the output may be a sine wave; however, other waveforms are possible.
• Such a programmable divider chip may be designed for particular applications, such as, for example, applications that may use dual DDS configurations, and therefore utilize a simplified or streamlined design.
• one DDS may be used to clock a second DDS operable to function with only specific divide ratios for particular spectral purity concerns.
• dual DDS synthesizers may be implemented to have the advantage of reducing spurs.
• Spurious responses is one characteristic of previous DDS architectures that has limited the widespread use of DDSs, particularly for wideband applications.
• the DDS has many close-in spurious responses.
• the clock is set at a single frequency to avoid these close-in responses, but this also limits the tuning range. Consequently, these spurious responses may prohibit the use of existing DDS architectures in wideband systems.
• the first DDS provides a tunable clock for the second DDS, which allows the input clock to the second DDS to be tuned as necessary to mitigate the inherent spurious regions of the second DDS.
• This configuration eliminates and/or significantly reduces close-in spurious responses to utilize the desired benefits of the DDS, which include excellent phase noise and fast tuning speed. Because the cleanest output spectrum is obtained at integer and half-integer ratios, a DDS chip dedicated to these division ratios may be optimized for that function.
• a further embodiment of the invention includes a programmable divider chip.
• a DDS synthesizer chip configured specifically as a divider DDS may be utilized in a variety of wideband applications where fast tuning and low phase noise characteristics are desired. These applications are not limited to but may include signal surveillance, electronic warfare, test equipment, transmitters, radar and data communications.
• Particular advantages of a divider DDS may include simpler design, faster design, smaller tuning word, lower spurious responses, higher fidelity and lower phase jitter.
• a programmable divider chip may include three sections: a divide-ratio-to-table-address mapping section 801, a lookup table (e.g. sine and/or cosine) 802, and a digital-to-analog converter (DAC) section 803.
• the divide-ratio-to-address mapping section 801, which outputs a sequence of addresses for lookup table 802 according to an indicated divide ratio, may be implemented in several different ways, with selected divide ratios (e.g. all or part of the series of 2.5, 3, 3.5, 4, 4.5, ..., 100) being supported.
• mapping section 801 may indicate the address in lookup table 802 for the sine or cosine value for every 90° (or 0°, 90°, 180° and 270°), to be output to DAC 803, at a rate of one address/angle for every clock cycle. Thus one complete cycle of the divide by four output may be produced in four clock cycles.
• mapping section 801 may indicate the address for the sine value for 0°, 144°, 288°, 432°, and 576°, to be output to DAC 803 at the same rate. In this case, two complete cycles of the divide by 2.5 output may be produced in five clock cycles. Operations for other divide ratios may be inferred from this logic.
• Such a chip may also include selectable (e.g. pin-selectable) profiles as described herein.
• Such embodiments may provide a sine or cosine wave output; however, other embodiments of this basic structure are possible.
• One example, as shown in FIGURE 8b, may include having the divide ratio to ROM lookup as one function 804.
• Another example is a lookup table based on a non-sinusoidal waveform (e.g. a triangle, sawtooth, or other waveforms).
• Table 2 lists some examples of incremental phase values that may be used to produce certain divider ratios.
• a DDS at a divide ratio of 2 (i.e. the Nyquist frequency) is not currently known.
• a DDS may exhibit a decrease in output signal strength of up to 20 dB or more at an integer ratio of 2 as compared to output signal strength at higher divide ratios.
• Some DDSs such as a DDS in the Analog Devices series 98XX, include a provision for adding a phase offset value to the phase value that is output by the phase accumulator (e.g. before digital-to-analog conversion).
• the inventors have discovered that by selecting a phase offset of 90 degrees (or 270 degrees), an output signal strength may be achieved at an integer ratio of 2 that is comparable to results at higher divide ratios (see, e.g., FIG. 25).
• Such a technique may be used to particular advantage with a DDS driven by a variable-frequency clock (e.g. a PLL or another DDS), as described herein.
• the divider DDS is configured with a divide ratio of 2 and a phase offset of 90 degrees.
• the clocking PLL or DDS may be used to provide frequency variability and/or wideband operation, while the divider DDS may be used to provide a phase-continuous and/or relatively spurious-free output at half of the clocking frequency. It may be determined that a different phase offset value provides similar advantages with other DDS models.
• Adjustment of a phase offset value of a DDS may also be used in conjunction with divide ratios of X.5, where X is an integer greater than or equal to 2 (see, e.g., FIG. 26).
• a phase offset value is selected to provide decreased spurious signal strength and/or increased output signal strength.
• DAC nonlinearity may give rise to spurious content. DAC nonlinearities are typically greater at higher frequencies.
• One reason for this effect may be that outputs at lower divide ratios are converted using fewer data points than outputs at higher divide ratios. Possibly because of this effect, operation of a DDS at a divide ratio of 2.5 is currently unknown. Filtering and other techniques that may be used to enable such operation are described herein.
• a DDS operated at a divide ratio of X.5 may be expected to have spurious outputs at 0.5 and 1.5 times the output frequency (see, e.g., FIG. 21).
• X is an integer greater than or equal to 2
• the strength of one or both of these spurs may be reduced.
• Such a method may be further applied, e.g., to simplify a filtering task.
• a filter may reduce the strength of a spur resulting from one clock frequency, but may not have a sufficient effect on the strength of a spur resulting from another clock frequency to meet a particular design specification.
• By reducing the strength of the spur as described above in at least the second case it may be possible to meet the specification by using the same filter in that case, which may avoid a need to add another filter to the system.
• a method as described herein may also be used with a DDS operated at a divide ratio other than X.5.
• phase offset value is changed or selected for a DDS to be operated at a divide ratio of X.5 (where X is an integer greater than or equal to 2)
• a suitable phase offset value i.e. a value that results in a desired or acceptable reduction of spur strength and/or a desired or acceptable increase in desired signal strength
• a suitable phase offset value may change over time.
• such a value may change based on effects of temperature, capacitance, frequency, device aging, etc. Therefore, it may be desirable to momtor a strength of one or more spurious components of the output signal of a DDS, and to change or select a phase offset value of the DDS based on a result of the monitoring (see, e.g., FIG. 27).
• Such a method may also be used with a DDS operated at a divide ratio other than X.5. Additionally, such a method may be used to increase a strength of the desired signal, either with or without reducing a strength of a spur.
• phase offset value may depend on one or more particular propagation paths (which may be internal and/or external to the DDS), and that information regarding a relation between the value and the path(s) may be obtained and applied to the use of other DDSs.
• phase offset value having advantages at another frequency (see, e.g., FIG. 28).
• Particular methods of characterization, interpolation, etc. as are known in the art may be applied in a method according to such an embodiment of the invention.
• embodiments of the present invention may be used for applications where one or more ultra-clean, fast tuning frequency sources are desired. Examples include, but are not limited to, a local oscillator in frequency conversion, complex modulation, and transmission and test & measurement applications. In general, the present invention may also be used for applications previously implementing a phase locked loop (PLL). Particular applications are described below with respect to FIGURES 9-16.
• PLL phase locked loop
• FIGURE 9 is a block diagram of a fast tuning, high spectral purity tuner/receiver 900 according to an embodiment.
• FIGURE 9 illustrates an embodiment of a tuner/receiver designed for fast tuning speed and high spectral purity (phase noise and spur free dynamic range (SFDR)).
• Applications for such an embodiment may include Signal Intelligence (SIGINT) and Electronic Intelligence (ELINT) signal collection and analysis.
• the receiver/tuner 900 may include a radio frequency (RF) antenna 901 coupled to a receive band filter 903, the output of which is fed through a low noise amplifier 905 to a first frequency translator 907 to produce a first intermediate frequency (IFi).
• RF radio frequency
• the output of frequency translator 907 is coupled through a bandpass filter 909 to a second frequency translator 911 that produces a second IF (IF 2 ).
• the output of the second frequency translator 911 may be fed through a bandpass filter 913 and an amplifier or signal conditioner 915 to a third frequency translator 917 to recover the detected digital signal.
• the output of frequency translator 917 may be coupled through a first low pass filter 919, an amplifier/signal conditioner 921, and a second low pass filter 923 to a DAC 925 to reconstruct the analog signal corresponding to the detected digital signal.
• the tuning speed and spectral purity of a receiver may be determined by its synthesizer (LO1, LO2, and LO3 inputs to frequency translators 907, 909 and 917, respectively, in the particular implementation shown in FIGURE 9).
• the phase noise, SFDR and tuning speed of embodiments of the present invention are well-suited for such applications.
• any one or all of LO1, LO2 and LO3 may be implemented using embodiments of a signal generator or synthesizer as described herein (e.g. including one or more implementations of signal generator 10).
• one or both of LO2 and LO3 may be implemented using other solutions such as PLL-based or SRD-based signal generators.
• FIGURE 10 is a block diagram of a DDS chip/chipsets according to an embodiment (e.g., "DDS on a chip").
• New mixed-signal foundry processes may be used to lend this architecture to a chip or chipset solution with a limited number of external components.
• the bandwidths of the chip or chipset may provide for simplicity of the DDS chips with vastly improved wideband SFDR (for example, 85-90dBc).
• the bandwidth of the architecture according to embodiments of the present invention will continue to increase with the speed of digital and DAC architecture.
• the modified sine look-up table and phase accumulator ROM would accommodate phase accumulator and look-up values for optimally tuned spots for DDS#2 described elsewhere in this document.
• those optimal spots are integer divide ratios and integer +/- 0.5 divide ratios. Using only these values corresponding to these "optimal spots" reduces the size of the phase accumulator ROM and the sine lookup table (ROM).
• filter and frequency translator components may, in some embodiments, be provided external to the DDS integrated circuit.
• FIGURE 11 is an illustrative information flow diagram for a test and measurement signal generator/spectrum analyzer front end according to an embodiment.
• the test and measurement signal generator front end may include, for example, a reference signal generator 1105 and a wideband signal generator 12 in communication with the reference signal generator 1105.
• the wideband signal generator 12 may be implemented to include one or more implementations of signal generator 10 as described herein.
• the architecture would also be beneficial in the RF front ends of devices such as spectrum analyzers, improving the overall performance of the equipment.
• FIGURE 12 is a block diagram of a secure transceiver 1200 having a modulation scheme provided in accordance with an embodiment.
• the modulation capabilities of embodiments of the present invention may be useful in such a transmitter/receiver (transceiver).
• the low phase noise and spectral purity provided by embodiments of the invention may enable implementation of high order complex modulation types and frequency hopping, which are prerequisites for some forms of secure transmission.
• the transmitter may be used for standard communication or for specific applications such as radar.
• the transmitter portion of the transceiver 1200 includes a coder/decoder (CODEC) for encoding secure data and a signal generator 14a, including one or more implementations of signal generator 10 as described herein, for modulating the encoded data for RF transmission.
• CDEC coder/decoder
• the receiver portion of the transceiver 1200 may include substantially the components described herein with respect to FIGURE 9, including use of signal generators 14b-d (each including one or more implementations of signal generator 10 as described herein) for local oscillator sources.
• FIGURE 13 is a block diagram of a satellite communication system in accordance with an embodiment. Satellite communication typically requires at least three basic components: two earth links and a satellite link used as a transponder. Each of these components may include transmitters/receivers or frequency translators (e.g. mixers) in conjunction with which embodiments of the present invention may be utilized (e.g. as local oscillator signal generators).
• SAW surface acoustic wave
• Other filters e.g., filters 903, 909, 919 and 923
• oscillators 14c and/or 14d may be, in some embodiments, implemented using other solutions such as PLL-based or SRD-based signal generators.
• FIGURE 13 is a block diagram of a satellite communication system in accordance with an embodiment. Satellite communication typically requires at least three basic components: two earth links and a satellite link used as a transponder. Each of these components may include transmitters/receivers or frequency translators (e.g. mixers) in conjunction with which embodiments of the present
• FIGURE 14 is a series of scatter plot diagrams showing examples of the effects of improved phase noise in an embodiment. Poor phase noise may result in the loss of data, increased BER (bit error rate) which results in distorted demodulation of data, or inability to demodulate in receivers. Note in this example that for 16-QAM the constellation points are well within the decision regions, whereas the 64-QAM example shows that decision errors (area within each grid) could be caused by only small noise excursions causing errors in data. The exceptional phase noise characteristics of embodiments of the present invention would allow for much higher order signals to be demodulated with a huge reduction in bit-errors.
• embodiments of the present invention may be applied, for example, to increase the data transmitted in a given bandwidth, thus allowing for expansion of the capabilities of cellular telephony/data base stations rather than adding new cell-sites.
• a transceiver embodiments may be applied to implement complex, high-order modulation/demodulation at levels unachievable by current PLL systems.
• increased tuning speed would also allow hopping frequencies to be intercepted and traced when used in a receiver.
• transceivers including embodiments of the invention could be implemented to tune faster than any present-day receiver (PLL) could detect.
• PLL present-day receiver
• embodiments may be used in transmit/receive (transceiver) systems that would enable secure transmission.
• FIGURE 15 is an overall functional block diagram of a single-frequency radar system according to an embodiment.
• a radar system may include power dividers (e.g., PD1-PD6), amplifiers, delay lines (e.g., DLl and DL2), and I/Q demodulators (IQD1-2) to produce cross- polarization and circular-polarization components as indicated in FIGURE 15.
• power dividers e.g., PD1-PD6
• amplifiers e.g., DLl and DL2
• I/Q demodulators IQD1-2
• the spectral purity and repeatable behavior of signal generators as described herein may allow the radar signatures to be defined with greater resolution and accuracy.
• embodiments including implementations of signal generator 10 as described herein may be used to provide the OSC1 and/or OSC2 elements shown in FIGURE 15 in order to implement a single-frequency or multiple-frequency radar system.
• the delay line elements DLl and DL2 may be implemented as variable and selectable based on the current frequency.
• Embodiments of the invention may also allow for a smaller, lighter packaged product in most applications and/or may exhibit repeatable behavior not available from PLL circuits. Embodiments may become even smaller as the speed of digital technology and DACs increases, reducing the need for peripheral hardware.
• embodiments of the present invention may be implemented any number of ways, including any variable frequency source in place of DDS #1 or by implementing the modified architecture as described with respect to the DDS Chip/Chip Sets embodiments. Characteristics of the embodiment shown in FIGURE 16 will now be described.
• DDS#1 may serve as a variable clock source for DDS#2.
• This clock source in this example, may be created by mixing DDS#1 with 300MHz and filtering to achieve 300MHz +/- DDS#1, depending on the frequency requirements. It should be noted that the frequencies and components are used only for reference examples and clarity in this document; other variations are possible.
• the narrowband spurious (i.e., unfilterable) performance is established by the spurious performance of DDS#1 and the divide ratio (tuning word) of DDS#2.
• the reduction of spurs on the output created by DDS#1 can be formulated as follows:
• DDS#1 may have a worst case spurious of - 75dBc; the frequency tuning word (FTW) of DDS#2 may be l total resolution or the divide ratio is 4.
• FSW frequency tuning word
• DAC resolution bits
• spurious reduction techniques such as dithering
• Dithering can be used to reduce the amplitudes of individual spurious responses, although dithering may also degrade the overall SFDR (noise floor), since dithering spreads the noise/spur in the frequency domain.
• the output of the translated (mixed) DDS#1 frequency may then be supplied as the system clock for DDS#2.
• DDS#2 may be tuned to an optimum (spurious free) spot.
• the output is changed by then varying DDS#1 (SYSCLK for DDS#2).
• phase truncation spurs worst case are as follows. For example, if the number of phase bits (after truncation) is 19, then the phase truncation error may be approximated as 19 bits * 6.02 ⁇ 114 dBc. This worst-case condition (-114dBc) only takes place in a single bit pattern for the truncated bits. The pattern is a 1 for the MSB and all zeroes in the remaining bits. As demonstrated by a worst case of -114 dBc, the phase truncation is not a major contribution to the spurious performance and is not considered.
• a second source of spurious responses is DAC error, including quantization error and DAC non-linearity. These spurs, which are created at harmonics of the fundamental frequency, may be aliased into the signal bandwidth, and are predictable and reproducible.
• FIGURE 17 illustrates a wideband signal generation method 1700 in accordance with at least one embodiment.
• the method 1700 may be implemented in an embodiment, for example, as logic in a Field Programmable Gate Array (FPGA). However, other variations are possible.
• the method 1700 may alternatively be implemented using a sequence of programmed instructions or software executed by a processor, microprocessor, microcontroller, or personal computer, or using discrete logic components.
• FPGA Field Programmable Gate Array
• a wideband signal generation method may commence at block 1705. Control may then proceed to task 1710, which receives a request for an output signal (e.g. from a user or from a hardware or software component of an application). The request may indicate at least a specified signal frequency. Control may then proceed to task 1715, which determines a divide ratio for a divider based on the requested output signal frequency and a clock source frequency. Control may then proceed to tasks 1720, 1725 and 1730, which generate at least one control signal (e.g. one or more control words) corresponding to the divide ratio determined at task 1715 and select a bandpass filter from a set of filters based on the divide ratio.
• a control signal may include a specification of a frequency, phase offset, and/or amplitude scaling.
• Control may then proceed to task 1725, which provides the control signal(s) to their corresponding dividers.
• this task may be accomplished by loading (e.g., latching) control words into corresponding registers in the divider.
• the divider is a DDS in accordance with the synthesizers and signal generators described herein.
• Task 1725 may also include selecting appropriate filters (e.g. among filters 167) and/or switch positions based on the requested frequency and/or a related value that may be selected in accordance with the requested frequency (e.g. the frequency ratio, the clock source frequency, a frequency of a signal to be filtered or passed).
• Control may then proceed to task 1735, which commands the at least one divider to begin operating according to the control signal(s). Control may then proceed to task 1740, which changes the frequency of the synthesizer in accordance with the new control signal(s). Control may then proceed to block 1745, at which the method may end.
• the method 1700 may be repeated as necessary and as often as required to support the application for the wideband synthesizer.
• FIGURES 18-23 illustrate principal frequencies of simulated outputs of embodiments of signal generator 20, including spurious components due mainly to DAC error (which may include quantization error and/or DAC non-linearities).
• the plots also illustrate aliasing and to show the optimum frequencies to tune the DDS.
• the best tuning spot to nullify DAC spurious responses may correspond to DDS tuning words that create integer divide values.
• FIGURE 18 shows a theoretical plot of the output signal produced by at least one embodiment having a divide ratio of 2.990, which generates spurious terms.
• FIGURE 19 shows a theoretical plot of the output signal produced by at least one embodiment having a divide ratio of 2.999, which also generates spurious terms, but closer to the fundamental (i.e., the terms are converging on the fundamental).
• FIGURE 20 shows a theoretical plot of the output signal produced by at least one embodiment having a divide ratio of 3.000.
• FIGURE 21 shows a theoretical plot of the output signal produced by at least one embodiment having a divide ratio of 2.5000.
• FIGURE 22 shows a theoretical plot of the output signal produced by at least one embodiment having a divide ratio of 3.1000.
• FIGURE 23 shows a theoretical plot of the output signal produced by at least one embodiment having a divide ratio of 6.1991.
• This condition allows tuning and/or modulation of an upstream DDS (e.g. DDS#1) without affecting the SFDR of a later DDS (e.g. DDS#2) in its current state, which allows for a clean, spurious free output.
• the spurious components hidden by the fundamental may be of arbitrary but deterministic phase due to this synchronous, discrete system, and they do not result in noticeable amplitude variations within the Nyquist band.
• the spurious components converge onto the fundamental frequency as the divide ratio nears an integer value.
• the plot of FIGURE 20 shows the spurious free performance as the terms are located directly beneath the carrier.
• the second best case is when the tuning word creates an integer +/- 0.5 as shown in FIGURE 21.
• This case creates spurious terms at the 0.5 and 1.5 times the output frequency, significantly due to DAC error.
• the third spurious term shown in the plot below is an image of the 2 nd harmonic of the fundamental. As spur location in this case is predictable, such a ratio may be used depending on the specifications, bandwidth and filtering implemented.
• the third option is an extension of the second case. This could be accomplished by programming a tuning word that creates an integer +/- 0.1, +/-0.2, +/-0.3, or +/- 0.4. Table 3 below helps to predict the spurious locations of this case (as shown in the example of FIGURE 22).
• a further case that may be implemented using these embodiments, as shown in FIGURE 23, requires additional filtering and frequency planning. This case may be achieved by characterizing the specific DDS and DAC used, and selecting bands that are observed to be spurious-free based upon the DAC characterization as shown in FIGURE 23. This case depends heavily on performance criteria, the DAC characteristics, and filtering. While this case may produce a more narrow output band in comparison to the above architectures, it still offers an improvement over present single-DDS architectures.

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