Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
  • H01L21/6735—Closed carriers
  • H01L21/67369—Closed carriers characterised by shock absorbing elements, e.g. retainers or cushions
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
  • B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
  • B65D21/00—Nestable, stackable or joinable containers; Containers of variable capacity
  • B65D21/02—Containers specially shaped, or provided with fittings or attachments, to facilitate nesting, stacking, or joining together
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
  • H01L21/6735—Closed carriers
  • H01L21/67386—Closed carriers characterised by the construction of the closed carrier

Definitions

• the present invention relates to a containment device or wafer box for transporting semiconductor wafers, particularly utilizing thermoformed material in place of other transport wafer packaging systems utilized in shipping wafers from a front-end wafer fabrication facility to a back-end product manufacturing facility.
• the wafer box of the present invention includes a bottom floor attachment design which mechanically isolates wafers from side walls thereby acting as a shock absorber against vertical impact and vibration; a side wall configuration which isolates interior walls and the cavity from horizontal shock impact; a pedestal configuration at the corners and mid-span which provides standoff clearance when full boxes are inter-stacked, so that shock and vibration are not transmitted through the inter- stack configuration; a side wall configuration comprised of mating surfaces from the lid and bottom to create a double thickness wall thereby allowing substantially increased stacking capabilities; interlocking engagement elements on four sides to provide full engagement and survival of multiple drops of fully loaded wafer boxes (typically including 16 semiconductor wafers); interlocked offset flanges to provide for simple separation of the base from the lid; a large side wall flat surface to provide for the attachment of a large label along the side of the wafer box; and translucent material along the top of the wafer box so that large print paperwork is visible through the
• the wafer box can include a side wall collapsible configuration through engagement of the lid to the base interface. This could be accomplished either by the vertical insertion of the lid over the base or through a living hinge folding action of the lid around the base. This provides for the reduction of excess movement of the semiconductor wafers in the cavity of the wafer box.
• Figure 1 is a top plan view of the tray of the wafer box of the present invention.
• Figure 2 is a side plan view of the tray of the wafer box of the present invention.
• Figure 3 is a front plan view of the tray of the wafer box of the present invention.
• Figure 4 is a perspective view of the tray of the wafer box of the present invention.
• Figure 5 is a top plan view of the cover of the wafer box of the present invention.
• Figure 6 is a side plan view of the cover of the wafer box of the present invention.
• Figure 7 is a front plan view of the cover of the wafer box of the present invention.
• Figure 8 is a perspective view of the cover of the wafer box of the present invention.
• the tray 10 of the wafer box of the present invention includes a planar base 12 which is square or rectangular in shape, as bounded by sides 14, 16, 18, 20.
• Side 20 includes an indented area 22.
• Indented area 22 in combination with a similar indented area on the cover as will be described hereinafter in more detail, provides the opportunity for the user, or even automated machinery, to separate easily the tray 10 from the cover.
• Outer walls 24, 26, 28, 30 rise inwardly adjacent from sides 14, 16, 18, 20, respectively, and terminate in elevated planar ledge area 32.
• Inner walls 34, 36, 38, 40 extend from the interior of elevated planar ledge area 32 to planar base 12 thereby forming wafer cavity 42 therewithin.
• Outer walls 24, 26, 28, 30 include semi-circular downwardly tapered concave portions 44 which add to the rigidity of the outer walls.
• the portion of planar base 12 within wafer cavity 42 includes lattice 46 of ridges thereby mechanically isolating any wafers (not shown) within wafer cavity 42 from inner walls 34, 36, 38, 40 and acting as a shock absorber against vertical impact and vibration.
• horizontal semi-circular channels 48, 50, 52, 54 are formed between respective outer walls 24, 26, 28, 30 and inner walls 34, 36, 38, 40.
• Channels 48, 50, 52, 54 perform spacing, strengthening and horizontal shock-absorbing functions.
• a pair of detent dimples 60 is formed on each of outer walls 24, 26, 28, 30 at about the one quarter and three quarters position along the span of each of the outer walls.
• cover 62 of the wafer box includes lower rim 64 bounded by sides 66, 68, 70, 72 which generally correspond to the footprint of base 12 of tray 10.
• side 72 includes indented area 74 which is intended to be laterally offset from indented area 22 when side 72 of cover 62 is aligned with side 20 of tray 10.
• indented area 22 is on the left portion of side 20 while indented area 74 is on the right portion of side 72.
• Cover side walls 76, 78, 80, 82 rise from lower rim 64 and terminate in cover upper planar surface 83.
• Cover upper planar surface 83 may be formed of translucent material so that (large print) printed material inside may reduce the need for labeling of the wafer box.
• Cover side walls 76, 78, 80, 82 are shaped so as to be able to outwardly engage outer walls 24, 26, 28, 30 when cover 62 is placed over tray 10 thereby forming a double thickness outer wall configuration.
• Cover side walls 76, 78, 80, 82 include semi-circular downwardly tapered concave portions 84 which outwardly engage and mate to semi-circular downwardly tapered concave portions 44 of tray 10 in the installed position.
• Central planar label areas 86 are formed at a central portion of each of cover side walls 76, 78, 80, 82, between the two interior semi-circular concave portions 84.
• a pair of detent dimples 88 is formed on each of cover side walls 76, 78, 80, 82 at about the one quarter and three quarters position along the span of each of the cover side walls.
• detent dimples 88 of cover 62 extend into detent dimples 60 of tray 10 thereby forming a detent relationship.
• Corner pedestals 90 rise from the intersections of the cover side walls 76, 78, 80, 82 while mid-span pedestals 92 rise from the mid-point of cover side walls 76, 78, 80, 82.
• Pedestals 90, 92 provide standoff clearance when full wafer boxes are inter-stacked so that transmission of shock and vibration through the inter-stack configuration is minimized or eliminated.
• Tray 10 and cover 62 are typically formed of thermoformed material, although those skilled in the art will recognize a range of equivalents after review of this disclosure.
• semiconductor wafers (not shown) are loaded into wafer cavity 42 of tray 10.
• Cover 62 is then placed vertically over tray 10 so that detent dimples 88 of cover 62 extend into detent dimples 60 of tray 10 thereby forming a detent relationship, semi-circular downwardly tapered concave portions 84 of cover 62 outwardly engage and mate to semi-circular downwardly tapered concave portions 44 of tray 10, and indented areas 22 and 74 are laterally offset from each other thereby forming an interlocked offset flange configuration.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Mechanical Engineering (AREA)
• Packaging Frangible Articles (AREA)

Applications Claiming Priority (3)

Publications (2)

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ID=34572862

Family Applications (1)

Country Status (5)

Families Citing this family (12)

Citations (1)

Family Cites Families (8)

• 2004
  • 2004-05-18 JP JP2006537959A patent/JP4335921B2/ja not_active Expired - Fee Related
  • 2004-05-18 CN CN2004800252401A patent/CN1845860B/zh not_active Expired - Fee Related
  • 2004-05-18 KR KR1020067005008A patent/KR101125775B1/ko not_active IP Right Cessation
  • 2004-05-18 EP EP04752489A patent/EP1685038A4/en not_active Withdrawn
  • 2004-05-18 WO PCT/US2004/015480 patent/WO2005044695A1/en active Application Filing

Patent Citations (1)

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