EP1685038A4 - Low cost wafer box improvements - Google Patents

Low cost wafer box improvements

Info

Publication number
EP1685038A4
EP1685038A4 EP04752489A EP04752489A EP1685038A4 EP 1685038 A4 EP1685038 A4 EP 1685038A4 EP 04752489 A EP04752489 A EP 04752489A EP 04752489 A EP04752489 A EP 04752489A EP 1685038 A4 EP1685038 A4 EP 1685038A4
Authority
EP
European Patent Office
Prior art keywords
container
side walls
semiconductor wafers
cover
tray
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04752489A
Other languages
German (de)
French (fr)
Other versions
EP1685038A1 (en
Inventor
Valoris L Forsyth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Illinois Tool Works Inc
Original Assignee
Illinois Tool Works Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Illinois Tool Works Inc filed Critical Illinois Tool Works Inc
Publication of EP1685038A1 publication Critical patent/EP1685038A1/en
Publication of EP1685038A4 publication Critical patent/EP1685038A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735—Closed carriers
    • H01L21/67369—Closed carriers characterised by shock absorbing elements, e.g. retainers or cushions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
    • B65D21/00—Nestable, stackable or joinable containers; Containers of variable capacity
    • B65D21/02—Containers specially shaped, or provided with fittings or attachments, to facilitate nesting, stacking, or joining together
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735—Closed carriers
    • H01L21/67386—Closed carriers characterised by the construction of the closed carrier

Definitions

  • the present invention relates to a containment device or wafer box for transporting semiconductor wafers, particularly utilizing thermoformed material in place of other transport wafer packaging systems utilized in shipping wafers from a front-end wafer fabrication facility to a back-end product manufacturing facility.
  • the wafer box of the present invention includes a bottom floor attachment design which mechanically isolates wafers from side walls thereby acting as a shock absorber against vertical impact and vibration; a side wall configuration which isolates interior walls and the cavity from horizontal shock impact; a pedestal configuration at the corners and mid-span which provides standoff clearance when full boxes are inter-stacked, so that shock and vibration are not transmitted through the inter- stack configuration; a side wall configuration comprised of mating surfaces from the lid and bottom to create a double thickness wall thereby allowing substantially increased stacking capabilities; interlocking engagement elements on four sides to provide full engagement and survival of multiple drops of fully loaded wafer boxes (typically including 16 semiconductor wafers); interlocked offset flanges to provide for simple separation of the base from the lid; a large side wall flat surface to provide for the attachment of a large label along the side of the wafer box; and translucent material along the top of the wafer box so that large print paperwork is visible through the
  • the wafer box can include a side wall collapsible configuration through engagement of the lid to the base interface. This could be accomplished either by the vertical insertion of the lid over the base or through a living hinge folding action of the lid around the base. This provides for the reduction of excess movement of the semiconductor wafers in the cavity of the wafer box.
  • Figure 1 is a top plan view of the tray of the wafer box of the present invention.
  • Figure 2 is a side plan view of the tray of the wafer box of the present invention.
  • Figure 3 is a front plan view of the tray of the wafer box of the present invention.
  • Figure 4 is a perspective view of the tray of the wafer box of the present invention.
  • Figure 5 is a top plan view of the cover of the wafer box of the present invention.
  • Figure 6 is a side plan view of the cover of the wafer box of the present invention.
  • Figure 7 is a front plan view of the cover of the wafer box of the present invention.
  • Figure 8 is a perspective view of the cover of the wafer box of the present invention.
  • the tray 10 of the wafer box of the present invention includes a planar base 12 which is square or rectangular in shape, as bounded by sides 14, 16, 18, 20.
  • Side 20 includes an indented area 22.
  • Indented area 22 in combination with a similar indented area on the cover as will be described hereinafter in more detail, provides the opportunity for the user, or even automated machinery, to separate easily the tray 10 from the cover.
  • Outer walls 24, 26, 28, 30 rise inwardly adjacent from sides 14, 16, 18, 20, respectively, and terminate in elevated planar ledge area 32.
  • Inner walls 34, 36, 38, 40 extend from the interior of elevated planar ledge area 32 to planar base 12 thereby forming wafer cavity 42 therewithin.
  • Outer walls 24, 26, 28, 30 include semi-circular downwardly tapered concave portions 44 which add to the rigidity of the outer walls.
  • the portion of planar base 12 within wafer cavity 42 includes lattice 46 of ridges thereby mechanically isolating any wafers (not shown) within wafer cavity 42 from inner walls 34, 36, 38, 40 and acting as a shock absorber against vertical impact and vibration.
  • horizontal semi-circular channels 48, 50, 52, 54 are formed between respective outer walls 24, 26, 28, 30 and inner walls 34, 36, 38, 40.
  • Channels 48, 50, 52, 54 perform spacing, strengthening and horizontal shock-absorbing functions.
  • a pair of detent dimples 60 is formed on each of outer walls 24, 26, 28, 30 at about the one quarter and three quarters position along the span of each of the outer walls.
  • cover 62 of the wafer box includes lower rim 64 bounded by sides 66, 68, 70, 72 which generally correspond to the footprint of base 12 of tray 10.
  • side 72 includes indented area 74 which is intended to be laterally offset from indented area 22 when side 72 of cover 62 is aligned with side 20 of tray 10.
  • indented area 22 is on the left portion of side 20 while indented area 74 is on the right portion of side 72.
  • Cover side walls 76, 78, 80, 82 rise from lower rim 64 and terminate in cover upper planar surface 83.
  • Cover upper planar surface 83 may be formed of translucent material so that (large print) printed material inside may reduce the need for labeling of the wafer box.
  • Cover side walls 76, 78, 80, 82 are shaped so as to be able to outwardly engage outer walls 24, 26, 28, 30 when cover 62 is placed over tray 10 thereby forming a double thickness outer wall configuration.
  • Cover side walls 76, 78, 80, 82 include semi-circular downwardly tapered concave portions 84 which outwardly engage and mate to semi-circular downwardly tapered concave portions 44 of tray 10 in the installed position.
  • Central planar label areas 86 are formed at a central portion of each of cover side walls 76, 78, 80, 82, between the two interior semi-circular concave portions 84.
  • a pair of detent dimples 88 is formed on each of cover side walls 76, 78, 80, 82 at about the one quarter and three quarters position along the span of each of the cover side walls.
  • detent dimples 88 of cover 62 extend into detent dimples 60 of tray 10 thereby forming a detent relationship.
  • Corner pedestals 90 rise from the intersections of the cover side walls 76, 78, 80, 82 while mid-span pedestals 92 rise from the mid-point of cover side walls 76, 78, 80, 82.
  • Pedestals 90, 92 provide standoff clearance when full wafer boxes are inter-stacked so that transmission of shock and vibration through the inter-stack configuration is minimized or eliminated.
  • Tray 10 and cover 62 are typically formed of thermoformed material, although those skilled in the art will recognize a range of equivalents after review of this disclosure.
  • semiconductor wafers (not shown) are loaded into wafer cavity 42 of tray 10.
  • Cover 62 is then placed vertically over tray 10 so that detent dimples 88 of cover 62 extend into detent dimples 60 of tray 10 thereby forming a detent relationship, semi-circular downwardly tapered concave portions 84 of cover 62 outwardly engage and mate to semi-circular downwardly tapered concave portions 44 of tray 10, and indented areas 22 and 74 are laterally offset from each other thereby forming an interlocked offset flange configuration.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

The wafer box includes a tray (10) and a cover (62) . The tray (10) includes an inner (34, 36, 38, 40) and outer (24, 26, 28, 30) wall configuration with horizontal semi­circular channels (48, 50, 52, 54) therebetween to perform spacing, strengthening and horizontal shock-absorbing functions. The tray (10) further includes a wafer cavity (42) formed within the inner wall (34, 36, 38, 40) . The wafer cavity (42) includes a lattice (46) of ridges on the floor thereof to provide a vertical shock absorbing function. The wall (76, 78, 80, 82) of the cover (62) engages and mates to the outer wall (24, 26, 28, 30) of the tray (10) thereby forming a double wall configuration. A pedestal configuration (90, 92) is formed on the comers and mid-spans of the top of the cover (62) to provide standoff clearance between the inter-stacked boxes to minimize or eliminate the transmission of shock and vibration through an inter-stack configuration.

Description

3029-165 LOW COST WAFER BOX IMPROVEMENTS
14426-99
This application claims priority from provisional application serial number 60/515,869, filed October 29, 2003.
BACKGROUND OF THE INVENTION
Field of the Invention The present invention relates to a containment device or wafer box for transporting semiconductor wafers, particularly utilizing thermoformed material in place of other transport wafer packaging systems utilized in shipping wafers from a front-end wafer fabrication facility to a back-end product manufacturing facility.
Description of the Prior Art The prior art contains a variety of designs for the containment and transport of semiconductor wafers. These designs must provide both electrostatic and mechanical protection for the wafers contained therein. Preferably, such containment devices should be easily adaptable to various automated apparatus which load or unload the semiconductor wafers. Such containment devices should have a simple design which is reliable and economical to mass produce. Additionally, such containment devices should be compliant to industry standards to achieve equipment handling capability. Examples of some prior art are U.S. Patent No. 6,193,068 entitled "Containment Device for Retaining Semiconductor Wafers" issued on February 27, 2001 to Lewis et al.; U.S. Patent No. 6,286,684 entitled "Protective System for Integrated Circuit (IC) Wafers Retained Within Containers Designed for Storage and Shipment" issued on September 11,
1179465A01051004 2001 to Brooks et al.; U.S. Patent No. 6,003,674 entitled "Method and Apparatus for Packing Contaminant-Sensitive Articles and Resulting Package" issued on December 21, 1999 to Brooks; and U.S. Patent No. 5,724,748 entitled "Apparatus for Packaging Contaminant- Sensitive Articles and Resulting Package" issued on March 10, 1998 to Brooks et al.
OBJECTS AND SUMMARY OF THE INVENTION In order to attain the above and other objects, the wafer box of the present invention includes a bottom floor attachment design which mechanically isolates wafers from side walls thereby acting as a shock absorber against vertical impact and vibration; a side wall configuration which isolates interior walls and the cavity from horizontal shock impact; a pedestal configuration at the corners and mid-span which provides standoff clearance when full boxes are inter-stacked, so that shock and vibration are not transmitted through the inter- stack configuration; a side wall configuration comprised of mating surfaces from the lid and bottom to create a double thickness wall thereby allowing substantially increased stacking capabilities; interlocking engagement elements on four sides to provide full engagement and survival of multiple drops of fully loaded wafer boxes (typically including 16 semiconductor wafers); interlocked offset flanges to provide for simple separation of the base from the lid; a large side wall flat surface to provide for the attachment of a large label along the side of the wafer box; and translucent material along the top of the wafer box so that large print paperwork is visible through the top of the box in order to reduce or eliminate the need for additional labels around the box. Optionally, the wafer box can include a side wall collapsible configuration through engagement of the lid to the base interface. This could be accomplished either by the vertical insertion of the lid over the base or through a living hinge folding action of the lid around the base. This provides for the reduction of excess movement of the semiconductor wafers in the cavity of the wafer box.
BRIEF DESCRIPTION OF THE DRAWINGS Further objects and advantages will become apparent from the following description and from the accompanying drawings, wherein: Figure 1 is a top plan view of the tray of the wafer box of the present invention. Figure 2 is a side plan view of the tray of the wafer box of the present invention. Figure 3 is a front plan view of the tray of the wafer box of the present invention. Figure 4 is a perspective view of the tray of the wafer box of the present invention. Figure 5 is a top plan view of the cover of the wafer box of the present invention. Figure 6 is a side plan view of the cover of the wafer box of the present invention. Figure 7 is a front plan view of the cover of the wafer box of the present invention. Figure 8 is a perspective view of the cover of the wafer box of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawings in detail wherein like numerals indicate like elements throughout the several views, one sees from Figures 1-4 that the tray 10 of the wafer box of the present invention includes a planar base 12 which is square or rectangular in shape, as bounded by sides 14, 16, 18, 20. Side 20 includes an indented area 22. Indented area 22, in combination with a similar indented area on the cover as will be described hereinafter in more detail, provides the opportunity for the user, or even automated machinery, to separate easily the tray 10 from the cover. Outer walls 24, 26, 28, 30 rise inwardly adjacent from sides 14, 16, 18, 20, respectively, and terminate in elevated planar ledge area 32. Inner walls 34, 36, 38, 40 extend from the interior of elevated planar ledge area 32 to planar base 12 thereby forming wafer cavity 42 therewithin. Outer walls 24, 26, 28, 30 include semi-circular downwardly tapered concave portions 44 which add to the rigidity of the outer walls. Furthermore, the portion of planar base 12 within wafer cavity 42 includes lattice 46 of ridges thereby mechanically isolating any wafers (not shown) within wafer cavity 42 from inner walls 34, 36, 38, 40 and acting as a shock absorber against vertical impact and vibration. Similarly, horizontal semi-circular channels 48, 50, 52, 54 are formed between respective outer walls 24, 26, 28, 30 and inner walls 34, 36, 38, 40. Channels 48, 50, 52, 54 perform spacing, strengthening and horizontal shock-absorbing functions. A pair of detent dimples 60 is formed on each of outer walls 24, 26, 28, 30 at about the one quarter and three quarters position along the span of each of the outer walls. One sees from Figures 5-8 that cover 62 of the wafer box includes lower rim 64 bounded by sides 66, 68, 70, 72 which generally correspond to the footprint of base 12 of tray 10. However, side 72 includes indented area 74 which is intended to be laterally offset from indented area 22 when side 72 of cover 62 is aligned with side 20 of tray 10. That is, when viewed from the perspective of Figures 4 and 8, indented area 22 is on the left portion of side 20 while indented area 74 is on the right portion of side 72. This forms an interlocked offset flange configuration which allows the user to grasp sides 20 and 72 between a thumb and forefinger and disengage cover 62 from tray 10 with a simple twisting motion. Cover side walls 76, 78, 80, 82 rise from lower rim 64 and terminate in cover upper planar surface 83. Cover upper planar surface 83 may be formed of translucent material so that (large print) printed material inside may reduce the need for labeling of the wafer box. Cover side walls 76, 78, 80, 82 are shaped so as to be able to outwardly engage outer walls 24, 26, 28, 30 when cover 62 is placed over tray 10 thereby forming a double thickness outer wall configuration. Cover side walls 76, 78, 80, 82 include semi-circular downwardly tapered concave portions 84 which outwardly engage and mate to semi-circular downwardly tapered concave portions 44 of tray 10 in the installed position. Central planar label areas 86 are formed at a central portion of each of cover side walls 76, 78, 80, 82, between the two interior semi-circular concave portions 84. A pair of detent dimples 88 is formed on each of cover side walls 76, 78, 80, 82 at about the one quarter and three quarters position along the span of each of the cover side walls. When cover 62 is installed over tray 10, detent dimples 88 of cover 62 extend into detent dimples 60 of tray 10 thereby forming a detent relationship. Corner pedestals 90 rise from the intersections of the cover side walls 76, 78, 80, 82 while mid-span pedestals 92 rise from the mid-point of cover side walls 76, 78, 80, 82. Pedestals 90, 92 provide standoff clearance when full wafer boxes are inter-stacked so that transmission of shock and vibration through the inter-stack configuration is minimized or eliminated. Tray 10 and cover 62 are typically formed of thermoformed material, although those skilled in the art will recognize a range of equivalents after review of this disclosure. To use the resulting wafer box, semiconductor wafers (not shown) are loaded into wafer cavity 42 of tray 10. Cover 62 is then placed vertically over tray 10 so that detent dimples 88 of cover 62 extend into detent dimples 60 of tray 10 thereby forming a detent relationship, semi-circular downwardly tapered concave portions 84 of cover 62 outwardly engage and mate to semi-circular downwardly tapered concave portions 44 of tray 10, and indented areas 22 and 74 are laterally offset from each other thereby forming an interlocked offset flange configuration. Thus the several aforementioned objects and advantages are most effectively attained. Although a single preferred embodiment of the invention has been disclosed and described in detail herein, it should be understood that this invention is in no sense limited thereby and its scope is to be determined by that of the appended claims.

Claims

What is Claimed is:
1. A container for semiconductor wafers, comprising: a tray element including a planar base, outer side walls rising from said planar base, inner side walls formed inwardly adjacent from said outer side walls and forming a wafer containment area therewithin, and lateral shocking absorbing means formed between said inner side walls and said outer side walls; and a cover element including a planar top and cover side walls extending from said planar top wherein, when said cover element is engaged with said tray element, said cover side walls are outwardly adjacent from said outer walls of said tray element.
2. The container for semiconductor wafers of Claim 1 wherein said outer side walls include first semi-circular concave portions and said cover side walls include second semi-circular concave portions wherein, when said cover element is engaged with said tray element, said first semi-circular concave portions engage said second semi-circular concave portions.
3. The container for semiconductor wafers of Claim 2 wherein said first and second semicircular concave portions are downwardly tapered.
4. The container for semiconductor wafers of Claim 1 wherein said lateral shock absorbing means comprises channels formed between respective said inner side walls and said outer side walls.
5. The container for semiconductor wafers of Claim 4 wherein said channels are formed by walls perpendicular to said inner side walls and said outer side walls.
6. The container for semiconductor wafers of Claim 5 wherein said channels are semicircular.
7. The container for semiconductor wafers of Claim 1 wherein said planar base includes protrusions which form lower shock absorbing means.
8. The container for semiconductor wafers of Claim 7 wherein said protrusions form a lattice of ridges.
9. The container for semiconductor wafers of Claim 1 wherein said cover side walls terminate in a rim, said rim including a portion which is parallel to said planar top.
10. The container for semiconductor wafers of Claim 9 wherein, when said cover element is engaged with said tray element, said rim abuts with a portion of said planar base outward from said outer side walls.
11. The container for semiconductor wafers of Claim 10 wherein said rim includes first indented areas and wherein said planar base outward from said outer side walls includes second indented areas.
12. The container for semiconductor wafers of Claim 11 wherein said first indented areas are offset from said second indented areas thereby forming an interlocked offset flange configuration facilitating the separation of said cover element from said tray element.
13. The container for semiconductor wafers of Claim 1 wherein said outer side walls include first detent elements and said cover side walls include second detent elements wherein, when said cover element is engaged with said tray element, said first detent elements engage said second detent elements.
14. The container for semiconductor wafers of Claim 13 wherein said first detent elements and said second detent elements are dimples.
15. The container for semiconductor wafers of Claim 1 wherein said planar top includes offset elements to offset the container from a successive upper container.
16. The container for semiconductor wafers of Claim 15 wherein said offset elements include pedestal elements formed on said planar top at intersections of said cover side walls.
17. The container for semiconductor wafers of Claim 15 wherein said offset elements include pedestal elements formed on said planar top at mid-spans of said cover side walls.
18. The container for semiconductor wafers of Claim 1 wherein at least a portion of said planar top is translucent.
19. The container for semiconductor wafers of Claim 1 wherein said cover side walls include central planar label areas.
20. The container for semiconductor wafers of Claim 1 wherein said tray element and said cover element are formed of thermoformed plastic.
EP04752489A 2003-09-23 2004-05-18 Low cost wafer box improvements Withdrawn EP1685038A4 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US50517503P 2003-09-23 2003-09-23
US51586903P 2003-10-29 2003-10-29
PCT/US2004/015480 WO2005044695A1 (en) 2003-09-23 2004-05-18 Low cost wafer box improvements

Publications (2)

Publication Number Publication Date
EP1685038A1 EP1685038A1 (en) 2006-08-02
EP1685038A4 true EP1685038A4 (en) 2008-11-26

Family

ID=34572862

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04752489A Withdrawn EP1685038A4 (en) 2003-09-23 2004-05-18 Low cost wafer box improvements

Country Status (5)

Country Link
EP (1) EP1685038A4 (en)
JP (1) JP4335921B2 (en)
KR (1) KR101125775B1 (en)
CN (1) CN1845860B (en)
WO (1) WO2005044695A1 (en)

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EP2209726A4 (en) 2007-10-12 2012-08-15 Peak Plastic & Metal Prod Wafer container with staggered wall structure
CN101459099B (en) * 2007-12-13 2010-11-10 中芯国际集成电路制造(上海)有限公司 Wafer kit, monitoring system and method for semi-conductor production process
CN101752281B (en) * 2008-12-02 2013-02-13 家登精密工业股份有限公司 Load-bearing box of wafer load-bearing device
US8813964B2 (en) 2009-08-26 2014-08-26 Texchem Advanced Products Incorporated Sdn. Bhd. Wafer container with recessed latch
US8556079B2 (en) 2009-08-26 2013-10-15 Texchem Advanced Products Incorporated Sdn Bhd Wafer container with adjustable inside diameter
US8109390B2 (en) 2009-08-26 2012-02-07 Texchem Advanced Products Incorporated Sdn Bhd Wafer container with overlapping wall structure
DE102010018668B4 (en) * 2010-04-07 2012-11-15 Curamik Electronics Gmbh Packaging unit for metal-ceramic substrates
TW201233602A (en) * 2010-10-29 2012-08-16 Entegris Inc Substrate shipper
JP6044635B2 (en) * 2011-07-29 2016-12-14 ロジャース ジャーマニー ゲーエムベーハー Packaging for substrates and packaging units comprising such packaging
CN102717982A (en) * 2012-07-02 2012-10-10 深圳市华星光电技术有限公司 Packaging device of liquid crystal glass
KR102425700B1 (en) * 2019-06-10 2022-07-28 삼성에스디아이 주식회사 Tray for packing secondary battery

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Also Published As

Publication number Publication date
CN1845860A (en) 2006-10-11
KR20070006665A (en) 2007-01-11
WO2005044695A1 (en) 2005-05-19
WO2005044695A8 (en) 2006-06-01
JP2007505798A (en) 2007-03-15
CN1845860B (en) 2011-01-19
JP4335921B2 (en) 2009-09-30
EP1685038A1 (en) 2006-08-02
KR101125775B1 (en) 2012-03-28

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