KR101125775B1 - Low cost wafer box improvements - Google Patents

Abstract

The wafer box includes a tray 10 and a cover 62. Tray 10 has an interior wall 34, 36, 38, 40 and an exterior with horizontal semi-circular channels 48, 50, 52, 54 therebetween for performing spacing, reinforcement and horizontal shock-mitigation functions. Wall 24, 26, 28, 30 configurations. The tray 10 further includes a wafer cavity 42 formed in the inner walls 34, 36, 38, and 40. Wafer cavity 42 includes a grating 46 of ridges on the bottom of the cavity to provide a vertical shock absorbing function. The walls 76, 78, 80, 82 of the cover 62 engage and engage the outer walls 24, 26, 28, 30 of the tray 10, thereby forming a double wall configuration. Retainer configurations 90 and 92 are formed over the corners and mid-spans of cover 62 to provide isolation clearance between interstacked boxes to minimize or eliminate transmission of shock and vibration through interstack configurations. .

Description

LOW COST WAFER BOX IMPROVEMENTS}

This application claims priority from Provisional Patent Application No. 60 / 515,869, filed October 29, 2003.

The present invention provides for semiconductor wafer transport, in particular using thermoformed materials in place of other transport wafer package systems used to load wafers from front-end wafer fabrication equipment to back-end product fabrication equipment. A storage device or a wafer box.

The prior art includes various designs for the storage and transportation of semiconductor wafers. This design must provide both static and mechanical protection for the wafers contained therein. Desirably, such a storage device should be easily adaptable to various automated devices for loading or unloading semiconductor wafers. Such a storage device should have a simple design that is reliable and economical for mass production. In addition, such receiving devices must comply with industry standards for achieving equipment processing capabilities.

Some examples of the prior art are as follows;

US Patent No. 6,193,068 entitled "Acceptive Device for Holding Semiconductor Wafers", issued February 27, 2001 to Lewis et al .; US Patent No. 6,286,684 to Brooks et al. On September 11, 2001 entitled “Protection System for Integrated Circuit (IC) Wafers Retained in Containers Designed for Storage and Loading”; US Patent No. 6,003,674 entitled Brooks, Dec. 21, 1999 entitled “Method and Apparatus for Packaging Contaminant-Sensitive Goods and the Resultant Package”; US Patent No. 5,724,748 to Brooks et al. On March 10, 1998 entitled "A device for packaging contaminant sensitive goods and the resulting package."

In order to achieve the above and other objects, the wafer box of the present invention has a bottom attachment design which mechanically isolates the wafer from the side wall which acts as a shock absorber for vertical shock and vibration, the inner wall and cavity from horizontal impact. Side wall configuration to isolate, pedestal configuration of corner and middle area to provide standoff clearance when the filled box is interstacked so that shock and vibration are not transmitted through the interstack configuration, Side wall configuration consisting of a lid and mating surface from the bottom to create a double-thick wall allowing virtually increased stacking capacity, multiple of fully loaded wafer boxes (typically containing 16 semiconductor wafers) Interlocking on four sides to provide drop survival and full engagement Bite elements, interconnected offset flange configuration provided for simple separation of the base from the lid, large side wall planes provided for the attachment of large labels along the sides of the wafer box, and large print documents work for additional labels around the box It includes translucent material along the top of the wafer box to be visible through the top of the box to reduce or eliminate the need.

Optionally, the wafer box may include a configuration in which the side walls are folded through engagement of the lid with the base interface. This can be achieved by vertical insertion of the lid onto the base or through a strong hinge folding action of the lid around the base. This is provided for the reduction of excessive movement of the semiconductor wafer in the cavity of the wafer box.

Further objects and advantages will become apparent from the accompanying drawings and the following description.

1 is a plan view of a tray of a wafer box of the present invention.

2 is a side view of a tray of a wafer box of the present invention.

3 is a front view of a tray of the wafer box of the present invention.

4 is a perspective view of a tray of the wafer box of the present invention.

5 is a plan view of the cover of the wafer box of the present invention.

Fig. 6 is a side view of the cover of the wafer box of the present invention.

Fig. 7 is a front view of the cover of the wafer box of the present invention.

8 is a perspective view of a cover of the wafer box of the present invention.

Reference is now made in detail to the drawings, wherein like numerals represent like elements throughout the several views, and the tray 10 of the wafer box of the present invention is square in shape, as defined by the sides 14, 16, 18, 20. Alternatively, it can be seen from FIGS. 1 to 4 that include a rectangular flat base 12. Side 20 includes indented region 22. The indented area 22 provides an opportunity for a user or even an automated machine to easily separate the tray 10 from the cover in combination with a similar indented area on the cover as will be described in more detail below. The outer walls 24, 26, 28, 30 rise inwardly adjacent from the sides 14, 16, 18, 20, respectively, and end with raised flat ledge areas 32. The inner walls 34, 36, 38, 40 extend from the interior of the raised flat ledge region 32 to the flat base 12, which forms a wafer cavity 42 therein.

The outer walls 24, 26, 28, 30 include semi-circular downwardly tapered recesses 44 that add to the stiffness of the outer wall. In addition, the portion of the flat base 12 in the wafer cavity 42 includes a grating 46 of ridges, thereby internally walling any wafer (not shown) in the wafer cavity 42. It mechanically isolates from (34,36,38,40) and functions as a shock absorber against vertical shock and vibration.

Similarly, horizontal semi-circular channels 48, 50, 52, 54 are formed between the outer walls 24, 26, 28, 30 and the inner walls 34, 36, 38, 40, respectively. Channels 48, 50, 52 and 54 perform spacing, reinforcement and horizontal shock-absorption functions.

A pair of detent dimples 60 are formed in each of the outer walls 24, 26, 28, 30 at about 1/4 and 3/4 positions along each area of the outer wall.

The cover 62 of the wafer box has a lower rim 64, which is generally defined by the sides 66, 68, 70, 72 that correspond to the footprint of the base 12 of the tray 10. It can be seen that includes. However, the side surface 72 is an indented region 74 intended to be laterally offset from the indented region 22 when the side 72 of the cover 62 is aligned with the side 20 of the tray 10. It includes. That is, as shown in the perspective views of FIGS. 4 and 8, the indented region 22 is the left side of the side 20, while the indented region 74 is the right side of the side 72. This forms an interconnected offset flange configuration that allows the user to grip the sides 20 and 72 between the thumb and forefinger and to detach the cover 62 from the tray 10 in a simple twisting motion.

The cover side walls 76, 78, 80, 82 rise from the lower rim 64 and end with a cover upper flat surface 83. The cover upper flat surface 83 is formed of a translucent material so that the (large print) printed material therein can reduce the need for labeling of the wafer box. The cover side walls 76, 78, 80, 82 are shaped to engage the outer walls 24, 26, 28, 30 outward when the cover 62 is positioned over the tray 10, This forms a double thickness outer wall configuration. The cover side walls 76, 78, 80, 82 face down downwards in a semi-circle that engages and engages outwardly with the tapered recess 44 toward the bottom of the semi-circle of the tray 10 in the installation position. Tapered recesses 84. A central flat label region 86 is formed in each central portion of the cover side walls 76, 78, 80, 82 between two inner semi-circular recesses 84.

A pair of detent recesses 88 are formed in each of the cover side walls 76, 78, 80, 82 at about 1/4 and 3/4 positions along each area of the cover side wall. When the cover 62 is installed on the tray 10, the detent recess 88 of the cover 62 extends into the detent recess 60 of the tray 10, thereby forming a detent relationship. do.

The corner bearing 90 rises from the intersection of the cover side walls 76, 78, 80, 82 while the middle area bearing 92 rises from the central point of the cover side walls 76, 78, 80, 82. have. Retainers 90 and 92 provide isolation clearance when the filled wafer box is interstacked such that the transmission of shock and vibration is minimized or eliminated through the interstack configuration.

Tray 10 and cover 62 are typically formed of a thermoformed material, but one of ordinary skill in the art will recognize the same range of materials after studying this disclosure.

In order to use the resulting wafer box, a semiconductor wafer (not shown) is loaded into the wafer cavity 42 of the tray 10. The cover 62 is then positioned vertically above the tray 10 such that the detent recess 88 of the cover 62 extends into the detent recess of the tray 10 thereby forming a detent relationship. And the semi-circular downwardly tapered recesses 84 of the cover 62 are engaged and engaged outwardly with the semi-circular downwardly tapered recesses 44 of the tray 10, and inden The tide regions 22 and 74 are laterally offset from one another and thereby form an interconnected flange configuration.

The above-mentioned objects and advantages are thus most effectively achieved. While a single preferred embodiment of the invention has been described and described in detail herein, it is to be understood that the invention is by no means limited thereto but its scope is determined by the scope of the appended claims.

The low cost wafer box improvement of the present invention is industrially available for wafer boxes.

Claims (20)

As a container for a semiconductor wafer, A flat base, an outer side wall that rises from the flat base, an inner side wall formed into and adjacent to the outer side wall and forming a wafer receiving region therein, and a side impact formed between the inner side wall and the outer side wall A tray element comprising absorbing means, A cover element comprising a flat top and a cover side wall extending from the flat top, wherein when the cover element engages the tray element, the cover side wall engages outwardly with the outer wall of the tray element; Cover elements Including, The outer side wall includes a first semi-circular recess, the cover side wall includes a second semi-circular recess, and the cover element engages the first semi-circular when engaged with the tray element. The recess of the mesh engages with the second semi-circular recess. delete The container of claim 1, wherein the first and second semi-circular recesses are tapered downward. The container for a semiconductor wafer according to claim 1, wherein said side impact absorbing means each comprise a channel formed between said inner side wall and said outer side wall. The container of claim 4, wherein the channel is formed by a wall perpendicular to the inner wall and the outer wall. 6. The container of claim 5, wherein the horizontal cross section of the channel is semi-circular. The container for a semiconductor wafer according to claim 1, wherein the flat base includes a protrusion forming a lower shock absorbing means. 8. The container of claim 7, wherein the protrusions form a lattice of ridges. The container of claim 1, wherein the cover side wall ends with a rim, the rim comprising a portion parallel to the flat top. 10. The container of claim 9, wherein the cover element is engaged with the tray element and the rim is engaged with a portion of the flat base facing outward from the outer side wall. The container of claim 10, wherein the rim comprises a first indented region and the flat base facing outward from the outer side wall comprises a second indented region. 12. The interlocked offset flange configuration of claim 11 wherein the first indented region is offset from the second indented region thereby thereby facilitating separation of the cover element from the tray element. Container for semiconductor wafers. 2. The first detent of claim 1, wherein the outer side wall comprises a first detent element and the cover side wall comprises a second detent element, wherein the cover element is engaged with the tray element. An element is in engagement with the second detent element. The container of claim 13, wherein the first detent element and the second detent element are dimples. The container of claim 1, wherein the flat top includes an offset element for offsetting the container from the top container. The container of claim 15, wherein the offset element comprises a bearing element formed at the flat top at the intersection of the cover side wall. The container of claim 15, wherein the offset element comprises a bearing element formed on the flat top in the mid-span of the cover side wall. The container of claim 1, wherein at least a portion of the flat top is translucent. The container of claim 1, wherein the cover side wall comprises a central flat label region. The container of claim 1, wherein the tray element and the cover element are formed of thermoformed plastic.

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