EP1634089A1 - Procede, systeme et circuit de controle d'erreurs de retard - Google Patents

Procede, systeme et circuit de controle d'erreurs de retard

Info

Publication number
EP1634089A1
EP1634089A1 EP04735277A EP04735277A EP1634089A1 EP 1634089 A1 EP1634089 A1 EP 1634089A1 EP 04735277 A EP04735277 A EP 04735277A EP 04735277 A EP04735277 A EP 04735277A EP 1634089 A1 EP1634089 A1 EP 1634089A1
Authority
EP
European Patent Office
Prior art keywords
test
circuit
clock signal
clock
logic circuitry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04735277A
Other languages
German (de)
English (en)
Inventor
Neal T. Wingen
Gregory E. Ehmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of EP1634089A1 publication Critical patent/EP1634089A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318577—AC testing, e.g. current testing, burn-in
    • G01R31/31858—Delay testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay

Definitions

  • the present invention relates generally to testing electrical circuits and, more particularly, to circuit testing methods and arrangements involving test signals including timing signals.
  • resistive electrical connection One such defect that has surfaced with high-speed operation of circuit sites exhibiting speed-sensitive defects is a resistive electrical connection.
  • Resistive interconnections have been a major circuit manufacturing problem in terms of yield, performance, and reliability, and this problem is expected to increase in importance as the number of interconnection levels and operating frequencies increase.
  • Such resistive connections tend to react slower than other circuit portions, resulting in a delay in the response of the circuit site to input signals (e.g., a delay fault).
  • a delay fault for example, can result in incorrect data being provided, switching delays or other problems.
  • test clock used during the test vector application
  • TCK test clock
  • This approach has typically required, for example, a tester with a high-speed test clock or other approach, such as a multiplier.
  • a circuit is tested using an approach involving a relatively low-speed operational clock and a high-speed test clock that is selectively implemented for clocking target circuitry.
  • the high-speed test clock is adapted to use inputs from a test signal generator and the operational clock to operate, or clock, logic circuitry while test signal inputs are provided to the target circuitry.
  • An output from the target circuitry is detected and a delay in the output (e.g., relative to an expected output) is detected as a delay fault.
  • a conventional tester can be used to analyze the circuit while also clocking the circuit with a high-speed clock that is controllable separately from the operational clock of the conventional tester.
  • a circuit tester having control signals is used to exercise a target circuit in a test mode using an operational clock while concurrently using a test-clock signal to exercise logic circuitry in the target circuit.
  • the operational clock signal has at least one clock cycle and the test-clock signal has at least four clock-state transitions that occur within the at least one clock cycle.
  • the operational clock has a frequency
  • the test-clock signal has a frequency that is at least twice as fast as the operational clock frequency.
  • the logic circuit In response to the test-clock signal, the logic circuit generates an output that is received and processed by the circuit tester to detect a delay fault in the target circuit.
  • a circuit device in still another example embodiment, includes an on-board high- speed clock circuit that is programmable and operable in connection with an external circuit tester.
  • the high-speed clock circuit is adapted to selectively use a high-speed clock signal from a high speed clock and test signals from the external circuit tester to selectively apply the high-speed clock signal to logic circuitry in the circuit device during a capture mode.
  • the high-speed clock circuit passes an operational speed clock signal from the external circuit tester.
  • the high-speed clock circuit executes a delay sequence at the initiation of the capture mode and clocks the logic circuitry with the high-speed clock signal during a middle portion of the capture cycle after the delay sequence is initiated. The high-speed clock circuit then disables the application of the highspeed clock signal prior to the end of the capture cycle.
  • FIG. 1 is a flow diagram for testing an electronic circuit, according to an example embodiment of the present invention
  • FIG. 2A shows an approach for circuit testing involving signal synchronization with a phase-locked loop (PLL), according to another example embodiment of the present invention
  • FIG. 2B shows an approach for circuit testing involving a delay-fault testing, according to another example embodiment of the present invention.
  • PLL phase-locked loop
  • FIG. 3 shows a circuit arrangement for circuit testing involving delivering a clock signal for delay-fault testing, according to another example embodiment of the present invention. While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.
  • the present invention is believed to be applicable to a variety of circuits and approaches involving and/or benefiting from testing, and in particular to testing involving timing approaches and circuits. While the present invention is not necessarily limited to such applications, an appreciation of various aspects of the invention is best gained through a discussion of examples in such an environment.
  • an electronic circuit is tested using an approach involving a high-speed clock circuit to selectively apply a high- speed clock signal to the electronic circuit during a test mode.
  • the high-speed clock circuit may be implemented, for example, in connection with a conventional-type circuit tester having an operational clock with a speed that is relatively slow.
  • the high-speed clock circuit is part of the electronic circuit being tested.
  • the high-speed clock circuit is part of a circuit tester that also has a slower operational clock as discussed above.
  • the high-speed clock circuit is separate from the electronic circuit being tested and from a circuit tester used for applying test signals to the electronic circuit.
  • a timing-related change therein is used to detect the presence of a timing-type condition, such as a resistive circuit or a delay fault.
  • a circuit tester may be operated in a conventional (i.e., low speed) mode for operating the electronic circuit, with the detection of the output generated in response to the test-clock signal being effected without necessarily modifying the operation of the circuit tester.
  • the high-speed clock circuit is adapted to use inputs from a circuit tester for selectively applying the high-speed clock signal during a middle portion of a capture mode of the circuit tester.
  • Several clock-state transitions are generated during a single period of the operational clock signal by the high-speed clock circuit.
  • a start input e.g., a scan enable input
  • a sequence of timing events that selectively delays the application of the high-speed clock signal for one or more of the clock-state transitions thereof after the capture mode has been initiated.
  • the sequence of timing events are executed using logic circuitry that also disables the high-speed clock signal prior to the termination of the capture mode.
  • FIG. 1 is a flow diagram showing an approach for delay fault testing of an electronic circuit, according to an example embodiment of the present invention.
  • a circuit tester is enabled and generates a relatively low-speed clock signal (e.g., a clock signal for a JTAG (Joint Test Access Group) tester using automatic test pattern generation (ATPG)).
  • a rapid clock signal is generated (e.g., using clock generation circuitry on the electronic circuit).
  • a test scan is enabled at block 130 for testing the electronic circuit using the relatively low-speed clock signal.
  • a delay sequence for delaying the implementation of the rapid clock with the electronic circuit is begun at block 140 (e.g., in a capture mode) and held for a selected amount of time.
  • the rapid clock is applied for clocking the target circuit at block 150 for a short time period (e.g., a few clock-state transitions) for detecting a delay fault, and the rapid clock is disabled at block 160.
  • An output from the target circuit as operated by the rapid clock is received at block 170, which may, for example, be detected at least in part during the disabling of the rapid clock signal at block 160.
  • the output is evaluated at block 180 for a delay fault. If there is no additional delay (i.e., during block 150 ), the signal is detected as not being indicative of a defect. However, if there is additional delay in the output signal (during block 150), the delay is detected as being indicative of a defective circuit, such as one having a resistive connection.
  • the clock application can be repeated, for example, for shifting in a new test vector and restarting the sequence beginning at block 110.
  • the approach discussed above can be implemented using a variety of approaches for detecting a delayed signal.
  • One such approach involves using a phase-locked-loop (PLL) to generate the capture clock for an output signal, such as the clock signal generated at block 110 in FIG. 1.
  • PLL phase-locked-loop
  • the PLL is implemented, for example, using circuitry on the target circuit to generate a system frequency. For instance, when an output of a target circuit being analyzed is known relative to an input clock signal (e.g., as "locked" to a clock-state transition of the input clock signal), an unexpected change in the output can be used to detect a delayed response.
  • FIG. 2A exemplifies another approach to locking that is implemented in connection with one example embodiment of the present invention, with a rapid clock for operating a target circuit being generated on the target circuit (e.g. , an on-chip clock).
  • the approach shown in FIG. 2A is directed to a three-mode delay fault test process and may, for example, be implemented in connection with the approach shown in FIG. 1 discussed above and also with the signals and approach discussed further below in connection with FIG. 2B.
  • Different tester states for a circuit tester include an initialization state 200, a shift state 210 (in which a first shift vector is applied), a capture state 215 (during which a high speed clock is applied) and an output state 220 (during which the first shift vector is shifted out and a second shift vector is applied).
  • Two signals 230 and 240 as shown are respectively directed to a test control block (TCB) circuit signal and a phase-locked loop (PLL) signal.
  • the TCB is implemented for analyzing a target circuit (e.g., a circuit board) for delay fault enable (DFE) testing.
  • the PLL signal 240 begins to lock, or synchronize, with the input clock after the rising state-transition (low-to-high) of the TCB signal 230.
  • the line 235 shows a delay between the start and end of locking for the PLL, which is locked before the capture state 215.
  • the output clock from the PLL is then used in the capture state 215 of an output from a circuit being tested, such that the output signal captured is analyzed to a reference (the locked phase) and a change in timing thereof is readily detected.
  • FIG. 2B shows an approach for clocking a target circuit with a high frequency clock while testing the target circuit with a tester having a relatively lower-speed clock, according to another example embodiment of the present invention.
  • JTAG test signals with a tester such as circuit tester 340 shown in FIG. 3 for operating a target circuit such as target circuit 332 of FIG. 3, three test modes are shown including a first shift mode 250, capture mode 260 and a second shift mode 270.
  • Signals shown in FIG. 2B include a test clock signal (TCK) 280 for operating the target circuit, a scan enable signal (SE) 282 for initiating a scan cycle, a high-frequency clock input signal (CLKI) 284 and an output clock signal (CLKO) 286.
  • TCK test clock signal
  • SE scan enable signal
  • CLKI high-frequency clock input signal
  • CLKO output clock signal
  • CLKI 284 may, for example, come from a source separate from the target circuit or from a PLL circuit on the target circuit, for instance, as discussed in connection with FIG. 2A. These signals are applied over time as shown (e.g., with time in the horizontal direction and voltage in the vertical direction of the signals as shown).
  • CLKO 286 is implemented as a function of one or more of TCK 280, SE 282 and CLKI 284 and is applied for operating (clocking) the target circuit. During the shift mode 250, CLKO 286 outputs a signal corresponding to TCK 280 until the capture mode 260 is begun. In one implementation, a verification check is performed to ensure that a PLL has locked, such as discussed in connection with FIG. 2A, prior to entering the capture mode 260.
  • a short capture delay is carried out for about three clock-state transitions of CLKI 284, with CLKO 286 remaining high until the fourth clock-state change of CLKI.
  • CLKI is applied for about two cycles (involving four clock-state change transitions), beginning with a high-to-low transition at time 287 with each two such clock-state transitions having a period (T) shown by period 290.
  • CLKO 286 remains high ("one") for the remainder of the capture mode 260.
  • SE 282 is disabled (goes high) and the second shift mode 270 is entered, wherein CLKO 286 outputs a signal corresponding to TCK 280.
  • a delay characteristic of the output from the target circuit that is a function of the target circuit being clocked with CLKI 286 (during the clock-state transitions beginning at time 287) is detected. If the output from the target circuit shows a delay, for example as compared with a PLL approach as discussed above and in connection with FIG. 2A, a resistive and/or delay-type fault in the target circuit is detected.
  • FIG. 3 shows one such circuit arrangement 300, according to another example embodiment of the present invention.
  • Table 1 discusses various signals and elements as may be implemented in connection with FIG. 3.
  • the circuit 300 is shown having inputs including scan test mode (STM) 302, scan enable (SE) 304, delay fault enable (DFE) 306, test clock (TCK) 308 and a rapid clock CLKI 309.
  • STM scan test mode
  • SE scan enable
  • DFE delay fault enable
  • TCK test clock
  • the output from the circuit 300 is CLKO 330 and is used for the operation of (clocking) a target circuit 332.
  • a circuit tester 340 such as a JTAG tester, is used to provide the inputs STM 302, SE 304, DFE 306 and TCK 308, as well as operational inputs to the target circuit 332.
  • An output of the target circuit 332 is also detected by the circuit tester 340 and used to detect a delay fault in the target circuit.
  • the circuit 300 supports at least four modes of operation, for example, as discussed further below in connection with Table 2.
  • the circuit 300 includes five flip-flop circuits 310, 312, 314, 316 and 318, with flip- flop 310 being clocked by TCK 308 and flip-flops 312, 314, 316 and 318 being clocked by CLKI 309. Each of these flip-flop circuits are not scanned, such that during delay fault scan testing they are exercised as intended (i.e., as discussed below).
  • the circuit 300 further includes logic circuitry, in this instance represented in the form of two-to-one multiplexers 322, 324 and 326 for selecting signals for passing forward to CLKO 330, depending upon the settings of the input signals DFE 306, SE 304 and STM 302, respectively. For example, multiplexer 322 passes TCK 308 unless the DFE 306 is "one," wherein the output from
  • NAND gate 320 is passed forward.
  • Multiplexer 324 passes TCK 308 forward when SE 304 is “one” and passes the output from the multiplexer 322 forward when SE is "zero” (e.g., during the capture mode as shown in FIG. 2B).
  • Multiplexer 326 passes the output from multiplexer 324 in the scan test mode (when STM is “one") and passes CLKI 309 when not in the scan test mode (when STM is "zero”).
  • the flip-flop circuits 310-318 and the NAND gate 320 generate, in connection with SE 304, TCK 308 and CLKI 309, a two-pulse, Return-To-One output.
  • This zero is clocked through the flip-flops 310, 312, 314, 316 and 318, and presented to NAND gate 320 as a "one" (inverted) from flip-flop 318 and as a "zero" from node 315.
  • the NAND gate 320 also receives CLKI 309, which transitions clock states between "one” and "zero.” Since inputs to the NAND gate 320 are not all
  • the output presented to selector circuit 322 is a "one,” for example as shown during the first portion of the capture mode 260 in FIG. 2B.
  • SE 304 goes low (“zero"), for example as shown in connection with SE 282 and capture mode 260 in FIG. 2B, a logical "one” is presented to flip-flop 310 (with SE 304 inverted from “zero” to “one”).
  • the output from the multiplexer 322 is selected at multiplexer 324 and passed forward to multiplexer 326.
  • flip-flop 310 is clocked using TCK 308, the "one" is presented to flip-flop 312, which is clocked by CLKI 309.
  • the inverted output of NAND gate 320 is "one" when CLKI 309 is “one” and “zero” when CLKI is “zero” during the next two clock-state transitions of CLKI as a "one” is passed through flip-flops 316 and 318. Therefore, the output of the NAND gate 320 follows CLKI 309, for example, as shown for period 290 in FIG. 2B.
  • the output from flip-flop 318 becomes “one” and the corresponding inverted signal "zero” is presented at the NAND gate 320.
  • the output from the NAND gate 320 returns to one, as shown by the portion of the CLKI 284 signal after period 290 in FIG. 2B.
  • SE 304 is returned to "one” (e.g., at the end of a capture mode 260 as shown in FIG. 2B)
  • the multiplexer 324 passes TCK 308 forward.
  • Table 2 shows one approach for implementing the circuit 300 shown in FIG. 3, according to a more particular example embodiment of the present invention.
  • multiplexer 326 passes CLKI 309 (the "functional” clock in the above table) to CLKO 330.
  • circuit selector 322 passes TCK 308 to multiplexer 324, which passes TCK because TCK is at both inputs "1" and "0.”
  • STM 302, DFE 306 and SE 304 are all "one,” TCK 308 is passed through to CLKO 330.
  • STM 302 and DFE 306 are “one” and SE 304 is "zero," the two-pulse Return-To- Zero signal from the NAND gate 320 is passed to CLKO 330.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

Cette approche de contrôle implique l'application sélective de signaux d'horloge à des circuits cibles. Dans un mode de réalisation (300) donné à titre d'exemple, un circuit cible (332) avec des circuits logiques qui traitent des données en réponse à un signal d'horloge d'exploitation (308) avec au moins une période d'horloge est analysé afin de détecter des erreurs de retard. Des signaux de contrôle sont appliqués aux circuits logiques pendant qu'ils sont synchronisés au moyen d'une horloge (309) de contrôle à haute vitesse avec plusieurs transitions d'état d'horloge qui surviennent pendant au moins une période d'horloge de l'horloge d'exploitation (308). Une sortie des circuits logiques est analysée pour déterminer son état (par exemple, si elle est affectée par le délai dans les circuits). Les erreurs de retard sont détectées comme une différence dans l'état de la sortie des circuits logiques. Avec cette approche, on teste des circuits en utilisant des testeurs conventionnels (340) qui opèrent à des vitesse normales (par exemple, lentes) en même temps que des parties sélectionnées du circuit sont synchronisées à des vitesses supérieures afin d'y détecter des erreurs associées à la vitesse.
EP04735277A 2003-06-03 2004-05-28 Procede, systeme et circuit de controle d'erreurs de retard Withdrawn EP1634089A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47523903P 2003-06-03 2003-06-03
PCT/IB2004/001750 WO2004106958A1 (fr) 2003-06-03 2004-05-28 Procede, système et circuit de contrôle d'erreurs de retard

Publications (1)

Publication Number Publication Date
EP1634089A1 true EP1634089A1 (fr) 2006-03-15

Family

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EP04735277A Withdrawn EP1634089A1 (fr) 2003-06-03 2004-05-28 Procede, systeme et circuit de controle d'erreurs de retard

Country Status (5)

Country Link
EP (1) EP1634089A1 (fr)
KR (1) KR20060019565A (fr)
CN (1) CN1798980A (fr)
TW (1) TW200508637A (fr)
WO (1) WO2004106958A1 (fr)

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Publication number Priority date Publication date Assignee Title
KR100817236B1 (ko) * 2006-05-08 2008-03-27 엠텍비젼 주식회사 Ｊｔａｇ 컨트롤러를 이용한 지연 결함 테스트 장치 및지연 결함 테스트 방법
US8627160B2 (en) * 2010-04-21 2014-01-07 Lsi Corporation System and device for reducing instantaneous voltage droop during a scan shift operation
CN101852839B (zh) * 2010-05-19 2012-06-27 中国科学院计算技术研究所 老化预测和超速时延测试双功能的系统及方法
GB201514522D0 (en) * 2015-08-14 2015-09-30 Novelda As High precision time measurement apparatus
CN111398775B (zh) * 2019-01-03 2024-02-06 瑞昱半导体股份有限公司 电路运行速度检测电路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6510534B1 (en) * 2000-06-29 2003-01-21 Logicvision, Inc. Method and apparatus for testing high performance circuits
US6763489B2 (en) * 2001-02-02 2004-07-13 Logicvision, Inc. Method for scan testing of digital circuit, digital circuit for use therewith and program product for incorporating test methodology into circuit description
JP4971557B2 (ja) * 2001-07-03 2012-07-11 パナソニック株式会社 半導体集積回路
JP2003043109A (ja) * 2001-07-30 2003-02-13 Nec Corp 半導体集積回路装置及びその試験装置

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* Cited by examiner, † Cited by third party
Title
See references of WO2004106958A1 *

Also Published As

Publication number Publication date
KR20060019565A (ko) 2006-03-03
TW200508637A (en) 2005-03-01
CN1798980A (zh) 2006-07-05
WO2004106958A1 (fr) 2004-12-09

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