EP1630815B1 - Dispositif de memoire a la flexibilite en relation a la tension d'alimentation et avec un rendement adapte a la tension d'alimentation - Google Patents

Dispositif de memoire a la flexibilite en relation a la tension d'alimentation et avec un rendement adapte a la tension d'alimentation Download PDF

Info

Publication number
EP1630815B1
EP1630815B1 EP04020080A EP04020080A EP1630815B1 EP 1630815 B1 EP1630815 B1 EP 1630815B1 EP 04020080 A EP04020080 A EP 04020080A EP 04020080 A EP04020080 A EP 04020080A EP 1630815 B1 EP1630815 B1 EP 1630815B1
Authority
EP
European Patent Office
Prior art keywords
memory
supply voltage
bit line
transistor
memory circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP04020080A
Other languages
German (de)
English (en)
Other versions
EP1630815A1 (fr
Inventor
Jean-Patrice Coste
Christophe Chanussot
Vincent Gouin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to EP04020080A priority Critical patent/EP1630815B1/fr
Priority to US11/212,082 priority patent/US7355915B2/en
Publication of EP1630815A1 publication Critical patent/EP1630815A1/fr
Application granted granted Critical
Publication of EP1630815B1 publication Critical patent/EP1630815B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/065—Sense amplifier drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

Definitions

  • the invention relates to memory circuits, particularly to SRAM circuits.
  • the SRAM-type memory comprises a memory cell array 15 of 1-bit memory cells 1 with m rows and n columns. Each memory cell is based on a flip-flop (typically CMOS-type) as the memory core cell with positive feedback for the storage of the data (not shown).
  • the differential data outputs of the flip-flop are selectively coupled to differential bit lines bl j and bln j by memory cell internal select transistors (not shown), which are driven by a corresponding word line wl i .
  • the bit lines bl j and bln j are usually precharged to a specific voltage level (usually the supply voltage V dd ) by precharging circuits P.
  • Each memory cell 1 is addressed by a row address signal 2 and a column address signal 3 with ld(m)- and ld(n)-bit word-length, respectively.
  • the row address signal 2 is decoded in a row decoder 4 to select one of the m rows.
  • the column address signal 3 is decoded in a column decoder 5 to select one of the n columns.
  • Each row of memory cells is coupled to one word line wl i . In case a row is selected, the corresponding word line wl i exhibits a logically high potential.
  • the selection of a word line is resetable by a signal wl_resetn which resets all word lines to a logically low level in case wl_resetn is high.
  • a signal wl_resetn which resets all word lines to a logically low level in case wl_resetn is high.
  • m AND-gates driving the m word lines, with each AND-gate being connected to one output signal a i of the row decoder and the signal wl_resetn.
  • each of the n output signals of the column decoder 5 is connected to one of n total column switches 6.
  • the corresponding pair of differential bit lines bl j and bln j is connected to the differential pair of data I/O lines 7 via the corresponding column switch 6.
  • the data I/O lines 7 are connected to the differential input sa and san of a sense amplifier 8 and to the differential output of a write buffer 9, respectively.
  • a dynamic sense amplifier 8 is employed, with its operation being controlled by a control signal saen.
  • the signal saen activates the amplifier 8 when switching from low to high.
  • the dynamic sense amplifier 8 is based on an internal positive feedback, which speeds up the signal detection compared to a static sense amplifier.
  • a dynamic sense amplifier 8 also consumes less power compared to a static sense amplifier since it switches to zero power as soon as it has made a decision.
  • the operation of the write buffer 9 is controlled by a control signal irwb which activates or deactivates the driving of the I/O data lines 7 and the therewith connected bit lines bl j and bln j , when switching from low to high level or from high to low level, respectively.
  • Fig. 2 illustrates the SRAM-internal timing during a memory read access.
  • the transient voltage curves 10 and 11 are related to the differential inputs sa and san of the sense amplifier 8, whereas the transient voltage curve 12 relates to the control signal saen for sense amplifier activation.
  • the inputs sa and san and the connected bit lines bl j and bln j are still precharged to V dd , with V dd being the positive supply voltage.
  • the recharge of the inputs sa and san with respect to the memory cell internal voltages is delayed because of parasitic capacitances (mainly parasitic capacitances of the bit lines bl j and bln j ).
  • the sense amplifier 8 is activated when the control signal saen switches from low to high.
  • the differential voltage between the signals sa and san at the time instant t a is defined as the read margin ⁇ sa.
  • the earlier the sense amplifier 8 is activated the smaller ⁇ sa is and the faster the read operation is. But the smaller ⁇ sa is, the more critical the detection of the signal is that is read out of the memory cell. Since the recharging capability of a selected memory cell 1 may vary from memory circuit to memory circuit as well as from memory cell to memory cell and in addition the detection capability of a sense amplifier 8 may vary from memory circuit to memory circuit, the read margin ⁇ sa needs to be set as large as necessary to guarantee safe operation.
  • the wordline wl i is deactivated by switching the signal wl_resetn (cf. Fig. 1 ) from high to low (not shown).
  • Fig. 3 illustrates the SRAM-internal timing during a memory write access.
  • the transient voltage curves 20 and 21 are related to the signal on the selected word line wl i and the signal irwb which controls the operation of the write buffer 9, respectively.
  • the transient voltage curves 22 and 23 relate to differential internal voltage levels c and cn of the flip-flop in the selected memory cell.
  • the transient voltage curves 24 and 25 relate to the voltage levels on the differential bit line bl j and bln j .
  • the signal irwb is switched from low to high to activate the write buffer 9.
  • a recharge of the bit lines bl j and bln j and the internal voltages c and cn of the selected flip-flop according to the data input signal of the write buffer 9 is initiated.
  • the write buffer 9 is deactivated by switching the signal irwb from high to low.
  • the word line wl i has to be maintained activated during the commutation of the flip-flop. Afterwards the wordline wl i is deactivated by switching the signal wl_resetn (cf. Fig.
  • the write margin ⁇ t is defined time-based.
  • the write margin ⁇ t is defined by the time window which is described by the time instance t 1 when the flip-flop-internal node-voltage cn crosses V dd /2 and the time instance t 2 when the falling edge of the voltage on the word line wl i crosses V dd /2 (word line deactivation).
  • the document US 5,936,905 describes a self-adjusting delay circuit in an SRAM circuit.
  • the delay circuit relates only to read access and adjusts the internal timing with respect to the activation of a dynamic sense amplifier.
  • the delay circuit comprises a dummy word line which replicates a corresponding word line and is connected to a number n of parallel dummy transistors.
  • the number n of parallel dummy transistors is the same than the number of transistors connected to the corresponding word line.
  • a subset m of these n dummy transistors drives a dummy bit line which replicates a corresponding bit line.
  • the activation signal related to the dynamic sense amplifier is derived from the voltage level on the dummy bit line.
  • the delay of the delay circuit is programmable by setting the number of transistors m driving the dummy bit line.
  • state-of-the-art memory circuits are only operational within a small range of the nominal supply voltage.
  • the read margin ⁇ sa and the write margin ⁇ t might be toolow and the operation of the memory circuit might fail.
  • the supply voltage should be variable. By reducing the supply voltage the memory circuit could work in a low power mode with lower speed.
  • the US patent application US 2003/0042955 A1 discloses in Figs. 6 and 7 a memory circuit comprising a plurality of memory cells organised in rows and columns, a memory access mean, which is controlled by at least one control signal, and a control mean for generating the at least one control signal comprising a delay mean, which delays a switching of the at least one control signal, with the respective delay time being adjustable in view of the applied supply voltage.
  • the US patents US 5,132,932 A and US 6,462,998 B1 disclose further features of memory circuits.
  • the document EP 1 033 721 A2 discloses a delay adjust circuitry 40 in Fig. 3 comprising delay elements 100 to 103, which may be activated by binary signals 122 to 125.
  • the binary signals 122 to 125 are provided by a fuse circuitry 24, the fuses of which are blown before the operation of the memory circuit.
  • the inventive memory circuit according to claim 1 comprises a plurality of memory cells, which are organised in rows and columns.
  • the memory circuit further comprises a memory access means, which is controlled by at least one control signal.
  • a control means for generating the at least one control signal is contained in the inventive memory circuit, with the control means comprising a delay means.
  • the delay means delays a switching of the at least one control signal.
  • the respective delay time is adjustable in view of the applied supply voltage.
  • the delay time being adjustable in view of the supply voltage is employed to counteract the dependency of the characteristics of the memory circuit on the applied supply voltage.
  • the circuit-internal signal detection capability is reduced with decreasing supply voltage.
  • a sense amplifier being part of the memory access means needs a larger voltage swing for signal detection, which is equivalent to a larger read margin.
  • a selected flip-flop in a memory cell demands a higher voltage swing before deactivating the write buffer and the selected word line, which results in a demand to increase the write margin.
  • both, the read and the write margin should be increased when reducing the supply voltage, thereby reducing the operating speed of the memory circuit.
  • the read and write margins have to be increased with decreasing supply voltage because of the increasing impact of the threshold-voltage mismatch and other mismatches in the memory core cells, i. e. in the flip-flops.
  • the supply voltage is reduced, the signal swing is also reduced (e.g. in CMOS circuits). This results in a decreased signal-to-noise-ratio (the threshold-voltage variance can be regarded as noise).
  • the inventive memory circuit provides the capability to adapt those margins to the actual applied supply voltage by adjusting the timing for the at least one control signal, e.g. an activation signal for a dynamic sense amplifier. Therefore the inventive memory circuit guarantees safe operation even for low supply voltages.
  • the memory circuit may be applied to a low supply voltage resulting in low power consumption and low operating speed in case the operating speed is not crucial.
  • the memory circuit may be applied to a high supply voltage in case the maximum operating speed is required.
  • claim 1 does not necessarily imply that every control signal of the data access unit is deduced from the delay unit.
  • claim 1 does not imply that the delay time is constant in case more than one control signals are deduced for the delay unit.
  • the scope of this invention may also comprise an implementation with different adjustable delay times assigned to different control signals.
  • the memory access means supports a memory read access mode and a memory write access mode and the delay time is independently selectable for the memory read access mode and for the memory write access mode.
  • This provides a further degree of freedom since the delay time is not only adjustable with respect to supply voltage but also with respect to read or write mode.
  • This added adjustability with respect to read or write mode is based on the recognition that the supply voltage driven impact on the memory characteristics, particularly the timing characteristics, may be different for read and write access. Therefore, the timing of the at least one control signal in the advantageous memory circuit may be independently optimised for read and write access.
  • the inventive memory circuit comprises a plurality of bit lines each coupled to a column of the plurality of memory cells.
  • the delay means comprises a dummy bit line, the signal transmission behaviour of which is essentially characteristic of the signal transmission behaviour of each of the bit lines.
  • the dummy bit line is particularly coupled to dummy memory cells which replicate the load of a bit line, i.e. the plurality of memory cells assigned to a bit line.
  • the at least one control signal is generated in dependency of the signal, particularly the voltage signal, on the dummy bit line.
  • the delay means further comprises a driver unit which drives the dummy bit line, particularly discharges the dummy bit line.
  • the preferred memory circuit is based on the idea that an apriori unknown delay variation for accessing a memory cell via a capacitive bit line transfers to a more or less identical delay variation with respect to the delay of the dummy bit line in case the bit line and the dummy bit line are matched to each other (considering the load and the driving circuit of both lines are matched).
  • Matching between the bit line and the dummy bit line means that the main characteristic structure features of both transmission lines which impacts the line capacitance and the propagation delay of the transmission line are identical, e.g. same length, same width, same thickness and same dielectricity of the isolation. In case the delay for reading the content of a memory cell via a bit line is increased, e.g.
  • the activation of a sense amplifier by the control signal is also delayed by the same additional delay. This leads to a self-adjusting timing architecture. In case the number of dummy memory cells which are connected to the dummy bit line and the number of the memory cells which are connected to the selected bit line are the same, the delay matching is improved.
  • a bit line is commonly implemented as a differential bit line with two metal lines.
  • the dummy bit line may be implemented as a differential dummy bit line or only as a single bit line with one metal line.
  • the driving capability of the driver unit is adjustable. Driving capability means the capability of the driver unit to recharge the load of the driver unit. The higher the driving capability is, the faster the recharge process is. Thus, the driving capability is equivalent to the current driving capability.
  • the driving capability of a driver circuit is determined by the parasitic elements of its equivalent circuit. In general, the larger the transistor area of a driving transistor is, the higher the driving capability is. According to the term transistor, it should be noted that throughout the whole application a transistor might comprise several parallel smaller transistors.
  • the driver unit advantageously comprises a plurality of driver transistors coupled to the dummy bit line, with the total transistor area or size of the one or those driver transistors which are actively driving the bit line is selectable. By altering the total transistor area of the active driving transistors, the driving capability of the driver unit is adjusted. This can be easily accomplished by switching on one or more transistors of the transistor bank, while switching off the remaining transistors of the transistor bank.
  • the driving capability of the driver unit is independently selectable for at least two different supply voltage operating modes of the memory circuit: a high supply voltage mode (e.g. 1.8 V nominal supply voltage) and a low supply voltage mode (e.g. 1.2 V nominal supply voltage).
  • a high supply voltage mode e.g. 1.8 V nominal supply voltage
  • a low supply voltage mode e.g. 1.2 V nominal supply voltage
  • the driving capability for the high supply voltage mode is higher than the driving capability for the low supply voltage mode, particularly the area of the actively driving transistors is higher for the high supply voltage mode compared to the low supply voltage mode.
  • the voltage potential of at least one first pin selects the driving capability.
  • the above-mentioned technical teaching is based on the idea that for high reliability of the memory circuit the timing margins must be increased when the memory circuit is operated in a low supply voltage mode (e.g. 1.2 V) compared to an operation in a high supply voltage mode (e.g. 1.8 V).
  • a low supply voltage mode e.g. 1.2 V
  • a high supply voltage mode e.g. 1.8 V
  • the driving capability is set to low, which results in a higher delay time for discharging the dummy bit line.
  • This increases the read margin ⁇ sa and/or the write margin ⁇ t of the memory circuit (cf. Fig. 2 and Fig.
  • the sense amplifier activation signal saen and/or the write buffer activation signal irwb and the word line deactivation signal wl_resetn (cf. Fig. 1 ) are derived from the signal on the dummy bit line, respectively.
  • the increased read margin ⁇ sa and/or the write margin ⁇ t reduces the memory operating speed.
  • the low supply voltage mode is equivalent to a low operating speed mode and the high supply voltage mode is equivalent to a high operating speed mode.
  • the driver unit advantageously comprises at least two MOS-type (metal oxide semiconductor) driver transistors: A first MOS driver transistor actively drives the dummy bit line in the low supply voltage mode, whereas a second MOS driver transistor (which may comprise several parallel smaller MOS transistors) actively drives the dummy bit line in the high supply voltage mode.
  • the transistor width of the second driver transistor is essentially i times higher than the transistor width of the first driver transistor, with i > 1.
  • i is a natural number.
  • the second transistor advantageously consists of i parallel transistors which are identical to the first MOS driver transistor (transistor matching).
  • MOS transistor is assigned to the high or low supply voltage operation.
  • scope of the invention also includes that two or more MOS transistors are assigned to high or low supply voltage mode.
  • the first MOS transistor is not necessarily switched off in the high supply voltage mode. This is due to the fact that the impact of the first MOS transistor on the driving capability of the driver unit in the high supply voltage mode is negligible (due to its small transistor area).
  • the driving capability of the driver unit is independently selectable for the memory read access mode and for the memory write access mode. This is based on the idea that the optimal delay for switching a control signal during read access (e.g. the signal saen) for a fixed supply voltage is different from the optimal delay for switching a control signal during write access for the same fixed supply voltage (e.g. the signal irwb).
  • the selection is done via a second pin.
  • the driver unit comprises at least four MOS driver transistors:
  • the transistor width of the second driver transistor is essentially i times higher than the transistor width of the first driver transistor, with i > 1.
  • the transistor width of the fourth driver transistor is essentially n times higher than the transistor width of the third driver transistor, with n > 1.
  • the factors i and/or n are natural numbers. In this case, the corresponding transistors may be matched to each other (see transistor matching above).
  • the first and/or the third MOS transistor are not necessarily switched off in high supply voltage mode.
  • the number of MOS driver transistors is necessarily not limited to four.
  • the memory access means comprises a sense amplifier for memory read access, particularly a dynamic sense amplifier.
  • the sense amplifier e.g. sense amplifier 8 in Fig. 1
  • the sense amplifier is selectively coupled to one of the plurality of bit lines and receiving data transmitted via the coupled bit line from one of the memory cells.
  • the sense amplifier is activated by a first control signal, e.g. the signal saen in Fig. 1 , which is delayed by the delay means, i.e. generated in dependence of the signal on the dummy bit line.
  • the memory access means may comprise a write buffer (e.g. write buffer 9 in Fig.
  • the write buffer is activated and deactivated by a second said control signal, e.g. the signal irwb in Fig. 1 , which is delayed by the delay means, i.e. generated in dependence of the signal on the dummy bit line.
  • the memory access means may also comprise a word line selection means, which selects one row of the plurality of memory cells for memory access.
  • the selection of the word line selection means is deactivated by a third control signal, e.g. the signal wl_resetn in Fig. 1 , which is delayed by the delay means, i.e. generated in dependence of the signal on the dummy bit line.
  • the inventive memory circuit is implemented as an SRAM circuit.
  • the scope of invention may also include other memory circuits, e.g. DRAM (dynamic random access memory) circuits, ROM (read-only memory) circuits or PROM (programmable read-only memory) circuits, particularly flash-type EEPROM (electrical erasable and programmable read-only memory) circuits.
  • DRAM dynamic random access memory
  • ROM read-only memory
  • PROM programmable read-only memory
  • flash-type EEPROM electrical erasable and programmable read-only memory
  • Fig. 4 illustrates an exemplary embodiment of the inventive memory circuit.
  • the memory circuit in Fig. 4 is an SRAM circuit which is based on the SRAM circuit in Fig. 1 .
  • Signals and circuit components of Fig.1 and Fig. 4 which are related to the same reference signs are the same. Above-given statements with respect to Fig. 1 (and to the internal signals in Fig. 2 and Fig. 3 ) are also valid with respect to Fig. 4 .
  • the main difference between the circuits in Fig. 1 and in Fig. 4 is the generation of the three control signals wl_resetn (word line deactivation), irwb (activation of write buffer 9) and saen (activation of read buffer 8).
  • the inventive SRAM circuit according to Fig. 4 comprises a control circuit block 30 for generating the three control signals wl_resetn, irwb and saen.
  • the circuit block 30 comprises a dummy bit line, a plurality 33 of dummy memory cells 9' connected to the dummy bit line 32 and a driver unit 31, which recharges the dummy bit line 32.
  • the output of the dummy bit line 32 is connected to a logical circuit 41, which generates the three control signals wl_resetn, irwb and saen in dependence of the signal on the dummy bit line 32.
  • the control circuit block 30 is driven by a dummy word line signal 34.
  • the corresponding transmission line of the signal 34 may be designed similar or identical to one of the word lines wl i to generate a similar line capacitance and therewith a similar propagation delay.
  • the dummy word line signal 34 is synchronised to the signal which generates the word line decoding.
  • the dummy word line signal 34 is received by the driver unit 31, particularly by the gates of the four NMOS driver transistors 36a - 39a, with their drains connected to the dummy bit line 32, and in parallel by a precharge PMOS transistor 35.
  • the transistor width of the transistor 36a for write access and high supply voltage mode is n times higher than the transistor width w 1 of the transistor 37a for write access and low supply voltage mode. Additionally, the transistor width of the transistor 38a for read access and high supply voltage mode is i times higher than the transistor width w 3 of the transistor 39a for read access and low supply voltage mode.
  • the larger the width of the selected driver transistor 36a - 39a is, the faster the dummy bit line 32 is discharged. For the high supply voltage mode or for high-speed operation the larger driver transistors 36a or 38a are selected, whereas for the low supply voltage mode or for low speed operation the smaller driver transistors 37a or 39a are selected.
  • each NMOS driver transistor 36a - 39a For the selective activation of one of the four NMOS driver transistors 36a - 39a the source of each NMOS driver transistor 36a - 39a is connected to the drain of a corresponding NMOS select transistor 36b - 39b.
  • the ratio of the widths of each two select transistors 36b - 39b is identical to the ratio of widths of the corresponding driver transistors 36a - 39a.
  • the select transistor 36b- 39b is switched on or off. In case the select transistor 36b - 39b is off, the corresponding driver transistor 36a - 39a is also switched off (independent from the signal 34).
  • the gates of the select transistors 36b - 39b are connected via the logical circuit 40 to the pins slowb and rwb.
  • the logical circuit is designed such that in dependence of the potential slowb and rwb only one of the four select transistors 36b - 39b and therefore only one of the four driver transistors 36a - 39a is selected.
  • a precharge PMOS transistor 35 is active, which precharges the dummy bit line 32 connected to the drain of the PMOS transistor 35 to the supply voltage V dd .
  • the selected (via the pins slowb and rwb) NMOS driver transistor 36a - 39a is activated.
  • the activated driver transistor 36a - 39a discharges the dummy bit line 32 resulting in a logically low potential.
  • the time for discharging the dummy bit line 32 from high to low depends on the width of the selected driver transistor 36a - 39a, the total capacitance of the dummy bit line 32 and the load of the dummy bit line, mainly the plurality 33 of dummy memory cells 9'.
  • the delay time for discharging differs from read operation to write operation and different from high supply voltage mode to low supply voltage mode.
  • the potential of the signal on the dummy bit line 32 and the potential of the pin rwb determines the potential of the control signals irwb, saen and wl_resetn by means of the logical circuit 41.
  • the NAND-gates and inverters of the logical circuit 41 are arranged in such a manner that in case the dummy bit lines 32 is discharged, i.e. the potential of the dummy bit line 32 switches from high to low,
  • the signal saen switches from low to high (at the time instant t a in Fig. 2 ), which activates the sense amplifier 8. Additionally, the selected word line wl i is deactivated, since the signal wl_reset switches from high to low.
  • the selection of the driver transistor 36a - 39a determines the time for discharging the dummy bit line 32 and therewith determines the read margin ⁇ sa (cf. Fig. 2 ). The smaller the width of the selected driver transistor 36a - 39a, the slower the dummy bit line 32 is discharged and the larger the read margin ⁇ sa is.
  • the write buffer 9 is already activated (cf. Fig. 3 ) prior to the discharge of the dummy bit line 32.
  • the signal irwb switches from high to low (cf. Fig. 3 ) stopping the operation of the write buffer 9.
  • the selected word line wl i is deactivated since the signal wl_reset switches from high to low.
  • the selection of the driver transistor 36a - 39a determines the time for discharging the dummy bit line 32 and therewith determines the write margin ⁇ t (cf. Fig. 3 ). The smaller the width of the selected driver transistor 36a - 39a, the slower the dummy bit line 32 is discharged and the larger the write margin ⁇ t is.
  • the operating speed of the circuit is decreased.
  • an adjustable delay in view of two or more different supported supply voltage modes might also be employed in view of two or more different selectable operating speed modes of the memory circuit, with each speed mode being operated at a different supply voltage.

Landscapes

  • Static Random-Access Memory (AREA)

Claims (11)

  1. Circuit de mémoire, comprenant :
    - une pluralité (15) de cellules (1) de mémoire organisées en rangées et en colonnes,
    - un moyen d'accès à la mémoire, qui est commandé par au moins un signal (wl_resetn, irwb, saen) de commande, et
    - un moyen (20) de commande pour produire le au moins un signal (wl_resetn, irwb, saen) de commande, comprenant :
    - - un moyen (31, 32, 33) de temporisation, qui retarde une commutation du au moins un signal (wl_resetn, irwb, saen) de commande,
    dans lequel le retard respectif du moyen (31, 32, 33) de temporisation est réglable pendant un fonctionnement du circuit de mémoire au vu de la tension (Vdd) d'alimentation appliquée,
    dans lequel le moyen d'accès à la mémoire supporte un mode d'accès à la mémoire en lecture et un mode d'accès à la mémoire en écriture,
    caractérisé en ce que
    - le retard peut être choisi indépendamment pour le mode d'accès à la mémoire en lecture et pour le mode d'accès à la mémoire en écriture.
  2. Circuit de mémoire suivant la revendication 1,
    caractérisé en ce que
    - le circuit de mémoire comprend :
    - - une pluralité de lignes (blj, blnj) de binaire couplées chacune à une colonne de la pluralité (15) de cellules (1) de mémoire, et
    - le moyen de temporisation comprend :
    - - une ligne (32) fictive de binaire - couplée en particulier à des cellules (9') fictives de mémoire - dont le comportement de transmission du signal est essentiellement caractéristique du comportement de transmission du signal des lignes (blj, blnj) de binaire, le au moins un signal (wl_resetn, irwb, saen) de commande étant produit en fonction du signal sur la ligne (32) fictive de binaire, et
    - - une unité (31) d'attaque attaquant la ligne (32) fictive de binaire, en particulier pour décharger la ligne (32) fictive de binaire.
  3. Circuit de mémoire suivant la revendication 2,
    caractérisé en ce que
    la capacité d'attaque de l'unité (31) d'attaque est réglable.
  4. Circuit de mémoire suivant la revendication 3,
    caractérisé en ce que
    l'unité (31) d'attaque comprend une pluralité de transistors (36a à 39a) d'attaque couplés à la ligne (32) fictive de binaire, la surface ou la dimension totale des transistors de l'un ou de ces transistors d'attaque, qui attaquent activement la ligne (32) de binaire, pouvant être sélectionnée.
  5. Circuit de mémoire suivant l'une quelconque des revendications 3 ou 4,
    caractérisé en ce que
    la capacité d'attaque de l'unité (31) d'attaque peut être sélectionnée indépendamment pour au moins deux modes de fonctionnement différents de tension d'alimentation du circuit de mémoire, un mode de haute tension d'alimentation et un mode de basse tension d'alimentation, par l'intermédiaire d'au moins une première broche (slowb), en particulier la capacité d'entraînement pour le mode d'alimentation en haute tension étant plus grande que la capacité d'entraînement pour le mode d'alimentation en basse tension.
  6. Circuit de mémoire suivant la revendication 5,
    caractérisé en ce que
    l'unité d'attaque comprend au moins deux transistors d'attaque MOS,
    - un premier transistor (37a ; 39a) d'attaque MOS attaquant activement la ligne (32) fictive de binaire, dans le cas du mode de tension d'alimentation basse,
    - un deuxième transistor (36a ; 38a) d'attaque.MOS attaquant activement la ligne (32) fictive de binaire, dans le cas du mode de tension d'alimentation haute,
    la largeur du deuxième transistor d'entraînement étant sensiblement i fois plus grande que la largeur (w1 ; w3) du premier transistor d'entraînement, avec i > 1, i étant en particulier un nombre naturel.
  7. Circuit de mémoire suivant l'une quelconque des revendications 3 à 6,
    caractérisé en ce que
    la capacité d'entraînement de l'unité (31) d'entraînement peut être sélectionnée, indépendamment pour le mode d'accès à la mémoire en lecture et pour le mode d'accès à la mémoire en écriture, par l'intermédiaire d'une deuxième broche (rwb).
  8. Circuit de mémoire suivant la revendication 7,
    caractérisé en ce que
    l'unité (31) d'entraînement comprend au moins quatre transistors (36a à 39a) d'entraînement MOS,
    - un premier transistor (39a) d'entraînement MOS attaquant activement la ligne (32) fictive de binaire, dans le cas du mode d'accès à la mémoire en lecture et du mode d'alimentation en tension basse,
    - un deuxième transistor (38a) d'attaque MOS attaquant activement la ligne (32) fictive de binaire, dans le cas du mode d'accès à la mémoire en lecture et du mode d'alimentation en tension haute,
    - un troisième transistor (37a) d'entraînement MOS attaquant activement la ligne (32) fictive de binaire, dans le cas du mode d'accès à la mémoire en écriture et du mode d'alimentation en tension basse,
    - un quatrième transistor (36a) d'attaque MOS attaquant activement la ligne (32) fictive de binaire, dans le cas du mode d'accès à la mémoire en écriture et du mode d'alimentation en tension haute,
    la largeur du deuxième transistor (38a) d'attaque étant sensiblement i fois plus grande que la largeur (w3) du premier transistor (39a) d'attaque, avec i > 1, i étant en particulier un nombre naturel, et
    la largeur du quatrième transistor (36a) d'attaque étant sensiblement n fois plus grande que la largeur (w1) du troisième transistor (37a) d'attaque, avec n > 1, n étant en particulier un nombre naturel,
  9. Circuit de mémoire suivant l'une quelconque des revendications 2 à 8,
    caractérisé en ce que
    - le moyen d'accès à la mémoire comprend :
    - - un amplificateur (8) de lecture pour l'accès à la mémoire en lecture, en particulier un amplificateur dynamique de lecture étant couplé sélectivement à l'une de la pluralité de lignes (blj, blnj) de binaire et recevant des données transmises par l'intermédiaire de la ligne (blj, blnj) de binaire couplée de l'une des cellules (1) de mémoire et étant activé par un premier du au moins un signal (saen) de commande, et
    - - un tampon (9) d'écriture pour l'accès à la mémoire en écriture étant couplé sélectivement à l'une de la pluralité des lignes (blj, blnj) de binaire et transmettant des données par l'intermédiaire de la ligne (blj, blnj) de binaire couplée à l'une des cellules (1) de mémoire et étant désactivé par un deuxième du au moins un signal (irwb) de commande.
  10. Circuit de mémoire suivant l'une quelconque des revendications 1 à 9,
    caractérisé en ce que
    - le circuit de mémoire comprend
    - - une pluralité de lignes (wli) de mots couplées chacune à une rangée de la pluralité (15) de cellules (1) de mémoire, et
    - le moyen d'accès à la mémoire comprend
    - - un moyen de sélection de lignes de mots sélectionnant une rangée de la pluralité de cellules de mémoire pour un accès à la mémoire dont la sélection est désactivée par un troisième du au moins un signal (wl_resetn) de commande.
  11. Circuit de mémoire suivant l'une quelconque des revendications précédentes,
    caractérisé en ce que
    le circuit de mémoire est un circuit SRAM.
EP04020080A 2004-08-24 2004-08-24 Dispositif de memoire a la flexibilite en relation a la tension d'alimentation et avec un rendement adapte a la tension d'alimentation Active EP1630815B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP04020080A EP1630815B1 (fr) 2004-08-24 2004-08-24 Dispositif de memoire a la flexibilite en relation a la tension d'alimentation et avec un rendement adapte a la tension d'alimentation
US11/212,082 US7355915B2 (en) 2004-08-24 2005-08-24 Memory circuit with supply voltage flexibility and supply voltage adapted performance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04020080A EP1630815B1 (fr) 2004-08-24 2004-08-24 Dispositif de memoire a la flexibilite en relation a la tension d'alimentation et avec un rendement adapte a la tension d'alimentation

Publications (2)

Publication Number Publication Date
EP1630815A1 EP1630815A1 (fr) 2006-03-01
EP1630815B1 true EP1630815B1 (fr) 2011-10-05

Family

ID=34926282

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04020080A Active EP1630815B1 (fr) 2004-08-24 2004-08-24 Dispositif de memoire a la flexibilite en relation a la tension d'alimentation et avec un rendement adapte a la tension d'alimentation

Country Status (2)

Country Link
US (1) US7355915B2 (fr)
EP (1) EP1630815B1 (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100641704B1 (ko) * 2004-10-30 2006-11-03 주식회사 하이닉스반도체 반도체 메모리 소자 및 그 비트라인 센스앰프 옵셋전압측정방법
DE102006023934B3 (de) * 2006-05-19 2007-11-15 Atmel Germany Gmbh Speichervorrichtung mit einer nicht-flüchtigen Speichermatrix
US7746716B2 (en) * 2007-02-22 2010-06-29 Freescale Semiconductor, Inc. Memory having a dummy bitline for timing control
US7646658B2 (en) * 2007-05-31 2010-01-12 Qualcomm Incorporated Memory device with delay tracking for improved timing margin
US7881147B2 (en) 2007-05-31 2011-02-01 Qualcomm Incorporated Clock and control signal generation for high performance memory devices
JP2012128895A (ja) * 2010-12-13 2012-07-05 Toshiba Corp 半導体記憶装置
US8659958B2 (en) * 2011-06-22 2014-02-25 Mediatek Inc. Memory device and related control method
US9013949B2 (en) * 2011-12-19 2015-04-21 Advanced Micro Devices, Inc. Memory access control system and method
US9076557B2 (en) * 2012-11-19 2015-07-07 Texas Instruments Incorporated Read margin measurement in a read-only memory
US9865316B2 (en) 2016-01-21 2018-01-09 Qualcomm Incorporated Memory with a word line assertion delayed by a bit line discharge for write operations with improved write time and reduced write power
US9817601B1 (en) * 2016-07-07 2017-11-14 Nxp Usa, Inc. Method and apparatus for determining feasibility of memory operating condition change using different back bias voltages
CN108010554B (zh) * 2016-10-27 2020-09-29 华为技术有限公司 一种数据访问系统、数据写入方法及数据读取方法
CN112041825A (zh) * 2018-05-02 2020-12-04 株式会社半导体能源研究所 半导体装置
KR20200079808A (ko) * 2018-12-26 2020-07-06 에스케이하이닉스 주식회사 집적 회로 및 메모리
US11694745B1 (en) 2019-10-18 2023-07-04 Gigajot Technology, Inc. SRAM with small-footprint low bit-error-rate readout

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1033721A2 (fr) * 1999-03-01 2000-09-06 Motorola Inc. Contrôle d'un circuit de retard programmable dans une mémoire

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2614514B2 (ja) * 1989-05-19 1997-05-28 三菱電機株式会社 ダイナミック・ランダム・アクセス・メモリ
US5596539A (en) * 1995-12-28 1997-01-21 Lsi Logic Corporation Method and apparatus for a low power self-timed memory control system
US5936905A (en) * 1996-09-03 1999-08-10 Townsend And Townsend And Crew Llp Self adjusting delay circuit and method for compensating sense amplifier clock timing
US6462998B1 (en) * 1999-02-13 2002-10-08 Integrated Device Technology, Inc. Programmable and electrically configurable latch timing circuit
JP2002216481A (ja) * 2001-01-19 2002-08-02 Hitachi Ltd 半導体集積回路装置
JP4339532B2 (ja) * 2001-07-25 2009-10-07 富士通マイクロエレクトロニクス株式会社 セルフタイミング回路を有するスタティックメモリ
JP3908493B2 (ja) * 2001-08-30 2007-04-25 株式会社東芝 電子回路及び半導体記憶装置
JP4152668B2 (ja) * 2002-04-30 2008-09-17 株式会社ルネサステクノロジ 半導体記憶装置
JP4439167B2 (ja) * 2002-08-30 2010-03-24 株式会社ルネサステクノロジ 半導体記憶装置
US6831853B2 (en) * 2002-11-19 2004-12-14 Taiwan Semiconductor Manufacturing Company Apparatus for cleaning a substrate
JP4090967B2 (ja) * 2003-08-29 2008-05-28 松下電器産業株式会社 半導体記憶装置
JP4517786B2 (ja) * 2004-09-06 2010-08-04 富士通セミコンダクター株式会社 半導体記憶装置及びセンスアンプの活性化信号の生成方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1033721A2 (fr) * 1999-03-01 2000-09-06 Motorola Inc. Contrôle d'un circuit de retard programmable dans une mémoire

Also Published As

Publication number Publication date
EP1630815A1 (fr) 2006-03-01
US7355915B2 (en) 2008-04-08
US20060050572A1 (en) 2006-03-09

Similar Documents

Publication Publication Date Title
US7355915B2 (en) Memory circuit with supply voltage flexibility and supply voltage adapted performance
US7215587B2 (en) Tracking circuit for a memory device
KR100546415B1 (ko) 메모리 장치의 파워 노이즈를 방지하는 직렬 웨이크 업 회로
US7466604B2 (en) SRAM voltage control for improved operational margins
EP2362398B1 (fr) SRAM avec tensions d'alimentations multiples pour les cellules de mémoire et la logique d'accès
JP3348432B2 (ja) 半導体装置および半導体記憶装置
US6556471B2 (en) VDD modulated SRAM for highly scaled, high performance cache
Otsuka et al. Circuit techniques for 1.5-V power supply flash memory
US6646938B2 (en) Static memory having self-timing circuit
KR100487098B1 (ko) 센스증폭기타이밍회로
US20080151653A1 (en) Semiconductor memory device
US20090059706A1 (en) Sram active write assist method for improved operational margins
US20030206448A1 (en) Sense amplifier enable signal generating circuits having process tracking capability and semiconductor memory devices including the same
US7403442B2 (en) Pulse controlled word line driver
US8456939B2 (en) Voltage regulation circuitry
US6999367B2 (en) Semiconductor memory device
US20040246799A1 (en) Memory devices having bit line precharge circuits with off current precharge control and associated bit line precharge methods
US8081502B1 (en) Memory elements with body bias control
US5576641A (en) Output buffer
US8854902B2 (en) Write self timing circuitry for self-timed memory
US20090067265A1 (en) Semiconductor storage device
KR20070101243A (ko) 고속 및 저전력 에스램 매크로 구조 및 방법
US7054211B2 (en) Semiconductor memory storage device capable of high operating speed
US8320201B2 (en) Method of reading memory cell
Arandilla et al. Comparison of replica bitline technique and chain delay technique as read timing control for low-power asynchronous SRAM

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL HR LT LV MK

17P Request for examination filed

Effective date: 20060801

17Q First examination report despatched

Effective date: 20060922

AKX Designation fees paid

Designated state(s): DE FR GB

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INFINEON TECHNOLOGIES AG

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

RTI1 Title (correction)

Free format text: MEMORY CIRCUIT WITH SUPPLY VOLTAGE FLEXIBILITY AND SUPPLY VOLTAGE ADAPTED PERFORMANCE

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602004034623

Country of ref document: DE

Effective date: 20120105

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20120706

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602004034623

Country of ref document: DE

Effective date: 20120706

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 13

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 14

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20220822

Year of fee payment: 19

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20220823

Year of fee payment: 19

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20221021

Year of fee payment: 19

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 602004034623

Country of ref document: DE

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20230824