EP1588417A2 - Procede pour produire des lignes de binaires destinees a des memoires flash ucp - Google Patents

Procede pour produire des lignes de binaires destinees a des memoires flash ucp

Info

Publication number
EP1588417A2
EP1588417A2 EP04702285A EP04702285A EP1588417A2 EP 1588417 A2 EP1588417 A2 EP 1588417A2 EP 04702285 A EP04702285 A EP 04702285A EP 04702285 A EP04702285 A EP 04702285A EP 1588417 A2 EP1588417 A2 EP 1588417A2
Authority
EP
European Patent Office
Prior art keywords
floating gate
trench
insulation
bit line
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04702285A
Other languages
German (de)
English (en)
Inventor
Achim Gratz
Veronika Polei
Mark Röhrich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ROEHRICH, MAYK
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1588417A2 publication Critical patent/EP1588417A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Definitions

  • the invention relates to a method for producing bit lines for UCP flash memories with a floating gate arrangement arranged on a substrate and an insulation underneath the floating gate arrangement, the floating gate initially being etched over the entire surface after the previous photolithography by etching deposited poly-silicon layer is produced.
  • the grid dimension is usually designed to be minimal, according to the state of the art.
  • the current concepts for UCP memories therefore use particularly aggressive metal design rules in order to make cell sizes as small as possible.
  • a substantial reduction in the cell size can only be achieved if one of the two bit lines can be buried, ie essentially underneath the substrate surface.
  • Such a buried bit line must meet further requirements with regard to its resistive and capacitive coating and must not significantly increase the manufacturing costs.
  • the conductive material used for the buried bit line must survive the temperature budget of the subsequent processes without damage.
  • the invention is therefore based on the object of providing a method for producing bit lines for UCP flash memories, with which a reduction in cell size is achieved, the production costs are insignificantly influenced and the bit line survives the temperature budget of the subsequent processes without damage.
  • bit line is arranged in a self-aligned manner as a buried bit line made of a temperature-resistant material in a silicon substrate or within the insulation of the active regions under the floating gate.
  • a trench is etched into the insulation, which is then filled with a low-resistance material.
  • the solution according to the invention has the advantage that no additional photolithographic steps have to be carried out, as a result of which the additional process costs for producing the buried bit line are minimized.
  • the self-adjustment of the buried bit line to the floating gate means that No further tolerance buffers are necessary to ensure minimum distances and there are extremely stable conditions with regard to parasitic capacitive couplings, in particular to the floating gate and the control gate of the memory cell. These can also be largely adapted to the process and circuitry requirements by appropriate design of the lateral and upper termination of the buried bit line.
  • a low-resistance material e.g. a high-melting metal, preferably tungsten, is used.
  • the trench can easily be filled with tungsten, tungsten silicide or a highly doped polysilicon by CVD deposition.
  • An embodiment of the invention is characterized in that the etching of the trench is stopped just above the bottom of the insulation, so that the buried bit line remains completely insulated within the insulation.
  • the trench is etched through the insulation, as a result of which a well contact is formed outside the insulation by the buried bit line.
  • one or more so-called insulating or conductive liners can be deposited in the trench before the bit line is deposited, as a lateral and / or lower termination of the buried bit line.
  • the lateral and / or lower end of the buried bit line can be made of an insulating material, preferably silicon dioxide, silicon nitride, or titanium or titanium nitride. stand.
  • the buried bit line is self-aligning with the floating gate in the cell arrangement, as a result of which an additional mask layer is not necessary for its formation.
  • the starting point is in each case a floating gate arrangement 1 on a Si substrate 2 and an insulation 3 (shallow trench insulation) made of SiO 2 , in the Si substrate 2 under the float ting gate arrangement 1, wherein the floating gate 1 is first produced by etching into a poly-silicon layer 4 located on the silicon substrate after previous photolithography.
  • the buried bit line 4 is located within the insulation 3, or in a second variant extends through the insulation 3 into the region of the trough below it (FIG. 1 c), so that an additional Trough contact can be realized in the P-substrate 2.
  • the schematic sectional view according to FIG. 1 c shows a variant in which the buried bit line 5 is simultaneously used as a well contact.
  • the etching trench 6 can extend into the insulation 3 or extend through it. In the latter case, a buried contact can additionally be implemented through the buried bit line 5.
  • the buried bit line 5 is preferably above the normal level of insulation 3 (FIG. 1b).
  • the second exemplary embodiment (FIGS. 2a-e) contains the following method steps:
  • tungsten silicide can also be used to fill the trench 6.
  • floating gate 1 is used as an etching mask.
  • FIG. 4 prior art
  • FIG. 5 shows the considerable area saving.
  • the conventional UCP flash memory cell consists of a drain 10, a source region 11, a cell region 12, bit lines 13, 14.
  • the contacting of different metallization levels is effected by vias 15.
  • the significant area saving is achieved clearly visible.

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

L'invention concerne un procédé pour produire des lignes de binaires destinées à des mémoires flash UCP comportant un ensemble grille flottante placée sur un substrat ainsi qu'une isolation située dans le substrat, sous la grille flottante. Ce procédé consiste tout d'abord à produire la grille flottante, après photolithographie, par attaque d'une couche de silicium polycristallin déposée sur toute la surface du substrat. L'objectif de l'invention est de créer un procédé qui permet de réduire la taille des cellules, sans augmenter sensiblement les coûts de production, et selon lequel la ligne de binaire résiste aux températures des processus ultérieurs sans être endommagée. A cet effet, la ligne de binaire (13), se présentant sous la forme d'une ligne de binaire enterrée constituée d'un matériau résistant aux températures, est placée dans un substrat de silicium (2) ou dans l'isolation (3) des zones actives, sous la grille flottante (1) par ajustement automatique par rapport à cette dernière. La grille flottante (1), déjà structurée, est utilisée comme masque d'attaque pour produire, par attaque dans l'isolation (3), une tranchée (6) qui est ensuite remplie d'un matériau de faible impédance.
EP04702285A 2003-01-30 2004-01-15 Procede pour produire des lignes de binaires destinees a des memoires flash ucp Withdrawn EP1588417A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10303847 2003-01-30
DE10303847 2003-01-30
PCT/DE2004/000042 WO2004068578A2 (fr) 2003-01-30 2004-01-15 Procede pour produire des lignes de binaires destinees a des memoires flash ucp

Publications (1)

Publication Number Publication Date
EP1588417A2 true EP1588417A2 (fr) 2005-10-26

Family

ID=32797297

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04702285A Withdrawn EP1588417A2 (fr) 2003-01-30 2004-01-15 Procede pour produire des lignes de binaires destinees a des memoires flash ucp

Country Status (4)

Country Link
US (1) US7485542B2 (fr)
EP (1) EP1588417A2 (fr)
CN (1) CN1745473B (fr)
WO (1) WO2004068578A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160211250A1 (en) * 2015-01-15 2016-07-21 Infineon Technologies Ag Semiconductor substrate arrangement, a semiconductor device, and a method for processing a semiconductor substrate

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US4855800A (en) 1986-03-27 1989-08-08 Texas Instruments Incorporated EPROM with increased floating gate/control gate coupling
EP0503896B1 (fr) * 1991-03-12 1999-01-07 Kuraray Co., Ltd. Composé de spiroorthocarbonate et poymères obtenus à partir de celui-ci
US5278438A (en) 1991-12-19 1994-01-11 North American Philips Corporation Electrically erasable and programmable read-only memory with source and drain regions along sidewalls of a trench structure
FR2686837B1 (fr) 1992-01-31 1995-05-24 Valeo Thermique Habitacle Dispositif de chauffage-ventilation de l'habitacle d'un vehicule automobile a moteur a faibles rejets thermiques.
JP3065164B2 (ja) * 1992-03-18 2000-07-12 富士通株式会社 半導体装置及びその製造方法
US20040111159A1 (en) * 2000-01-30 2004-06-10 Diamicron, Inc. Modular bearing surfaces in prosthetic joints
US5570314A (en) * 1994-12-28 1996-10-29 National Semiconductor Corporation EEPROM devices with smaller cell size
US6001687A (en) * 1999-04-01 1999-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Process for forming self-aligned source in flash cell using SiN spacer as hard mask
WO2001017022A1 (fr) * 1999-08-27 2001-03-08 Infineon Technologies North America Corp. Dispositif a semiconducteur comportant des lignes binaires enfouies ameliorees
US6214741B1 (en) * 1999-11-05 2001-04-10 United Silicon Incorporated Method of fabricating a bit line of flash memory
JP2001168306A (ja) * 1999-12-09 2001-06-22 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US20020045304A1 (en) * 1999-12-30 2002-04-18 Chien-Hsing Lee Fabrication method and structure of flash memory device
JP2001244349A (ja) * 2000-02-29 2001-09-07 Nec Corp 半導体装置とその製造方法
US6355524B1 (en) * 2000-08-15 2002-03-12 Mosel Vitelic, Inc. Nonvolatile memory structures and fabrication methods
DE10122364B4 (de) * 2001-05-09 2006-10-19 Infineon Technologies Ag Kompensationsbauelement, Schaltungsanordnung und Verfahren
JP2003023113A (ja) 2001-07-05 2003-01-24 Mitsubishi Electric Corp 半導体装置およびその製造方法

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"Lexikon", Retrieved from the Internet <URL:http://reuschling.de/html/lexikon.htm> [retrieved on 20041116] *
"Wikipedia: Beschaltung der Signalleitungen", Retrieved from the Internet <URL:http://daswillichwissen.de/Open_circuit> [retrieved on 20041116] *
"Wikipedia: Open circuit", Retrieved from the Internet <URL:http://www.daswillichwissen.de/Open_circuit> [retrieved on 20041116] *
DEUTSCHE PHYSIKALISCHE GESELLSCHAFT E.V. (DPG): "E-Verhandlungen 2002 - Programm und Abstracts der Sitzung TT 15 - Metall-Isolatorübergänge, Phasenübergänge in Quantensystemen I", WWW-SERVER FÜR FRÜHJAHRSTAGUNGEN UND E-VERHANDLUNGEN, Retrieved from the Internet <URL:http://dpg.rz.uni-ulm.de/archive/2002/tt_15.html> [retrieved on 20041118] *
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Also Published As

Publication number Publication date
US7485542B2 (en) 2009-02-03
CN1745473B (zh) 2010-04-14
WO2004068578A3 (fr) 2004-10-28
US20060024889A1 (en) 2006-02-02
WO2004068578A2 (fr) 2004-08-12
CN1745473A (zh) 2006-03-08

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