EP1588417A2 - Method for producing bit lines for ucp flash memories - Google Patents

Abstract

The invention relates to a method for producing bit lines for UCP flash memories comprising a floating gate arrangement arranged on a substrate and an insulation arranged in the substrate under the floating gate arrangement. Initially, the floating gate is produced, after photolithography, by etching a separated polysilicon layer deposited on the total surface of the substrate. The aim of the invention is to provide a method wherein cell size can be reduced without significantly increasing production costs and wherein the bit lines survive the temperature budget of the sequence process without being damaged. As a result, the bit line (13), embodied as a buried bit line made of a temperature resistant material, is arranged in a silicon substrate (2) or in the insulation (3) of the active area below the floating gate (1) by automatic adjustment therewith (2). The already structured floating gate (1) is used as an etching mask for producing, by etching in insulation (3), a trench (6) which is subsequently filled with a low impedance material.

Description

 Method of making bit lines for UCP flash

Storage

The invention relates to a method for producing bit lines for UCP flash memories with a floating gate arrangement arranged on a substrate and an insulation underneath the floating gate arrangement, the floating gate initially being etched over the entire surface after the previous photolithography by etching deposited poly-silicon layer is produced.

With UCP (Uniform Channel Program) flash memories, two bit lines are required to connect the source and drain of the memory transistors. As a result, the grid dimension in the cell field in the direction perpendicular to the bit lines cannot become smaller than twice the minimum grid between the metal interconnects. The routing of the bit lines in different wiring levels does not change anything in principle, since the distance between the interconnects and the contact holes (vias) for connecting different wiring levels is generally the same size as the distance between two interconnects.

In the direction parallel to the bit lines, the grid dimension is usually designed to be minimal, according to the state of the art. The current concepts for UCP memories therefore use particularly aggressive metal design rules in order to make cell sizes as small as possible. However, there is still a competitive disadvantage compared to other concepts, especially with large and very large memories. A substantial reduction in the cell size can only be achieved if one of the two bit lines can be buried, ie essentially underneath the substrate surface. Such a buried bit line must meet further requirements with regard to its resistive and capacitive coating and must not significantly increase the manufacturing costs. In addition, the conductive material used for the buried bit line must survive the temperature budget of the subsequent processes without damage.

The invention is therefore based on the object of providing a method for producing bit lines for UCP flash memories, with which a reduction in cell size is achieved, the production costs are insignificantly influenced and the bit line survives the temperature budget of the subsequent processes without damage.

The object on which the invention is based is achieved in a method of the type mentioned at the outset in that the bit line is arranged in a self-aligned manner as a buried bit line made of a temperature-resistant material in a silicon substrate or within the insulation of the active regions under the floating gate.

In a continuation of the invention, using the already structured floating gate as an etching mask, a trench is etched into the insulation, which is then filled with a low-resistance material.

The solution according to the invention has the advantage that no additional photolithographic steps have to be carried out, as a result of which the additional process costs for producing the buried bit line are minimized. The self-adjustment of the buried bit line to the floating gate means that No further tolerance buffers are necessary to ensure minimum distances and there are extremely stable conditions with regard to parasitic capacitive couplings, in particular to the floating gate and the control gate of the memory cell. These can also be largely adapted to the process and circuitry requirements by appropriate design of the lateral and upper termination of the buried bit line.

For filling the trench with a low-resistance material, e.g. a high-melting metal, preferably tungsten, is used.

The trench can easily be filled with tungsten, tungsten silicide or a highly doped polysilicon by CVD deposition.

An embodiment of the invention is characterized in that the etching of the trench is stopped just above the bottom of the insulation, so that the buried bit line remains completely insulated within the insulation.

In a further advantageous embodiment of the invention, the trench is etched through the insulation, as a result of which a well contact is formed outside the insulation by the buried bit line.

Finally, one or more so-called insulating or conductive liners can be deposited in the trench before the bit line is deposited, as a lateral and / or lower termination of the buried bit line.

The lateral and / or lower end of the buried bit line can be made of an insulating material, preferably silicon dioxide, silicon nitride, or titanium or titanium nitride. stand.

The buried bit line is self-aligning with the floating gate in the cell arrangement, as a result of which an additional mask layer is not necessary for its formation.

The invention will be explained in more detail using an exemplary embodiment. In the accompanying drawings:

1 a - e: a schematic process sequence for producing a buried self-adjusting bit line in the isolation of the active regions;

2 a - e: a schematic process sequence according to FIG. 1 with an additional oxide liner which surrounds the bit line in the etched trench;

3 a - e: a variant of the method according to FIG. 1, in which polysilicon is used for the buried bit line, which is surrounded by an oxide liner as in FIG. 2;

4: the layout of a conventional UCP flash memory cell (prior art), and

5: the layout of a UCP flash memory cell with the significantly reduced area requirement made possible by the simplified method for producing a self-aligning buried bit line.

In the exemplary embodiment, three process variants are described. The starting point is in each case a floating gate arrangement 1 on a Si substrate 2 and an insulation 3 (shallow trench insulation) made of SiO ₂ , in the Si substrate 2 under the float ting gate arrangement 1, wherein the floating gate 1 is first produced by etching into a poly-silicon layer 4 located on the silicon substrate after previous photolithography.

In a first variant (FIG. 1 b), the buried bit line 4 is located within the insulation 3, or in a second variant extends through the insulation 3 into the region of the trough below it (FIG. 1 c), so that an additional Trough contact can be realized in the P-substrate 2.

The schematic sectional view according to FIG. 1 c shows a variant in which the buried bit line 5 is simultaneously used as a well contact.

To be able to implement this, the following process steps are necessary (Fig. 1 a - e):

a) Etching of the floating gate 1. b) Etching of the buried bit line 4 (buried bitline: BB) through the floating gate 1 and formation of a trench 6. c) Deposition of tungsten 7 in the etching trench 6 and subsequent chemical mechanical polishing (CMP) , d) etching back the tungsten 7. e) filling the etching trench 6 with an oxide and subsequent etching back.

The etching trench 6 can extend into the insulation 3 or extend through it. In the latter case, a buried contact can additionally be implemented through the buried bit line 5.

In one variant, the buried bit line 5 is preferably above the normal level of insulation 3 (FIG. 1b). The second exemplary embodiment (FIGS. 2a-e) contains the following method steps:

a) Etching of the floating gate 1. b) Etching of the trench 6 by the floating gate 1 and coating of the trench 6 with a liner 8. c) Deposition of tungsten 7 in the trench 6 and chemical mechanical polishing. d) etching back of tungsten 7. e) finally filling the trench 6 with an oxide 9 and etching back.

Instead of tungsten, tungsten silicide can also be used to fill the trench 6.

In the third variant (FIG. 3), tungsten is finally replaced by highly doped poly-Si. The following process steps are carried out:

a) etching of the floating gate 1. b) etching of the trench 6 for the buried bit line 5 by the floating gate 1 and filling of the trench 6 with an oxide liner 8. c) deposition of poly-Si in the trench 6 and etching back. d) reoxidation of the poly-Si. e) Final filling the trench with an oxide and from 9 ^¬ closing etch-back.

In all variants, floating gate 1 is used as an etching mask.

The comparison between FIG. 4 (prior art) and FIG. 5 with buried bit line shows the considerable area saving. The conventional UCP flash memory cell consists of a drain 10, a source region 11, a cell region 12, bit lines 13, 14. The contacting of different metallization levels is effected by vias 15. In the UCP flash memory memory cell shown in FIG. 5, the significant area saving is achieved clearly visible.

Method of making bit lines for UCP flash

Storage

LIST OF REFERENCE NUMBERS

Floating gate

Si substrate

isolation

Poly-silicon buried bit line

dig

tungsten

liner

oxide

drain

Source region

cell area

bit

bit

Via

Claims

Method of making bit lines for UCP flash memory claims 1. A method for producing bit lines for UCP flash memories with a floating gate arranged on a substrate and an insulation under the floating gate arrangement, the floating gate first being etched after the previous photolithography by etching a surface area deposited on the substrate Poly-Si layer has been produced, characterized in that the bit line (13) as a buried bit line made of a temperature-resistant material in a silicon substrate (2) or within the insulation (3) of the active areas under the floating gate (1 ) is self-aligned to this. 2. The method according to claim 1, so that a trench (6) is etched into the insulation (3) using the already structured floating gate (1) as an etching mask, which is then filled with a low-resistance material. 3. The method according to claim 2, so that a high-melting metal, preferably tungsten, is used to fill the trench (6) as a low-resistance material. 4. The method of claim 2, since you rchgekennzeic hn et that for filling the trench (6) as a low-resistance material, a silicide or a highly doped polysilicon is used. 5. The method according to claim 2, that the trench (6) is filled with tungsten or tungsten silicide by CVD deposition. 6. The method according to any one of claims 1 to 5, so that the etching of the trench (6) is stopped just above the bottom of the insulation (3). 7. The method according to any one of claims 1 to 5, characterized in that the trench (6) is etched through the insulation (3) and that through the bit line formed in the trench (6) an additional tub contact underneath the insulation ( 3) is trained. 8. The method according to any one of claims 1 to 6, so that one or more so-called liners (8) are deposited in the trench (6) before the bit line is deposited as a lateral and / or lower termination of the buried bit line (13). 9. The method of claim 8, d a d u r c h g e k e nn z e i c hn e t that silicon dioxide, silicon nitride, or titanium or titanium nitride are used as liners.