EP1580719A1 - Affichage, substrat a matrice active et procede d'excitation - Google Patents

Affichage, substrat a matrice active et procede d'excitation Download PDF

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Publication number
EP1580719A1
EP1580719A1 EP03777188A EP03777188A EP1580719A1 EP 1580719 A1 EP1580719 A1 EP 1580719A1 EP 03777188 A EP03777188 A EP 03777188A EP 03777188 A EP03777188 A EP 03777188A EP 1580719 A1 EP1580719 A1 EP 1580719A1
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EP
European Patent Office
Prior art keywords
terminal
current
input terminal
signal input
switch
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP03777188A
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German (de)
English (en)
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EP1580719A4 (fr
Inventor
Yoshiro Aoki
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Japan Display Central Inc
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Toshiba Matsushita Display Technology Co Ltd
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Publication of EP1580719A1 publication Critical patent/EP1580719A1/fr
Publication of EP1580719A4 publication Critical patent/EP1580719A4/fr
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0238—Improving the black level
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present invention relates to a display, active matrix substrate, and driving method and, more particularly, to a display which controls the optical characteristic of a display element by a current to be supplied to it, an active matrix substrate usable for the display, and a driving method of the display.
  • a display such as an organic EL (ElectroLuminescence) display which controls the optical characteristics of a display element by a drive current to be supplied to it
  • the drive current varies, the image quality becomes poor due to, e.g., uneven luminance.
  • the drive transistors which drive the display elements must have almost uniform characteristics between the pixels. In this display, however, since the transistors are normally formed on an insulating body such as a glass substrate, the transistor characteristics readily vary.
  • U.S. Patent Nos. 6,229,506 and 6, 373, 454B1 propose circuits shown in FIGS. 1 and 2, respectively. Characteristic correction of drive transistors by using these circuits will be described below.
  • an output control switch Sw2 is opened (OFF) by using a scan signal line 7 first.
  • a correction switch Sw3 is closed (ON) by using a scan signal line 15 to supply charges to capacitors C1 and C2 until no current flows between the source and drain of a drive transistor Tr.
  • the potential at a point A is equal to a threshold value Vth of the drive transistor Tr.
  • a scan signal is supplied from a scan signal line driver (not shown) to a scan signal line 6 to close a selection switch Sw1.
  • a reset signal Vrst is supplied from a video signal line driver (not shown) to a video signal line 9.
  • the correction switch Sw3 is opened, and the output control switch Sw2 is closed.
  • a video signal Vsig is supplied from the video signal line driver to the video signal line 9. Accordingly, the gate potential of the drive transistor Tr varies from the threshold value Vth by an amount equal to the variate from Vrst to Vsig. As a result, a drive current corresponding to the variation amount is supplied from a power supply line 11 to an organic EL element 20 through the drive transistor Tr and output control switch Sw2.
  • the influence of the threshold value Vth on the drive current can be eliminated.
  • the influence of such variation on the drive current to be supplied to the organic EL element 20 can be minimized.
  • the drive current is affected not only by the threshold value of the drive transistor Tr but also by its mobility and dimensions. For this reason, it is difficult in the circuit shown in FIG. 1 to so improve the light emission uniformity that no display nonuniformity is visually recognized.
  • the output control switch Sw2 is opened first. Simultaneously, the selection switch Sw1 and a correction/write switch Sw4 are closed. In this state, a current Isig corresponding to the video signal is supplied between the source and drain of the drive transistor Tr by using a constant current circuit (not shown). With this operation, the voltage between the two electrodes of the capacitor C2 becomes the gate-to-source voltage necessary for supplying the current Isig to the channel of the drive transistor Tr.
  • the potential at a point B is set by the above operation to supply a drive current almost equal to the current Isig between the source and drain of the drive transistor Tr.
  • a current having a magnitude almost equal to that of the current Isig supplied as a video signal during the write period can be supplied between the source and drain of the drive transistor Tr even during the holding period next to the write period. For this reason, not only the influence of the threshold value Vth of the drive transistor Tr but also the influence of its mobility and dimensions on the drive current can be eliminated.
  • a display comprising pixels arranged in a matrix, each of the pixels comprising a voltage signal input terminal to which a voltage signal is supplied, a drive control element including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal that outputs a current corresponding to a voltage between the first and second terminals, a first capacitor connected between the voltage signal input terminal and the control terminal, a current signal input terminal to which a current signal is supplied, a first switch connected between the current signal input terminal and the control terminal, a second switch connected between the current signal input terminal and the second terminal, an output control switch whose input terminal is connected to the second terminal, and a display element connected between a second power supply terminal and an output terminal of the output control switch.
  • a display comprising pixels arranged in a matrix, each of the pixels comprising a voltage signal input terminal to which a video signal and a reset signal are supplied as voltage signals, a drive control element including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal that outputs a current corresponding to a voltage between the first terminal and the control terminal, a first capacitor connected between the voltage signal input terminal and the control terminal, an output control switch whose input terminal is connected to the second terminal, a display element connected between a second power supply terminal and an output terminal of the output control switch, and a correction signal supply control unit that forms first and second conductive paths during a period when the output control switch disconnects the display element from the second terminal, the first conductive path allowing a reset current to flow between the first and second terminals, and the second conductive path allowing charges to move between the control terminal and an outside of the pixel.
  • a display comprising pixels arranged in a matrix, each of the pixels comprising a voltage signal input terminal to which a reset signal is supplied as a voltage signal during a correction period and a video signal is supplied as a voltage signal during a write period next to the correction period, a drive control element including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal that outputs a drive current corresponding to the video signal, a first capacitor connected between the voltage signal input terminal and the control terminal, a display element to which the drive current is to be supplied, an output control switch that disconnects the display element from the second terminal during the correction period and the write period and connects the display element to the second terminal after the write period, and a correction signal supply control unit that forms first and second conductive paths during the correction period and disconnects the second conductive path during the write period, the first conductive path allowing a reset current to flow between the first and second terminals, and the second conductive path allowing charges to move
  • a display comprising pixels arranged in a matrix, each of the pixels comprising a voltage signal input terminal to which a voltage signal is supplied, a drive control element including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal that outputs a current corresponding to a voltage between the first terminal and the control terminal, a first capacitor connected between the voltage signal input terminal and the control terminal, a current signal input terminal to which a current signal is supplied, a first switch connected between the current signal input terminal and the control terminal, a second switch connected between the current signal input terminal and the second terminal, an output control switch whose input terminal is connected to the second terminal, and a display element connected between a second power supply terminal and an output terminal of the output control switch, wherein the display changes a write operation between first and second write operations on the basis of a gray level to be displayed, the first write operation includes setting the voltage signal input terminal to a first potential, and opening the output control switch and closing the first and second
  • a display comprising pixels arranged in a matrix, each of the pixels comprising a voltage signal input terminal to which a voltage signal is supplied, a drive control element including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal that outputs a current corresponding to a voltage between the first terminal and the control terminal, a first capacitor connected between the voltage signal input terminal and the control terminal, a current signal input terminal to which a current signal is supplied, a first switch connected between the current signal input terminal and the control terminal, a second switch connected between the current signal input terminal and the second terminal, an output control switch whose input terminal is connected to the second terminal, and a display element connected between a second power supply terminal and an output terminal of the output control switch, wherein a write operation of the display includes setting the voltage signal input terminal to a first potential, and opening the output control switch and closing the first and second switches to supply a current as a video signal between the first and second terminals, subsequently opening
  • an active matrix substrate on which a display element is to be formed comprising a voltage signal input terminal to which a voltage signal is supplied, a drive control element including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal that outputs a current corresponding to a voltage between the first terminal and the control terminal, a first capacitor connected between the voltage signal input terminal and the control terminal, a current signal input terminal to which a current signal is supplied, a first switch connected between the current signal input terminal and the control terminal, a second switch connected between the current signal input terminal and the second terminal, and an output control switch including an input terminal connected to the second terminal and an output terminal to be connected to the display element.
  • a method of driving a display comprising pixels arranged in a matrix, each of the pixels comprising a drive control element including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal that outputs a current corresponding to a voltage between the first terminal and the control terminal, a display element connected between the second terminal and a second power supply terminal, and a capacitor connected between the control terminal and the voltage signal input terminal, comprising supplying a current as a reset signal between the first terminal and the second terminal in a state that the voltage signal input terminal is set to a reset potential, the display element is disconnected from the second terminal, and the control terminal is connected to an outside of the pixel, subsequently disconnecting the control terminal from the outside of the pixel, and then setting the voltage signal input terminal to a potential corresponding to the video signal.
  • a method of driving a display comprising pixels arranged in a matrix, each of the pixels comprising a drive control element including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal that outputs a current corresponding to a voltage between the first terminal and the control terminal, a display element connected between the second terminal and a second power supply terminal, and a capacitor connected between the control terminal and the voltage signal input terminal, comprising changing a write operation between first and second write operations on the basis of a gray level to be displayed, wherein the first write operation includes supplying a current as a video signal between the first and second terminals in a state that the voltage signal input terminal is set to a first potential, the display element is disconnected from the second terminal, and the control terminal is connected to an outside of the pixel, and the second write operation includes supplying a current as a reset signal between the first and second terminals in a state that the voltage signal input terminal is set to a second potential, the display element
  • a method of driving a display comprising pixels arranged in a matrix, each of the pixels comprising a drive control element including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal that outputs a current corresponding to a voltage between the first terminal and the control terminal, a display element connected between the second terminal and a second power supply terminal, and a capacitor connected between the control terminal and the voltage signal input terminal, comprising setting the voltage signal input terminal to a first potential, and opening the output control switch and closing the first and second switches to supply a current as a video signal between the first and second terminals, subsequently opening the first switch, and simultaneously or since then setting the voltage signal input terminal to a second potential different from the first potential.
  • FIG. 3 is a plan view schematically showing a display according to the first embodiment of the present invention.
  • a display 1 is, e.g., an organic EL display and includes a plurality of pixels 2.
  • the pixels 2 are arranged in a matrix on a substrate 3.
  • a scan signal line driver 4 and video signal line driver 5 are also arranged on the substrate 3.
  • the video signal line driver 5 constitutes at least part of a current signal supply circuit.
  • the video signal line driver 5 also constitutes at least part of a voltage signal supply circuit.
  • the video signal line driver 5 incorporates, as the current signal supply circuit, a constant current circuit which outputs a predetermined current, i.e., a reset current.
  • Scan signal lines 6 to 8 connected to the scan signal line driver 4 run on the substrate 3 in the row direction of the pixels 2.
  • a scan signal is supplied from the scan signal line driver 4 to the scan signal lines 6 to 8 as a voltage signal.
  • Voltage signal lines 9 which are connected to the video signal line driver 5 and receive a voltage signal and current signal lines 10 which are connected to the video signal line driver 5 and receive a current signal run on the substrate 3 in the column direction of the pixels 2.
  • the voltage signal lines 9 are video signal lines to which a video signal is supplied from the video signal line driver 5.
  • the current signal lines 10 are the reset signal lines 10 connected to the constant current circuit incorporated in the video signal line driver 5.
  • a power supply line 11 is also formed on the substrate 3.
  • Each pixel 2 includes a drive transistor Tr, a selection switch Sw1, an output control switch Sw2, correction signal supply control switches Sw5a and Sw5b, capacitors C1 and C2, and a display element 20.
  • the switches Sw1, Sw2, Sw5a, and Sw5b are, e.g., thin film transistors (TFTs).
  • the capacitors C1 and C2 are, e.g., thin film capacitors.
  • the drive transistor Tr is assumed to include a TFT.
  • the display element 20 includes an anode and a cathode, which face each other, and an active layer whose optical characteristics change depending on the current that flows between the anode and the cathode.
  • the display element 20 is an organic EL element including a light-emitting layer as the active layer.
  • the anode is arranged as a lower electrode and connected to the drive transistor Tr via the output control switch Sw2.
  • the cathode is arranged as, e.g., an upper electrode which faces the lower electrode via the active layer.
  • the drive transistor Tr is, e.g., a p-channel TFT.
  • the gate is connected to one electrode of the capacitor C1.
  • the drive transistor Tr is a p-channel TFT
  • the source is connected to the power supply line 11, and the drain is connected to the lower electrode of the organic EL element 20 via the output control switch Sw2.
  • the input terminal of the selection switch Sw1 is connected to the video signal line 9.
  • the output terminal is connected to the gate of the drive transistor Tr via the capacitor C1.
  • the switching operation of the selection switch Sw1 is controlled by a scan signal supplied from the scan signal line 6.
  • the selection switch Sw1 is, e.g., a p-channel TFT.
  • the gate is connected to the scan signal line 6.
  • the source is connected to the video signal line 9.
  • the drain is connected to the other electrode of the capacitor C1.
  • the output control switch Sw2 is connected between the drive transistor Tr and the organic EL element 20.
  • the switching operation of the output control switch Sw2 is controlled by a scan signal supplied from the scan signal line 7.
  • the output control switch Sw2 is, e.g., a p-channel TFT.
  • the gate is connected to the scan signal line 7.
  • the source and drain are connected to the drive transistor Tr and the organic EL element 20, respectively.
  • the correction signal supply control switch Sw5a is connected between the reset signal line 10 and the gate of the drive transistor Tr.
  • the switching operation of the switch Sw5a is controlled by a scan signal supplied from the scan signal line 8.
  • the correction signal supply control switch Sw5a is, e.g., a p-channel TFT.
  • the gate is connected to the scan signal line 8.
  • the source and drain are connected to the gate of the drive transistor Tr and the reset signal line 10, respectively.
  • the correction signal supply control switch Sw5b is connected between the reset signal line 10 and the drain of the drive transistor Tr.
  • the switching operation of the switch Sw5b is controlled by a scan signal supplied from the scan signal line 8.
  • the correction signal supply control switch Sw5b is, e.g., a p-channel TFT.
  • the gate is connected to the scan signal line 8.
  • the source and drain are connected to the drain of the drive transistor Tr and the reset signal line 10, respectively.
  • the correction signal supply control switches Sw5a and Sw5b form a correction signal supply control unit.
  • This correction signal supply control unit may have a structure other than that shown in FIG. 3 if connection/disconnection between the drain of the drive transistor Tr, the gate of the drive transistor Tr, and the reset signal line 10 can be switched.
  • the switching operations of the correction signal supply control switches Sw5a and Sw5b are controlled by one scan signal line 8. Instead, the switching operations may be controlled by two scan signal lines.
  • the correction signal supply control switch Sw5a is connected between the reset signal line 10 and the drain of the drive transistor Tr. Instead, the correction signal supply control switch Sw5a may be connected between the drain of the drive transistor Tr and the gate of the drive transistor Tr.
  • the capacitor C1 is connected between the selection switch Sw1 and the gate of the drive transistor Tr.
  • the capacitor C2 is connected between the source of the drive transistor Tr and the gate of the drive transistor Tr.
  • the capacitances of the capacitors C1 and C2 need not be equal. However, they are assumed to be equal here for the sake of simplicity.
  • the capacitor C2 may be connected between, e.g., the gate of the drive transistor Tr and a constant potential terminal insulated from the source of the drive transistor Tr instead of between the source of the drive transistor Tr and the gate of the drive transistor Tr. More specifically, the capacitor C2 need not always be connected between the gate and source of the drive transistor Tr if the capacitor C2 has one terminal connected to the gate of the drive transistor Tr and can hold the gate-to-source voltage of the drive transistor Tr in correspondence with a video signal.
  • the substrate 3 scan signal lines 6, voltage signal lines 9, current signal lines 10, power supply line 11, switches Sw1, Sw2, Sw5a, and Sw5b, drive transistors Tr, and capacitors C1 and C2 form an active matrix substrate.
  • This active matrix substrate can also include the scan signal line driver 4 and video signal line driver 5.
  • This active matrix substrate can also include one electrode of each display element.
  • the display 1 shown in FIG. 3 is driven by, e.g., a method to be described below.
  • FIG. 4 is a timing chart schematically showing an example of the driving method of the display 1 shown in FIG. 3.
  • FIGS. 5 and 6 are views showing the direction of a current which flows when the display 1 shown in FIG. 3 is driven by the method shown in FIG. 4.
  • All the switches Sw1, Sw2, Sw5a, and Sw5b are p-channel TFTs.
  • "Sw5 gate potential” indicates the gate potential of the switches Sw5a and Sw5b.
  • Point D potential indicates the gate potential of the drive transistor Tr.
  • dotted arrows indicate the flowing directions of currents.
  • one horizontal period includes a correction period P2 and a write period P3.
  • One vertical period includes the correction period P2, the write period P3, and a holding period P4.
  • a period P1 indicates a holding period one vertical period before.
  • the selection switch Sw1 and correction signal supply control switches Sw5a and Sw5b are open.
  • the output control switch Sw2 is closed.
  • the drive transistor Tr is outputting a drive current corresponding to the magnitude of a video signal Vsig written one frame before.
  • the organic EL element 20 is emitting light.
  • the output control switch Sw2 is closed while keeping the selection switch Sw1 and correction signal supply control switches Sw5a and Sw5b open.
  • the correction signal supply control switches Sw5a and Sw5b are closed, and the selection switch Sw1 is closed to supply a reset signal Vrst to a node E as a voltage signal input terminal.
  • a predetermined constant current i.e., a reset current Irst is supplied between the source and drain of the drive transistor Tr. Accordingly, a current flows between the reset signal line 10 and the gate of the drive transistor Tr. As a result, the potential of a node D changes as shown in FIG. 4. More specifically, a correction signal Vcrct on which the element characteristics such as the threshold value, mobility, and dimensions are reflected is supplied to the node D.
  • the drive current output from the drive transistor Tr equals the reset current Irst.
  • the effect for correcting the characteristic of the drive transistor Tr is maximized when the magnitude of the video signal Vsig equals the reset signal Vrst.
  • the reset current Irst may be set to be almost equal to the drive current corresponding to the gray level at which the maximum effect should be obtained.
  • the selection switch Sw1 is continuously kept closed, and the output control switch Sw2 and correction signal supply control switches Sw5a and Sw5b are kept open.
  • the video signal Vsig is supplied to the node E as an input terminal in this state. Accordingly, as shown in FIG. 4, the potential of the node D changes along with the change in potential of the node E.
  • the output control switch Sw2 is closed. Accordingly, a current flows to the organic EL element 20, as shown in FIG. 6.
  • the organic EL element 20 emits light at a luminance corresponding to the video signal Vsig.
  • the selection switch Sw1 is set in the OFF state to end the write period P3.
  • the selection switch Sw1 and correction signal supply control switches Sw5a and Sw5b are open, and the output control switch Sw2 is kept closed. For this reason, the potential of the node D is maintained almost at a predetermined level.
  • the organic EL element 20 continuously emits light at the luminance corresponding to the video signal Vsig.
  • the characteristics are corrected by using the correction signal Vcrct on which the element characteristics of the drive transistor Tr, i.e., the threshold value, mobility, and dimensions of the drive transistor Tr are reflected. Additionally, in this method, the correction signal Vcrct obtained in association with a given transistor is used to correct that transistor itself. For this reason, according to the above method, the influence of the variation in characteristic of the transistor on the drive current can very effectively be reduced.
  • the constant current circuit capable of supplying the constant current Irst is necessary, though no constant current circuit capable of freely changing the current value is necessary. For this reason, the above-described method is very advantageous for cost reduction of the display 1.
  • FIG. 7 is a graph showing an example of the effect obtained by the method according to the first embodiment of the present invention.
  • the abscissa represents the video signal Vsig supplied to the electrode of the capacitor C1 on the side of the selection switch Sw1 during the write period.
  • the ordinate represents the current which flows between the source and drain of the drive transistor Tr during the holding period, i.e., the output current or drive current.
  • Curves 51a to 51c in FIG. 7 indicate data obtained when the display 1 shown in FIG. 3 is driven by the method described with reference to FIG. 4.
  • Curves 52a to 52c in FIG. 7 indicate data obtained when the display 1 shown in FIG. 1 is driven by the method described in association with it.
  • the channel width of the drive transistor Tr was 5 ⁇ m, and the channel length was 20 ⁇ m.
  • the mobility of the drive transistor Tr was 100 cm 2 /V ⁇ S.
  • the mobility of the drive transistor Tr was 150 cm 2 /V ⁇ S.
  • the mobility of the drive transistor Tr was 200 cm 2 /V ⁇ S.
  • the reset potential Vrst was 0V, and the reset current Irst was 0.5 ⁇ A.
  • the influence of the variation in mobility of the drive transistor Tr on the output current is suppressed as compared to the method described with reference to FIG. 1.
  • the influence of the variation in mobility of the drive transistor Tr on the output current is 1/2 or less in the method of this embodiment as compared to the method described with reference to FIG. 1.
  • the influence of the variation in characteristics of the transistor can very effectively be reduced.
  • the characteristics of the drive transistor Tr are corrected for each pixel row. More specifically, characteristic correction is executed simultaneously for all the pixels 2 included in a selected pixel row during each horizontal period. In the second embodiment, however, pixels 2 included in a selected pixel row during each horizontal period are classified into a plurality of groups, and the characteristic correction operation is done sequentially for the pixel groups. An example will be described below, in which the correction operation is sequentially executed for each pixel 2.
  • FIG. 8 is a plan view schematically showing a display according to the second embodiment of the present invention.
  • a display 1 is, e.g., an organic EL display and includes the plurality of pixels 2.
  • the pixels 2 are arranged in a matrix on a substrate 3.
  • a scan signal line driver 4 and video signal line driver 5 are arranged on the substrate 3.
  • the scan signal line driver 4 incorporates, as a current signal supply circuit, a constant current circuit which outputs a predetermined current, i.e., a reset current.
  • Scan signal lines 6, 7, and 8a connected to the scan signal line driver 4 and reset signal lines 10 connected to the constant current circuit incorporated in the scan signal line driver 4 run on the substrate 3 in the row direction of the pixels 2.
  • a scan signal is supplied from the scan signal line driver 4 to the scan signal lines 6, 7, and 8a as a voltage signal.
  • the reset signal line 10 is a current signal line to which a reset current is supplied from the scan signal line driver 4.
  • Video signal lines 9 and control signal lines 8b which are connected to the video signal line driver 5, run on the substrate 3 in the column direction of the pixels 2.
  • a power supply line 11 is formed on the substrate 3.
  • a video signal is supplied from the video signal line driver 5 to the video signal lines 9 as a voltage signal.
  • a control signal is supplied from the video signal line driver 5 to the control signal lines 8b as a voltage signal.
  • Each pixel 2 includes a drive transistor Tr, a selection switch Sw1, an output control switch Sw2, correction signal supply control switches Sw5a, Sw5b, and Sw5c, capacitors C1, C2, and C3, and a display element 20.
  • the switches Sw1, Sw2, Sw5a, Sw5b, and Sw5c are, e.g., TFTs.
  • the capacitors C1, C2, and C3 are, e.g., thin film capacitors.
  • the drive transistor Tr is assumed to include a TFT.
  • the correction signal supply control switch Sw5c is connected between the control signal line 8b and each gate of the correction signal supply control switches Sw5a and Sw5b.
  • the switching operation of the switch Sw5c is controlled by a scan signal supplied from the scan signal line 8a. That is, in this embodiment, the correction signal supply control switches Sw5a, Sw5b, and Sw5c form a correction signal supply control unit.
  • the capacitor C3 is connected between the gates of the switches Sw5a and Sw5b and a constant voltage source and, in this example, GND.
  • the correction signal supply control switch Sw5c is, e.g., a p-channel TFT.
  • the gate of the switch Sw5c is connected to the scan signal line 8a.
  • the source and drain are connected to the control signal line 8b and each gate of the switches Sw5a and Sw5b, respectively.
  • the substrate 3, scan signal lines 6, 7, and 8a, control signal lines 8b, voltage signal lines 9, current signal lines 10, power supply line 11, switches Sw1, Sw2, Sw5a, Sw5b, and Sw5c, drive transistors Tr, and capacitors C1, C2, and C3 form an active matrix substrate.
  • This active matrix substrate can also include the scan signal line driver 4 and video signal line driver 5.
  • This active matrix substrate can also include one electrode of each display element.
  • the reset signal line 10 connected to the constant current circuit is arranged almost parallel to the scan signal line 6.
  • the scan signal line 8a and control signal line 8b which run in the horizontal and vertical directions, and the correction signal supply control switch Sw5c
  • the switching operations of the correction signal supply control switches Sw5a and Sw5b can be controlled for each pixel 2.
  • the same correction as that described in the first embodiment can be executed sequentially for the pixels 2 in each row.
  • all the pixels 2 included in one row can be corrected by, e.g., one constant current circuit.
  • the constant current circuit used for characteristic correction of the pixels 2 included in a row can be used even for characteristic correction of the pixels 2 included in another row.
  • FIG. 9 is a plan view schematically showing a display according to the third embodiment of the present invention.
  • FIG. 10 is a timing chart schematically showing an example of the driving method of a display 1 shown in FIG. 9. Referring to FIG. 10, "Sw5 gate potential" indicates the gate potential of switches Sw5a, Sw5b, and Sw5d.
  • the display 1 is, e.g., an organic EL display and includes a plurality of pixels 2.
  • the pixels 2 are arranged in a matrix on a substrate 3.
  • a scan signal line driver 4 and video signal line driver 5 are arranged on the substrate 3.
  • the video signal line driver 5 incorporates a constant current circuit.
  • a control signal line 12 which runs in the row direction of the pixels 2 is connected to each scan signal line 8.
  • Video signal lines 9 connected to the video signal line driver 5 run on the substrate 3 in the column direction of the pixels 2.
  • a power supply line 11 is formed on the substrate 3.
  • the video signal line driver 5 selects one of the constant current circuit and the circuit which outputs a video signal as a voltage signal and connects the video signal line 9 to the selected circuit. That is, in this example, the video signal line 9 is a voltage/current signal line.
  • Each pixel 2 includes a drive transistor Tr, a selection switch Sw1, an output control switch Sw2, the correction signal supply control switches Sw5a, Sw5b, and Sw5d, capacitors C1 and C2, and a display element 20.
  • the switches Sw1, Sw2, Sw5a, Sw5b, and Sw5d are, e.g., TFTs.
  • the capacitors C1 and C2 are, e.g., thin film capacitors.
  • the drive transistor Tr is assumed to include a TFT.
  • the correction signal supply control switch Sw5d is connected between the reset signal supply line 13 and the electrode of the capacitor C1 on the side of the selection switch Sw1.
  • the switching operation of the switch Sw5d is controlled by a scan signal supplied from the scan signal line 8 through the control line 12.
  • the correction signal supply control switches Sw5a, Sw5b, and Sw5d form a correction signal supply control unit.
  • the correction signal supply control switch Sw5d is, e.g., a p-channel TFT.
  • the gate of the switch Sw5d is connected to the scan signal line 8.
  • the source and drain are connected to the reset signal supply line 13 and the electrode of the capacitor C1 on the side of the selection switch Sw1, respectively.
  • the substrate 3 scan signal lines 6 to 8 and 13, voltage/current signal lines 9, power supply line 11, control signal lines 12, switches Sw1, Sw2, Sw5a, Sw5b, and Sw5d, drive transistors Tr, and capacitors C1 and C2 form an active matrix substrate.
  • This active matrix substrate can also include the scan signal line driver 4 and video signal line driver 5.
  • This active matrix substrate can also include one electrode of each display element.
  • a reset signal Vrst is supplied from the reset signal supply line 13 to a node E through the correction signal supply control switch Sw5d.
  • a reset current Irst can flow to the video signal line 9. That is, the video signal line 9 is used for both supply of a video signal Vsig and supply of the reset current Irst. Since the reset signal line 10 formed independently of the video signal line 9 is unnecessary, the number of wiring lines which run almost parallel to the video signal lines 9 can be decreased.
  • a voltage signal is supplied as a video signal.
  • an arrangement capable of supplying both a voltage signal corresponding to a video signal and a current signal corresponding to a video signal is employed.
  • FIG. 11 is a plan view schematically showing a display according to the fourth embodiment of the present invention.
  • a display 1 shown in FIG. 11 is, e.g., an organic EL display.
  • the display 1 has the same structure as that of the display 1 shown in FIG. 3 except that the following arrangement is employed.
  • the display 1 shown in FIG. 11 includes a voltage/current source 25 connected to a video signal line driver 5.
  • the voltage/current source 25 incorporates a voltage source capable of changing the output voltage and a current source capable of changing the output current.
  • a correction signal supply control switch Sw5b is connected between the gate and drain of a drive transistor Tr.
  • the switch Sw5b may be connected between a reset signal line 10 and the gate of the drive transistor Tr.
  • a substrate 3 scan signal lines 6 to 8, voltage signal lines 9, current signal lines 10, power supply line 11, switches Sw1, Sw2, Sw5a, and Sw5b, drive transistors Tr, and capacitors C1 and C2 form an active matrix substrate.
  • This active matrix substrate can also include a scan signal line driver 4 and the video signal line driver 5.
  • This active matrix substrate can also include one electrode of each display element.
  • FIG. 12 is an equivalent circuit diagram of the video signal line driver and the voltage/current source, which can be used in the display shown in FIG. 11.
  • the voltage/current source 25 includes a current source CS, voltage source VS, switch SwC1, and switch SwV1.
  • the switch SwC1 is connected between the current source CS and the output terminal of the voltage/current source 25.
  • the switch SwV1 is connected between the voltage source VS and the output terminal of the voltage/current source 25.
  • the voltage source VS and current source CS can be formed on one IC (Integrated Circuit) 16.
  • the switch SwC1 and switch SwV1 can also be formed on the IC 16.
  • the voltage/current source 25 can include, e.g., a plurality of ICs 16.
  • the video signal line driver 5 includes a constant potential line 14, switch SwV0, switch SwV2, and switch SwC2.
  • the constant potential line 14 is set to a predetermined potential of, e.g., 0V.
  • the switch SwV0 is connected between the constant potential line 14 and the voltage signal line 9.
  • the switch SwV2 is connected between the voltage signal line 9 and the output terminal of the voltage/current source 25.
  • the switch SwC2 is connected between the current signal line 10 and the output terminal of the voltage/current source 25.
  • FIG. 13 is a timing chart schematically showing an example of the method of driving the display shown in FIG. 11.
  • one horizontal period includes a first write period P3C and a second write period P3V.
  • One vertical period includes the first write period P3C, second write period P3V, and a holding period P4.
  • an output current Iout from the current source CS and an output voltage Vout from the voltage source VS in the case of displaying a brighter gray level differ from those in the case of displaying a darker gray level.
  • FIG. 13 assumes that, for example, a brighter gray level is displayed by the pixels 2 of the mth and (m+2)th rows, and a darker gray level is displayed by the pixels 2 of the (m+1)th row.
  • the display 1 is driven by, e.g., the following method.
  • the switch Sw2 is opened first.
  • the first write operation and second write operation are sequentially executed.
  • the switches SwV0, SwC1 and SwC2 are closed, and the switches SwV1 and SwV2 are opened. More specifically, the voltage source VS is disconnected from the video signal line driver 5.
  • the constant potential line 14 is connected to the voltage signal line 9, and the current source CS is connected to the current signal line 10.
  • the switches Sw1, Sw5a, and Sw5b are closed to set the output current Iout from the current source CS to a current signal Isig of, e.g., 500 nA corresponding to the video signal.
  • the gate-to-source voltage of the drive transistor Tr is set to a value when the current Isig flows between the source and drain.
  • the first write period P3C is ended by opening the switches Sw5a and Sw5b.
  • the voltage source VS is disconnected from the video signal line driver 5.
  • the potential Vout at the output terminal of the voltage source VS can have any value.
  • the potential Vout at the output terminal of the voltage source VS is set to 0V.
  • the gate-to-source voltage of the drive transistor Tr which is set during the first write period P3C, is held. More specifically, the switch Sw5b is kept open. For example, during the second write period P3V, the switches SwV0, SwC1, and SwC2 are opened, and the switches Sw1, SwV1, and SwV2 are closed. In this case, for example, the potential Vout at the output terminal of the voltage source VS is set to a predetermined potential of, e.g., 0V.
  • the second write period P3V is ended by opening the switch Sw1.
  • the switch Sw2 is closed. Accordingly, a current having a magnitude almost equal to the current Isig flows to the display element 20.
  • the switches SwV0, SwC1, and SwC2 are closed, and the switches SwV1 and SwV2 are opened.
  • the current signal Isig is supplied between the source and drain of the drive transistor Tr as a video signal.
  • the potential of a node D is set to a value corresponding to the video signal. Since the current Isig is sufficiently large, the potential of the node D faithfully reflects the characteristic of the drive transistor Tr. More specifically, according to this embodiment, not only the influence of a threshold value Vth of the drive transistor Tr but also the influence of its mobility and dimensions on the drive current can completely be eliminated.
  • the display 1 is driven by, e.g., the following method.
  • the switch Sw2 is opened first, as described about the mth row selection period.
  • the first write operation and second write operation are sequentially executed.
  • the switches SwV0, SwC1 and SwC2 are closed, and the switches SwV1 and SwV2 are opened, as described about the mth row selection period. More specifically, the voltage source VS is disconnected from the video signal line driver 5. In addition, the constant potential line 14 is connected to the voltage signal line 9, and the current source CS is connected to the current signal line 10. In this state, the switches Sw1, Sw5a, and Sw5b are closed.
  • the output current Iout from the current source CS is set to not the current Isig corresponding to the video signal but a predetermined reset current Irst of, e.g., 100 nA. Accordingly, the gate-to-source voltage of the drive transistor Tr is set to a value Vcrct when the current Irst flows between the source and drain.
  • the first write period P3C is ended by opening the switches Sw5a and Sw5b.
  • the gate-to-source voltage of the drive transistor Tr which is set during the first write period P3C, is held, as described about the mth row selection period. More specifically, the switch Sw5b is kept open. During the second write period P3V, the switches SwV0, SwC1, and SwC2 are opened, and the switches SwV1 and SwV2 are closed.
  • the voltage signal Vout output from the voltage source VS is set to a voltage signal Vsig' of, e.g., 4V corresponding to the video signal.
  • the voltage signal Vsig' falls within the range of, e.g., 0V to 6V.
  • a node E as a voltage signal input terminal is set to the potential Vsig'.
  • the second write period P3V is ended by opening the switch Sw1.
  • the potential of the node D is set to the value Vcrct when the current Irst flows between the source and drain of the drive transistor Tr. For this reason, when the potential of the node E is changed from, e.g., 0V to Vsig' during the second write period P3V, the potential of the node D changes from Vcrct to Vcrct + Vsig".
  • Vsig is a value determined by the gate potential of the drive transistor Tr and the capacitance ratio of the capacitors C1 and C2.
  • Vsig Vsig" + Vcrct (Av).
  • Vcrct (Av) is a value expected for the potential Vcrct and, for example, the average value of Vcrct for all pixels.
  • the potential Vcrct is affected not only by the threshold value of the drive transistor Tr but also by its mobility and dimensions.
  • the potential Vcrct faithfully reflects the characteristic of the drive transistor Tr. Hence, at the time when the second write period P3V is ended, the characteristics of the drive transistor Tr are corrected.
  • the switch Sw2 is closed, as described about the mth row selection period. Accordingly, a current having a magnitude almost corresponding to the potential Vcrct + Vsig' flows to the display element 20.
  • the switches SwV0, SwC1, and SwC2 are closed, and the switches SwV1 and SwV2 are opened.
  • the sufficiently large reset current Irst is supplied between the source and drain of the drive transistor Tr first.
  • the correction signal Vcrct corresponding to the reset current Irst is supplied to the node D. Accordingly, the variations of the characteristics, i.e., the threshold value Vth, mobility, and dimensions of the drive transistor Tr are corrected.
  • the voltage signal Vsig' almost corresponding to the video signal is supplied to the node E, and the potential of the node D is set to Vcrct + Vsig'.
  • the correction signal Vcrct completely eliminates the influence of the characteristics, i.e., the threshold value Vth, mobility, and dimensions of the drive transistor Tr on the drive current.
  • the correction signal Vcrct does not completely eliminate the influence of the characteristics of the drive transistor Tr on the drive current.
  • the correction signal Vcrct contains an error corresponding to the difference between the potential of the node E during the second write period P3V and the potential of the node E during the first write period P3C. If the potential difference is sufficiently small, the error of the correction signal Vcrct also becomes small.
  • the influences of the characteristics, i.e., the threshold value Vth, mobility, and dimensions of the drive transistor Tr on the drive current can almost completely be eliminated.
  • the output from the voltage source VS or the output from the current source CS is selected in the voltage/current source 25. For this reason, the number of output terminals of the voltage/current source 25 or the number of the input terminals of the video signal line driver can be one for each pixel row.
  • FIG. 14 is a plan view schematically showing a display according to the fifth embodiment of the present invention.
  • a display 1 shown in FIG. 14 is, e.g., an organic EL display.
  • the display 1 has the same structure as that of the display 1 shown in FIG. 11 except that the following arrangement is employed.
  • current signal lines 10 are omitted.
  • voltage signal lines 9 are used as voltage/current signal lines to which both a voltage signal and a current signal are supplied.
  • a constant potential line 26 is arranged in the display 1.
  • each pixel 2 the drain of a switch Sw1 is connected to the voltage/current signal line 9.
  • a correction signal supply control switch Sw5e connected between the source of the switch Sw1 and the constant potential line 26 is arranged.
  • a p-channel transistor is used as the switch Sw5e.
  • the source of the switch Sw5e is connected to the constant potential line 26.
  • the source of the switch Sw5e may be connected to a power supply line 11. In this case, the constant potential line 26 can be omitted.
  • Scan signal lines 17 connected to a scan signal line driver 4 are arranged on a substrate 3.
  • the gate of the switch Sw5e is connected to the scan signal line 17.
  • a video signal line driver 5 shown in FIG. 12 is omitted. Instead, the output terminals of a voltage/current source 25 are connected to the voltage/current signal lines 9 so that the voltage/current source 25 is used as the video signal line driver.
  • the substrate 3 scan signal lines 6 to 8 and 17, voltage/current signal lines 9, power supply line 11, constant potential line 26, switches Sw1, Sw2, Sw5a, Sw5b, and Sw5e, drive transistors Tr, and capacitors C1 and C2 form an active matrix substrate.
  • This active matrix substrate can also include the scan signal line driver 4 and the like.
  • This active matrix substrate can also include one electrode of each display element.
  • the display 1 is driven by, e.g., the following method.
  • the switch Sw2 is opened first, as described with reference to FIG. 13. Within the period when the switch Sw2 is open, the first write operation and second write operation are sequentially executed.
  • switches SwV0, SwC1, and SwC2 are closed, and switches SwV1 and SwV2 are opened, as described with reference to FIG. 13. More specifically, a voltage source VS is disconnected from the video signal line driver 5. In addition, a constant potential line 14 is connected to the voltage signal line 9, and a current source CS is connected to the current signal line 10. In this state, the switches Sw5a, Sw5b, and Sw5e are closed. The switch Sw1 is kept open.
  • an output current Iout from the current source CS is set to a current signal Isig corresponding to a video signal. Accordingly, the gate-to-source voltage of the drive transistor Tr is set to a value when the current Isig flows between the source and drain.
  • the first write period P3C is ended by opening the switches Sw5a and Sw5b.
  • the switch Sw5e is opened.
  • the switch Sw5e may be opened at this time or simultaneously as the switch Sw5b is opened.
  • the switch SwC1 is opened, and the switches Sw1 and SwV1 are closed.
  • the potential Vout at the output terminal of the voltage source VS almost equals a potential V0 of the constant potential line 26.
  • the switch Sw1 is opened. With this operation, the second write period P3V is ended.
  • the switch Sw2 is closed. Accordingly, a current having a magnitude almost equal to the current Isig flows to a display element 20.
  • the switch SwC1 is closed, and the switch SwV1 is opened.
  • the switch Sw2 is opened first, as described with reference to FIG. 13. Within the period when the switch Sw2 is open, the first write operation and second write operation are sequentially executed.
  • the switch SwC1 is closed, and the switch SwV1 is opened, as described about the mth row selection period. More specifically, the voltage source VS is disconnected from the voltage/current signal line 9. In addition, the current source CS is connected to the voltage/current signal line 9. In this state, the switches Sw5a, Sw5b, and Sw5e are closed. The switch Sw1 is kept open.
  • the output current Iout from the current source CS is set to not the current Isig corresponding to the video signal but a predetermined reset current Irst of, e.g., 100 nA. Accordingly, the gate-to-source voltage of the drive transistor Tr is set to a value Vcrct when the current Irst flows between the source and drain.
  • the first write period P3C is ended by opening the switches Sw5a and Sw5b.
  • the switch Sw5e is opened, as described about the mth row selection period.
  • the switch Sw5e may be opened at this time or simultaneously as the switch Sw5b is opened.
  • the switch SwC1 is opened, and the switches Sw1 and SwV1 are closed, as described about the mth row selection period.
  • the voltage signal Vout output from the voltage source VS is set to a voltage signal Vsig' almost corresponding to the video signal.
  • a node E is set to the potential Vsig'.
  • the second write period P3V is ended by opening the switch Sw1.
  • the potential of a node D is set to the value Vcrct when the current Irst flows between the source and drain of the drive transistor Tr. For this reason, when the potential of the node E is changed from V0 to Vsig' during the second write period P3V, the potential of the node D changes from Vcrct to Vcrct + Vsig" - V0.
  • the switch Sw2 is closed, as described about the mth row selection period.
  • a current having a magnitude almost corresponding to the potential Vcrct + Vsig" - V0 flows to the display element 20.
  • the switch SwC1 is closed, and the switch SwV1 is opened.
  • the driving method according to this embodiment is almost the same as in the fourth embodiment except that the power supply line 11 is used in place of the constant potential line 14. Hence, the same effect as described in the fourth embodiment can be obtained even in this embodiment.
  • the constant potential line 26 is used in place of the constant potential line 14 used in the fourth embodiment. Accordingly, the switch Sw5e need be arranged in each pixel 2. Instead, the current signal line 10 and the video signal line driver 5 shown in FIG. 12 can be omitted.
  • FIG. 15 is a plan view schematically showing a display according to the sixth embodiment of the present invention.
  • a display 1 shown in FIG. 15 is, e.g., an organic EL display.
  • the display 1 has the same structure as that of the display 1 shown in FIG. 14 except that scan signal lines 17 are omitted, and the gate of a switch Sw5e is connected to a scan signal line 8.
  • the switching operation of the switch Sw5e cannot be controlled independently of those of switches Sw5a and Sw5b.
  • the display can be driven by the same method as described in the fifth embodiment. Hence, even in this embodiment, the same effect as described in the fifth embodiment can be obtained.
  • the scan signal lines 17 are omitted. That is, according to this embodiment, the number of wiring lines can be reduced as compared to the fifth embodiment.
  • FIG. 16 is a plan view schematically showing a display according to the seventh embodiment of the present invention.
  • a display 1 shown in FIG. 16 is, e.g., an organic EL display.
  • the display 1 has the same structure as that of the display 1 shown in FIG. 15 except that the following arrangement is employed.
  • correction signal supply control switches Sw5f and Sw5g and scan signal lines 17 are arranged.
  • Each correction signal supply control switch Sw5f is connected between the output terminal of a correction signal supply control switch Sw5b and the gate of a drive transistor Tr. Switching of the correction signal supply control switch Sw5f is controlled by a scan signal supplied from a scan signal line 8.
  • the correction signal supply control switch Sw5g is connected between the output terminal of a correction signal supply control switch Sw5e and the electrode of a capacitor C1 on the side of the switch Sw5e. Switching of the correction signal supply control switch Sw5g is controlled by a scan signal supplied from the scan signal line 17.
  • a substrate 3 scan signal lines 6 to 8 and 17, voltage/current signal lines 9, power supply line 11, constant potential line 26, switches Sw1, Sw2, Sw5a, Sw5b, Sw5e, Sw5f, and Sw5g, drive transistors Tr, and capacitors C1 and C2 form an active matrix substrate.
  • This active matrix substrate can also include a scan signal line driver 4 and the like.
  • This active matrix substrate can also include one electrode of each display element.
  • the display 1 shown in FIG. 16 can be driven by the same method as described in the sixth embodiment. Hence, even in this embodiment, the same effect as described in the sixth embodiment can be obtained.
  • the switches Sw5a and Sw5b employ identical structures and are formed simultaneously. In this case, the switches Sw5a and Sw5b have the same threshold value in principle. In fact, the threshold value of the switches Sw5a and Sw5b may vary.
  • the switching operations are not simultaneously executed. For example, if the switch Sw5a is opened before the switch Sw5b is opened, the potential of a node D varies after the switch Sw5b is opened until the switch Sw5a is opened. That is, it may be difficult to sufficiently correct the characteristics of the drive transistor Tr.
  • switching of the switch Sw5f can be controlled independently of switching of the switch Sw5b.
  • the switch Sw5f can be opened before the switch Sw5b is opened. For this reason, any undesirable variation of the potential of the node D can be prevented.
  • the characteristic of the drive transistor Tr can reliably be corrected. This effect can also be obtained even when the switches Sw5b and Sw5g are not arranged.
  • the switches Sw5f and Sw5b are connected in series between the gate and drain of the drive transistor Tr.
  • the switches Sw5g and Sw5e are connected in series between the capacitor C1 and the constant potential line 26.
  • the write method is changed between display of a brighter gray level and display of a darker gray level.
  • the eighth embodiment employs a method of displaying all gray levels by using the method of displaying a darker gray level, which has been described in the fourth to seventh embodiments.
  • FIG. 17 is a plan view schematically showing a display according to the eighth embodiment of the present invention.
  • a display 1 shown in FIG. 17 is, e.g., an organic EL display.
  • the display 1 has the same structure as that of the display 1 shown in FIG. 11 except that the following arrangement is employed.
  • a selection switch Sw1 scan signal lines 6, and voltage signal lines 9 are omitted, and nodes E are connected to scan signal lines 8.
  • a video signal line driver 5 is omitted. Additionally, in the display 1, a voltage source VS and switches SwC1 and SwV1 of a voltage/current source 25 are omitted. More specifically, the output terminals of the voltage/current source 25 are connected to the voltage/current signal lines 9 so that the voltage/current source 25 is used as the video signal line driver.
  • a substrate 3 scan signal lines 7 and 8, current signal lines 10, power supply line 11, switches Sw2, Sw5a, and Sw5b, drive transistors Tr, and capacitors C1 and C2 form an active matrix substrate.
  • This active matrix substrate can also include a scan signal line driver 4 and the like.
  • This active matrix substrate can also include one electrode of each display element.
  • the display 1 is driven by, e.g., the following method independently of the gray level to be displayed.
  • the switch Sw2 is opened first. Within the period when the switch Sw2 is open, the first write operation and second write operation are sequentially executed.
  • a first write period P3C when the first write operation is executed, switches Sw5a and Sw5b are closed. In this state, an output current Iout from a current source CS is set to a current Isig' almost corresponding to a video signal. At this time, a potential V1 of the node E is constant independently of the gray level to be displayed. Accordingly, the gate-to-source voltage of the drive transistor Tr is set to a value Vsig' when the current Isig' flows between the source and drain.
  • the first write period P3C is ended by opening the switches Sw5a and Sw5b.
  • a second write period P3V when the second write operation is executed, the switches Sw5a and Sw5b are closed. At this time, a potential V2 of the node E is constant independently of the gray level to be displayed. The second write period P3V is ended when the node E stabilizes to the potential V2.
  • the potential of a node D is set to the value Vsig' when the current Isig' flows between the source and drain of the drive transistor Tr. For this reason, when the potential of the node E is changed from V1 to V2 during the second write period P3V, the potential of the node D changes from Vsig' to Vsig' - (V1 - V2).
  • the current signal Isig' is supplied between the source and drain of the drive transistor Tr as a video signal.
  • the potential of the node D is set to the value Vsig' corresponding to the video signal.
  • the current Isig' is larger than the current Isig.
  • the potential Vsig' faithfully reflects the characteristics of the drive transistor Tr. More specifically, according to this embodiment, not only the influence of a threshold value Vth of the drive transistor Tr but also the influence of its mobility and dimensions on the drive current can sufficiently be eliminated.
  • FIG. 18 is a plan view schematically showing a display according to the ninth embodiment of the present invention.
  • a display 1 shown in FIG. 18 is, e.g., an organic EL display.
  • the display 1 has the same structure as that of the display 1 shown in FIG. 17 except that the following arrangement is employed.
  • a correction signal supply control switch Sw5f and scan signal lines 17 are arranged.
  • the correction signal supply control switch Sw5f is connected between the output terminal of a correction signal supply control switch Sw5b and the gate of a drive transistor Tr. Switching of the correction signal supply control switch Sw5f is controlled by a scan signal supplied from the scan signal line 17.
  • a substrate 3 scan signal lines 7, 8, and 17, current signal lines 10, power supply line 11, switches Sw2, Sw5a, Sw5b, and Sw5f, drive transistors Tr, and capacitors C1 and C2 form an active matrix substrate.
  • This active matrix substrate can also include a scan signal line driver 4 and the like.
  • This active matrix substrate can also include one electrode of each display element.
  • the display 1 shown in FIG. 18 can be driven by the same method as described in the eighth embodiment. Hence, even in this embodiment, the same effect as described in the eighth embodiment can be obtained.
  • switching of the switch Sw5f can be controlled independently of switching of the switch Sw5b.
  • the switch Sw5f can be opened before the potential of a node E is changed to open the switch Sw5b. For this reason, any undesirable variation of the potential of a node D can be prevented.
  • the characteristics of the drive transistor Tr can reliably be corrected. This effect can also be obtained even when the switch Sw5b is not arranged.
  • the switches Sw5f and Sw5b are connected in series between the gate and drain of the drive transistor Tr.
  • FIG. 19 is a plan view schematically showing a display according to the 10th embodiment of the present invention.
  • a display 1 shown in FIG. 19 is, e.g., an organic EL display.
  • the display 1 has the same structure as that of the display 1 shown in FIG. 18 except that the following arrangement is employed.
  • scan signal lines 18 are arranged. Nodes E are connected not to scan signal lines 8 but to the scan signal lines 18.
  • a substrate 3 scan signal lines 7, 8, 17, and 18, current signal lines 10, power supply line 11, switches Sw2, Sw5a, Sw5b, and Sw5f, drive transistors Tr, and capacitors C1 and C2 form an active matrix substrate.
  • This active matrix substrate can also include a scan signal line driver 4 and the like.
  • This active matrix substrate can also include one electrode of each display element.
  • the display 1 shown in FIG. 19 can be driven by almost the same method as described in the ninth embodiment. Hence, even in this embodiment, the same effect as described in the ninth embodiment can be obtained. Even in this embodiment, the characteristic of the drive transistor Tr can reliably be corrected even when the switch Sw5b is not arranged.
  • potentials V1 and V2 of the node E can arbitrarily be set. Additionally, in this embodiment, the potential of the node E can be changed independently of switching of the switches Sw5a and Sw5b.
EP03777188A 2002-12-06 2003-12-03 Affichage, substrat a matrice active et procede d'excitation Withdrawn EP1580719A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2002355338 2002-12-06
JP2002355338A JP4131659B2 (ja) 2002-12-06 2002-12-06 表示装置及びその駆動方法
PCT/JP2003/015456 WO2004053825A1 (fr) 2002-12-06 2003-12-03 Affichage, substrat a matrice active et procede d'excitation

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EP1580719A1 true EP1580719A1 (fr) 2005-09-28
EP1580719A4 EP1580719A4 (fr) 2009-02-18

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JP (1) JP4131659B2 (fr)
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CN (1) CN1720566A (fr)
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WO (1) WO2004053825A1 (fr)

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US8525763B2 (en) 2005-08-26 2013-09-03 Semiconductor Energy Laboratory Co., Ltd. Display device and method of driving the same

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JP4517804B2 (ja) 2004-09-29 2010-08-04 カシオ計算機株式会社 ディスプレイパネル
JP4693009B2 (ja) * 2008-10-07 2011-06-01 奇美電子股▲ふん▼有限公司 アクティブマトリクス型ディスプレイ装置及びこれを備える携帯機器
US9080944B2 (en) * 2013-01-07 2015-07-14 Bruker Axs, Inc. Method and apparatus for surface mapping using in-plane grazing incidence diffraction
TWI527012B (zh) * 2014-07-03 2016-03-21 友達光電股份有限公司 發光二極體畫素電路及其驅動方法
JP2016075836A (ja) * 2014-10-08 2016-05-12 Ｎｌｔテクノロジー株式会社 画素回路、その駆動方法及び表示装置

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Publication number Priority date Publication date Assignee Title
US8525763B2 (en) 2005-08-26 2013-09-03 Semiconductor Energy Laboratory Co., Ltd. Display device and method of driving the same
WO2008123089A1 (fr) 2007-04-04 2008-10-16 Sony Corporation Procédé d'attaque d'une partie émettant de la lumière par électroluminescence organique
EP2133859A1 (fr) * 2007-04-04 2009-12-16 Sony Corporation Procédé d'attaque d'une partie émettant de la lumière par électroluminescence organique
EP2133859A4 (fr) * 2007-04-04 2010-04-07 Sony Corp Procédé d'attaque d'une partie émettant de la lumière par électroluminescence organique
US8094145B2 (en) 2007-04-04 2012-01-10 Sony Corporation Driving method for organic electroluminescence light emitting section
CN101681592B (zh) * 2007-04-04 2012-06-20 索尼株式会社 有机电致发光的发光部分的驱动方法
US8325176B2 (en) 2007-04-04 2012-12-04 Sony Corporation Driving method for organic electroluminescence light emitting section
US8907940B2 (en) 2007-04-04 2014-12-09 Sony Corporation Driving method for organic electroluminescence light emitting section

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KR20050087816A (ko) 2005-08-31
TWI235986B (en) 2005-07-11
EP1580719A4 (fr) 2009-02-18
KR100637824B1 (ko) 2006-10-24
JP4131659B2 (ja) 2008-08-13
JP2004191388A (ja) 2004-07-08
WO2004053825A1 (fr) 2004-06-24
CN1720566A (zh) 2006-01-11
TW200417982A (en) 2004-09-16

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