EP1574036A2 - Architecture de capteur d'image assurant la commande d'integration de charge par pixel - Google Patents

Architecture de capteur d'image assurant la commande d'integration de charge par pixel

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Publication number
EP1574036A2
EP1574036A2 EP00949865A EP00949865A EP1574036A2 EP 1574036 A2 EP1574036 A2 EP 1574036A2 EP 00949865 A EP00949865 A EP 00949865A EP 00949865 A EP00949865 A EP 00949865A EP 1574036 A2 EP1574036 A2 EP 1574036A2
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EP
European Patent Office
Prior art keywords
integration
charge
programming
unit cells
unit cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00949865A
Other languages
German (de)
English (en)
Inventor
Moshe Stark
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vision Sciences Inc
Original Assignee
Vision Sciences Inc
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Filing date
Publication date
Application filed by Vision Sciences Inc filed Critical Vision Sciences Inc
Publication of EP1574036A2 publication Critical patent/EP1574036A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/53—Control of the integration time
    • H04N25/533—Control of the integration time by using differing integration times for different sensor regions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/58—Control of the dynamic range involving two or more exposures
    • H04N25/581—Control of the dynamic range involving two or more exposures acquired simultaneously
    • H04N25/583—Control of the dynamic range involving two or more exposures acquired simultaneously with different integration times

Definitions

  • the present invention relates to image sensor array architecture generally and, in particular, to logic control thereof.
  • Image sensors are generally comprised of an array of sensing unit cells, wherein each unit cell comprises a pixel which is exposed to light, and produces an electrical response representative thereof.
  • each unit cell comprises a pixel which is exposed to light, and produces an electrical response representative thereof.
  • the minimal signal that can be detected by an image sensor is defined as the minimal incident light intensity on the pixel that results in a recognizable, meaningful response signal above the noise level. Signals with light intensity below the noise level are considered to act in the image sensor's cutoff region.
  • the maximum signal that can be detected by an image sensor is defined as the maximal incident light intensity on an image sensor's pixel that results in a recognizable non-saturated response. Signals with light sensitivity above this level are considered to be in the saturation range.
  • the region between the cutoff region and the saturation range is defined as the image sensor's sensitivity range.
  • Light signals with intensity in the image sensor's sensitivity range yield a response signal that corresponds to the incoming light intensity
  • the resolution and the minimum sensitivity determine the noise floor.
  • Dynamic range (DR) performance is described in terms of the ratio between the highest intensity and the lowest intensity range limits.
  • An image sensor's dynamic range is described in three equivalent ways.
  • the dynamic range is described as the ratio: (1) DRV ⁇ 10 n : 1 where DR ⁇ is the image sensor's dynamic-range performance and n is a positive number, normally rounded to an integer.
  • an image sensor with a dynamic range of 10 3 : 1 can capture signals that are up to thousand times larger than its minimum signal.
  • the second way of describing the dynamic range is in a logarithmic fashion, where:
  • the third way often used to describe the image sensor's dynamic range is by the number of bits required to describe the dynamic range in a binary number fashion. This number of bits is directly related to the dynamic range by the following formula,
  • N is the number of bits
  • Intg is a function that extracts the integer part of its argument.
  • the most desirable image sensor is one that imitates the human eye's performance and captures scenes with comparable performance to the human eye's retina.
  • the human eye's retina provides a dynamic range of 10 8 : 1
  • commercially available image sensor's "silicon retinas" provide a dynamic range that is typically only 10 3 : 1.
  • the silicon retina performs quite poorly.
  • Dynamic range is a central issue in image-sensor design research.
  • the basis for the research is the understanding of the workings of the human eye's retina.
  • the superb performance of the human eye's retina results from the fact that each retina's photoreceptor locally adjusts its sensitivity to the intensity of the incident light.
  • the individual photo receptors of the human eye's retina each have a dynamic range of less than 10 3 : 1 , the overall retina's performance is much better due to photoreceptor's capability to locally adjust its "quiescent point". Shifting the point of operation means that the photoreceptor, when exposed to a high intensity of light, reduces its sensitivity while, when exposed to a low light intensity, it increases its sensitivity.
  • charge-integration periods are acquired and then combined into a single image Typically the combination of several different-exposure images is done on the image sensor s video output
  • the image sensor's dynamic range is highly dependent on the column scan rate
  • Column-scan rate is limited by the programming rate of each column
  • each column program must be loaded in a single pixel time This can be done only with a very wide and fast bus that loads the row control register S G Chen and J P Lee discuss the use of flip-flops in their article
  • IPR Independent Pixel Reset
  • the method is limited in its scope since unit cells with the same exposure time are not reset simultaneously Therefore the unit cells at the upper left corner of the image sensor array are reset significantly sooner than the unit cells at the bottom right corner For instance, if the array is 768x483 lines and the reset is performed with a 67-nsec pixel clock, the time difference between the upper left corner reset and the lower right corner reset is 24 86 milliseconds, which is unacceptable for commercial video applications Hence, the method is not suitable for large arrays or for real-time 30 frames per second video rate
  • the exposure time of the sensor is limited to a few values, such as 1 , 1 / 2 , %, 1 / 8 , and 1/16 of the maximum integration time, which is unsatisfactory for real-time high quality imaging Hence, the IPR technique is currently unsuitable for most commercial applications SUMMARY
  • a sensor array that produces a captured image at the end of a time frame
  • the array includes a plurality of unit cells which sense the image with multiple within-frame charge-integrations, and control means which separately controls each of the unit cells
  • the unit cells are programmable multiple charge-integration unit cells with modes of photocurrent integration and non-integration
  • Each unit cell includes a photosensor, a charge-storage device for accumulating charge transfer from the photosensor, and a programmable memory unit for storing a charge-integration state of the unit cell
  • the control means includes means for separately controlling multiple charge-integrations in a single frame capture of each unit cell, independently of the charge-integrations of the other unit cells
  • the control means includes means for providing N charge-integration sub-periods within a single frame capture, where N is equal to or greater than 1 Within each single frame capture, the control means generally simultaneously individually integrates the charge of each unit cell within a group of cells Generally, the control means includes a row-select line and a column-select line The row-select line carries a multiplicity of first signals to the unit cells and the column-select line carries a multiplicity of second signals, such as program and sense signals, to the unit cells
  • control means also programs the unit cells A group of cells, such as a line of unit cells, is generally simultaneously programmed, preferably in a sequential order
  • the means for programming may also include means for sequentially programming one or more lines of the plurality of unit cells
  • the control means includes means for defining the charge-integration sub-periods where, alternatively, the charge-integration sub-periods are of various time lengths
  • the control means also includes means for providing fine time resolution in clock-time units and means for providing wide dynamic range of charge-integration steps Generally, the wide dynamic range is in the range of 2 N -1 unit steps of integration times
  • a method for sensing an image with a plurality of unit cells The method includes the steps of individually accessing each of the unit cells and controlling charge-integration of each unit cell, independently of the charge-integration of other of the plurality of unit cells
  • the method further includes the steps of determining the charge-integration time for each unit cell and programming each unit cell according to the determined charge-integration time
  • a method for improving the intra-scene dynamic range of an image-sensor array of multiple unit cells includes the steps of individually accessing and individually controlling each unit cell
  • the method also includes the step of individually controlling the charge-integration time of each of the unit cells, including individually programming such
  • the step of individually programming includes programming each unit cell according to a pre-determined charge-integration time and programming each unit cell with multiple charge-integration sub-periods
  • a programmable image sensor including a multiplicity of unit cells for capturing an image
  • the sensor includes a first plurality P of input lines for carrying data, a second plurality H of columns which are connected to the cells, wherein P is equal or smaller than H, and a controller for receiving the data and selectively distributing the data to the columns, to program N times the array, within a single frame of motion video
  • the data is programming data and includes charge-integration/non-integration state data for each of the plurality of unit cells
  • each of the plurality of programmable unit cells is individually controlled.
  • FIG. 1 is a schematic illustration of an image-sensor array architecture for implementation with non-interlaced video, constructed and operative in accordance with a preferred embodiment of the present invention
  • Fig 2 is a schematic illustration of an image-sensor unit cell that provides multiple integration sub-periods and is used with the architecture illustrated in Fig 1 ,
  • FIG 3 is a schematic illustration of a row-program loader used in the architecture illustrated in Fig 1 , and constructed and operative in accordance with a preferred embodiment of the present invention
  • Fig 4A and 4B are timing diagrams of single row programming when implemented with the architecture illustrated in Fig 1 ,
  • Fig 5 is a timing diagram of a programming sequence implemented with the architecture illustrated in Fig 1 ,
  • Fig 6 is a timing diagram of a programming/integration interval operative with the architecture illustrated in Fig 1
  • Fig 7 is a schematic illustration of an image-sensor array architecture for implementation with interlaced video, constructed and operative in accordance with an alternative preferred embodiment of the present invention
  • Fig 8 is a schematic illustration of an alternative image sensor unit that provides multiple integration sub-periods and is used with the architecture illustrated in Fig 7,
  • Fig 9 is a schematic illustration of a row-program loader used in the architecture illustrated in Fig 7, and constructed and operative in accordance with an alternative preferred embodiment of the present invention
  • Fig 10A and 10B are timing diagrams of single-row programming implemented with the architecture of Fig 7 .
  • Fig 11 is a timing diagram of even-row programming implemented with the architecture of Fig 7
  • Fig. 12 is a timing diagram of an interlaced readout, program and integration cycle implemented with the architecture of Fig. 7.
  • CMOS image sensor architecture and method that facilitates independent control of the charge-integration time of each pixel
  • autonomous per-pixel exposure control is accomplished via direct and independent control of the pixel's charge-integration time
  • the present invention describes two novel image-sensor architectures, for utilization in both interlaced and non-interlaced video
  • the image- sensor architectures incorporate a multiplicity of image-sensor unit cells that are capable of multiple charge-integration sub-periods, and preferably, the architectures provide for individual charge-integration time per pixel
  • Implementation of the present invention facilitates programming the charge integration time in numerous, various-timed, small steps As a result, hundreds, or even thousands of exposure-time values are available This is important for an effective implementation of dynamic range compression, and elimination of quantization noise and image artifacts Hence, exposure times in the range of 2 10 1 in unit steps are feasible for motion video This is instrumental for accomplishing wide dynamic-range scene capture roughly comparable in performance to the human eye s retina Furthermore via novel use of a row-program loader the present invention provides for simultaneous different charge-integration intervals for all the pixels The present invention describes loading an entire row program, one row at a time, at video rate Furthermore, this operation is done outside the image sensor's array Reference is now made to Fig 1 an illustration of array 10, a novel and improved non-interlaced type CMOS image-sensor array architecture that comprises a plurality of unit cells 12 and implements autonomous, per-pixel, charge-integration control
  • unit cell 12 the basic building block of array 10 Unit cell 12 captures light and produces electrical signals associated therewith
  • unit cell 12 is capable of multiple-integration sub-periods, as is the unit cell described in patent application PCT/1 LOO/00129, CMOS Unit Cell with Autonomous/Per-Pixel Charge Integration Time Control Circuit, filed on March 2, 2000
  • PCT/1 LOO/00129 is co-pending to the same assignees as the invention presented herein, and is incorporated herein by reference
  • reference to a "unit cell” is synonymous with reference to a "pixel”
  • integration is synonymous with charge-integration
  • All the unit cells 12 in array 10 undergo a programming cycle, in a manner to be explained in detail hereinbelow, wherein they are preprogrammed for a predetermined integration interval Each such programming cycle is followed by the predetermined integration interval Each such predetermined integration cycle may comprise a series of integration sub-periods and/or a series of non-integration sub-periods At the completion of the integration interval the unit cell 12 is read out The procedure of reset, programming cycle, integration cycle, and readout is repeated An integration interval is defined as the period of time from reset to readout
  • the preprogrammed unit cell 12 injects charge into an integration capacitor which resides in unit cell 12 During the non-integration sub-periods, the integration capacitor stores the collected charge, but the preprogrammed unit cell 12 does not inject additional charge into the capacitor
  • the integration and non-integration sub-periods may be multiple and alternate between integration and non-integration, depending on the predetermined programmed cycle
  • unit cell 12 During the integration interval, all the unit cells 12 that are primarily enabled for charge integration are "exposed" to the light intensity It is noted that although the integration interval is the same for all unit cells 12, the charge collected during this period differs from unit cell 12 to unit cell 12
  • the charge accumulated per unit cell 12 is proportional to the effective charge-integration time (i e the summation of the various integration sub-periods for each pixel) and to the local intensity of the incident light
  • Unit cell 12 retains the so-far accumulated charge on its integration capacitor, as long it is not actively discharged. In such a manner, unit cell 12 functions as an analog memory element which retains analog signals.
  • each unit cell 12 is dependent on its associated sequence of programmed states of integration/non-integration, such that each sub-period is subject to a different charge integration.
  • PCT/1 L00/00129 Based upon PCT/1 L00/00129, and for the special case where,
  • T m is the Int signal staying "high” in the i-th integration sub-period
  • q is the number of program/integration sub-periods in the sequence
  • the integration interval is programmable through the binary number (u q- ⁇ u q-2 ... u 2 ui Uo) 2 -
  • (u q-1 u q-2 ... u 2 U T u 0 ) 2 is (0 0 ... 0 1 ) 2 T
  • (min) T 0 is the shortest possible integration time.
  • T m a x is the maximum integration time
  • q is the number of program/integrate sub-periods
  • the integration time can be any value starting with T 0 , 2T 0 , 3T 0 , ... , in T 0 steps, and up to T max .
  • the collected charge or the corresponding voltage is proportional to the total integration time, and to the photocurrent magnitude.
  • the photocurrent itself is proportional to the intensity of the incident light.
  • C ⁇ is the Integration Capacitor's capacitance
  • Q a is the accumulated charge on the Integration Capacitor
  • V c is the voltage across the Integration Capacitor.
  • array 10 comprises an array of lines, arranged in rows along the x-axis and columns along the y-axis.
  • Unit cells 12 are located at the x, y nodes of the lines, and connected thereto.
  • the lines carry electrical signals that control the integration interval of each unit cell 12.
  • Array 10 additionally comprises a multiplicity of circuits located on the horizontal and vertical axis, respectively.
  • a readout circuit 14 and a row program loader 18 are located along the horizontal or y-axis
  • a row program/read decoder 16 is located along the vertical or x-axis. It is noted that the usage of the terms vertical and horizontal are for purposes of clarity, and alternative locations of these circuits are included within the scope of the present invention.
  • the array of lines includes lines generally designated row-read (RwRd) lines, row-program (RwPrg) lines, column sense (ColSense) lines, column program (ColPrg) lines, reset (Rst) lines, and integration (Int) lines
  • Each line carries an associated signal, i e the RwRd line carries a RwRd signal and so on
  • the Int (i e integration) line is one line that splits into multiple lines and is connected to all unit cells 12
  • the Int line carries the Int signal All unit cells 12 are subject to integration controlled by the Int signal Preferably, when the Int signal is high, charge integration takes place During the integration sub period (when the Int signal is high), those associated unit cells 12 that have been programmed to integrate, do so
  • the Rst (i e reset) line is one line that splits into multiple lines and is connected to all unit cells 12
  • the Rst lines carry a Rst signal which drives all the unit cells 12 in array 10 to reset simultaneously
  • the Rst signal activates a transistor that resides in unit cells 12 that drains the residual charge which remained after the previous readout, thereby preconditioning the integration capacitors for the next integration interval
  • RwRd lines In a preferred embodiment, the RwRd (i e row-read) lines are connected to the row program/read decoder 16, and the location designations of the RwRd lines range from RwRd_0 to RwRd_V-1 Each RwRd line is connected to the associated unit cells 12 on its respective row.
  • RwRd lines carry a row read (RwRd) signal that controls the readouts of the associated unit cells
  • RwRd_ ⁇ signal When the RwRd_ ⁇ signal is high and all the other RwRd signals are low, the content of the unit cells 12 ( ⁇ ,j) is read Typically, unit cells 12 are readout after the completion of the charge integration cycle
  • RwPrg lines In a preferred embodiment, the RwPrg (i e row-program) lines are connected to the row program/read decoder 16, and the location designations of the RwRd lines range from RwPrg_0 to RwPrg_V-1 Each RwPrg line is connected to all the associated unit cells 12 on its respective row
  • the RwPrg lines carry a row program (RwPrg) signal that controls the programming of the associated unit cells 12
  • the programming of the unit cells 12 determines the charge integration sequence for each unit cell 12 Preferably, programming is done in a row-by-row fashion, i e , when the RwPrgj signal is high and all other RwRd signals are low, the unit cells 12 in row i are programmed
  • RwRd signal and the RwPrg signal function in tandem with each other When the RwRd signal is high, the RwPrg signal is low, and visa versa
  • RdEn and PrgEn signals The RwRd signal activates a RdEn (i e read-enable) signal that enables the readout of the accumulated charge
  • the RwPrg signal activates a PrgEn (i e program-enable) that enables the programming of the associated unit cell 12
  • ColSense and ColPrg lines run between row program loader 18 and readout circuit 14
  • the ColSense lines and ColPrg lines are alternatively active, when the ColSense line is active - the ColPrg line is inactive, and visa versa As such, the same physical line is usable for both functions
  • the ColSense lines and the ColPrg lines are separate physical lines The location designations of the ColSense/ColPrg lines range from ColSense_0/ColPrg_0 to ColSense_H-1/ColPrg_H-1
  • Each ColSense/ColPrg line is connected to all the associated unit cells 12 on its respective column
  • the ColSense/ColPrg lines are common for programming and reading, and carry a ColSense/ColPrg signal
  • ColSense/ColPrg signal is a multiplexed input/output signal that alternatively acts as an input signal during the charge integration interval, and as an output signal during the read cycle
  • the ColSense/ColPrg lines serve as ColPrg_0/ColPrg_V-1 lines and provide the ColPrg signal, which is actively driven by row program loader 18
  • the value of the ColPrg signal determines whether the unit cell 12 will integrate or not integrate the photocurrent charge during the next integration sub-period
  • unit cell 12 When the ColPrg signal is low, unit cell 12 is preprogrammed to disable charge integration Conversely, when the ColPrg signal is high, unit cell 12 is preprogrammed to enable charge integration Alternatively, unit cell 12 can be programmed to respond to the opposite polarity of the ColPrg signal
  • the ColSense/ColPrg lines serve as ColSense_0/ ColSense_H-1 lines and provide the ColSense signal
  • the outputs of row program loader 18 are t ⁇ stated, and readout from the associated unit cells 12 is enabled, providing readout signals to readout circuit 14
  • Row program/read decoder 16 Decoder 16 selects one or more of the RwRd lines and activates the RwRd signal, which enables readout of the charge accumulated in the associated unit cell 12 In a preferred embodiment, the readout phase of the selected unit cell 12 occurs when the RwRd signal is high, and simultaneously the RwPrg signal is low and no row programming is occurring
  • row program/read decoder 16 activates a predetermined combination of line address (RwAdr) input signals
  • RwAdr line address
  • the combination of RwAdr signals creates a binary combination representative of the number "z"
  • the RwRd lines are inactive, and the RwPrg lines are active, thereby allowing programming of the unit cells 12 in array 10, row-by-row.
  • a predetermined combination of RwAdr input signals is activated for designation of the appropriate row for programming.
  • row program/read decoder 16 selects one of the RwPrg lines.
  • a dynamic type of row program/read decoder 16 is suggested, and as such, a row clock (RwClk) signal is used for the internal decoder precharge.
  • the precharge occurs before every row selection.
  • Internal precharge results in the deselection of all RwRd lines and RwPrg lines by pulling all the lines to low. It is noted that other selection/deselection timing mechanisms are feasible and within the scope of the present invention.
  • Readout circuit 14 enables the readout of collected charge from each unit cell 12 in array 10.
  • Readout circuit 14 typically comprises one sense amplifier (not shown) per each ColSense line, or column.
  • the sense amplifiers sense the electrical signal, (either charge, voltage, or current) from the read-out unit cells 12, and convert the sensed signal into a more robust video signal.
  • the RwRd signal enables readout on a row by row basis, thus enabling the sense amplifiers to readout the unit cells 12 row by row.
  • the output from each sense amplifier is then time multiplexed to the output of the readout circuit.
  • the signal representative of each of the collected charges is converted to video signals V ou t that are sequentially output through an output buffer 34
  • readout circuit 14 the video output could be demultiplexed, and readout simultaneously via several video outputs to speed-up the pixel video readout process
  • different readout architectures and different output sequences are implementable For instance, to speed up the readout, several pixels can be output at the same pixel period
  • Row program loader 18 facilitates programming each of the unit cells 12 to an integrate/non-integrate state
  • row-program loader 18 is loaded from a program memory, or from a charge-integration program generator, not shown This memory or charge-integration program generator is either part of array 10 or resides outside of the architecture and is input to the program loader 18
  • a single-row program is loaded into the internal memory of row-program loader 18 via a plurality of external input lines 28
  • the input pin of each input line 28 is connected to one of a plurality of shift register inputs 30, which are used to shift the row program in
  • Each shift register 30 comprises k (or r) stages 31
  • each shift stage 31 is a D type flip-flop, where in Fig 3, an input to stage 31 is generally designated as D, an output is generally designated as Q, and a clock input is generally designated as CK
  • array 10 comprises p shift registers 30
  • H is the number of ColPrg lines in the array (and also the total number of stages 31)
  • p is the number of input lines 28 to the row program loader 18 (and also the number of shift registers 30)
  • p is the number of input lines 28 to the row program loader 18 (and also the number of shift registers 30)
  • p is the number of input lines 28 to the row program loader 18 (and also the number of shift registers 30)
  • Example 1 In one preferred implementation of row-program loader 18, there are
  • the p input lines 28 connect to
  • the last shift register 30 which has r stages 31 , where r is less than or equal to k Therefore, to synchronize the operation with other p-1 shift registers 30, the data for the last shift register 30 must start with k-r garbage/don't care information bits followed by r information
  • T LdRw lntg(H/p +1 ) T p ,
  • T p (the clock time period) is 17 46 nsec thus T LdRw , the time to load an entire line is 419 04 nsec
  • a line register LR preferably comprises of a series of D type flip-flops
  • the data, or program, stored in the line register LR is transferred via a row load (LdRw) line to a set of H t ⁇ state buffers 32
  • Each tnstate buffer 32 drives an associated ColPrg line, enabling programming of the associated column
  • the value of the ColPrg signal determines whether the unit cell 12 will integrate or not integrate the photocurrent charge during the integration/non-integration sub-period
  • the data loaded by the buffers 32 to the ColPrg line is a series of values (0s and 1 s) that determine the next integration/non-integration sub-period, of the associated unit cells 12
  • T Prg V lntg(H/p +1 ) - T p ,
  • FIGs. 4A and 4B timing diagrams illustrating a single line of programming as performed by row-program loader 18. It is noted that the signals depicted in Figs. 4A and 4B are received from, or act upon, the hardware depicted in Fig. 3. As such, it is noted that the reference names are similar, i.e. XfrRw (i.e. transfer-row) line sends a XfrRw signal, and input lines 28 send input data signals.
  • XfrRw i.e. transfer-row
  • the top line of Fig. 4A depicts the program clock (PrgClk) pulse.
  • PrgClk program clock
  • each input line 28 loads an associated shift registers 30 with k stages 31.
  • each input line 28 has loaded k stages 31.
  • Fig. 4A depicts only four such input signals, associated with four input lines 28.
  • the present invention entails the appropriate number of input signals for the relevant number of input lines 28 which feeds the row loader 18
  • a transfer row (XfrRw) signal (Fig 4B) releases connection from the row which has just completed programming and connects to the next row designated for programming
  • the XfrRw signal is preferably an externally controlled signal
  • the row load (LdRw) line then releases a LdRw signal that enables the buffers 32 during programming
  • the LdRw signal loads row ⁇ -1 Depicted simultaneously with the LdRw signal, is the ColPrgj signal, the RwAdr signal and a RwPrg signal
  • the ColPrg signal is the data sent to the specific row via the buffers 32
  • the ColPrg signal contains the data specifying the program instructions for the associated column i e the ColPrgj signal contains the programming instructions for the column j
  • the RwAdr signal contains the address of the row to be loaded, and causes the data to be loaded to the appropriate row
  • the RwPrg signal contains the data specifying the program instructions for appropriate associated row
  • array 10 is set up as a matrix of columns and rows
  • Row loader 18 loads data for a selected row and programming information is sent for all the columns that intercept that row Consequently, the unit cells 12 that are affected are the pixels of that selected row
  • Fig 5 details the timing diagram of one programming sequence of the entire array 10
  • the top line of Fig 5 depicts a Prg signal, which remains high during a time period T prg , which is a composite of multiple time periods T LdR w, as defined in connection with Fig 3 and equation 13
  • Tp rg is the time period required for one programming sequence of the entire array 10
  • a series of XfrRw signals goes high releasing a series of rows designated to be programmed Simultaneously with the fall of each XfrRw signal, the associated LdRw signal goes high Thus, when XfrRw signal releases row 0, the LdRw signal 0 goes high, thereby preparing row 0 to receive the line register data With each commencement of a LdRw signal, all the ColPrg signals and the RwAdr signal change states, performing their appropriate tasks as described in Fig 4
  • FIG 6 a timing diagram of the programming and integration sequences of array 10 Array 10 is programmed and integrated q times, whereas each integration sub-period T q is preceded by programming of the entire array 10
  • each programming sequence is followed by an integration sub-period
  • the integration sub-period is halved in every cycle, as such, the second integration sub-time T q 2 is half the time of the first integration sub-period T q
  • Each unit cell 12 is subject to integration as governed by a unique set of U m programming coefficients, defined by a coefficient vector (u q- ⁇ u q-2 u 2 Ui u 0 ) 2 It is noted that the programming coefficients u m define the state of integration or non-integration for each preprogrammed integration sub-period T m , such that if u m ⁇ s high (1 ), integration takes place, and if u m is low, integration does not take place
  • each unit cell 12 is subject to a unique and autonomously defined charge integration, i e charge integration time As illustrated in Fig. 6, when the Rst signal goes high the single frame programming/integration/readout commences. The Rst signal is immediately followed by the first array programming cycle.
  • the most significant programming coefficients u q-1 ⁇ J are programmed into the respective unit cells 12.
  • the first array programming is followed by charge integration over the entire array 10.
  • additional charge is accumulated in the integration capacitor, and retained until the next charge integration.
  • the integration time for each pixel is different, and governed by the programming coefficients u m as defined by formula (6). It is noted that although herein the integration sub-period T m varies from longest to shortest, other variations of timing schedules are also applicable within the scope of this invention.
  • the programming/integration interval is followed by the image sensor array readout. If, T is the total integration time
  • T Rd is the image sensor readout time
  • Tp rg is the total programming time
  • T FR is the time allocated to a single frame
  • q is the number of program/ integration cycles
  • T FR T + q - T Prg + T Rd
  • T FR T + q - T Prg + T Rd
  • q 10 program/integrate cycles
  • T Rd 8 msec for image sensor readout
  • T 23 31 msec for integration
  • each pixel it is possible for each pixel to be individually and autonomously programmed with a wide range of charge-integration times, programmed in time unit steps This is instrumental in the capture of wide dynamic range scenes and furthermore important for the elimination of quantization noise
  • the time consumed by the programming can be designed to become reasonably short and therefore to slightly affect the maximum integration time
  • Another useful aspect of the present invention is a wide charge-integration time dynamic range (DR T ) If the charge-integration time dynamic range (DR T ) is defined as,
  • the integration-time dynamic range DR T parameter is the one of the keys to accomplishing high dynamic ranges of the artificial retina A wider program-load bus and/or a faster program clock enable more program/integration cycles, and therefore a wider integration time dynamic range
  • array 10 provides a multiplicity of 5 programming and charge-integration sub-periods within a single integration interval (or equivalently within a single frame)
  • the presented case of a circuit working at about 60 MHz program clock can be accomplished with the current state-of-the-art CMOS technologies
  • the ⁇ o programming is done via the row-program loader 18, which is outside array 10, the circuit must be carefully isolated, and uncoupled from the array For instance an appropriate guard ring around the row-program loader's 1 8 layout could help to accomplish this goal Interlaced image sensor
  • TV-format image sensors usually operate in an interlaced mode In the interlaced mode, the frame output is divided into two fields In the first field period the lines 0, 2, 4, are read out In the second period lines 1 , 3, 5, are read
  • the readout timing is compliant with the TV-format timing whether this is an NTSC, or a PAL format
  • the 0 program/integrate cycles are performed on one field, while readout is performed on the other
  • FIG. 7 is a block diagram of image-sensor array 50
  • Fig 8 depicts a unit cell 52, which is used in array 50
  • Elements similar to array 10 are similarly labeled and will not be described further
  • image sensor array 50 has H ColPrg/ColSense columns, and V RwPrg/RwRd lines (rows), where V is0 assumed to be odd
  • V is0 assumed to be odd
  • the odd ColPrg lines are programmed simultaneously with the readout of the even ColSense lines
  • unit cell 52 requires that the
  • ColPrg lines be separated from the ColSense lines.
  • Image sensor array 50 comprises two row-program/read decoders 16E and 16D. While one line decoder controls the readout, the other controls the programming, and vice versa.
  • Row-program/read decoder 16E controls the even read (RwRd) and program (RwPrg) lines. During a read cycle, decoder 16E generates even RwRd lines, such as, RwRd_0, RwRd_2, RwRd_4, RwRd_6 During the program/integrate cycles, decoder 16E generates even RwPrg lines, such as,
  • RwPrgj RwPrg_2, RwPrg_4, RwPrg_6 and so on.
  • decoder 16E The operation of decoder 16E is controlled by a plurality of signals, a read-even (RdEven) signal and a program-even (PrgEven) signal.
  • RdEven read-even
  • PrgEven program-even
  • the unit cells 52 on the even RwPrg lines are activated.
  • RdEven, and PrgEven are both low, the RwRd and RwPrg lines from decoder 16E are all low, and therefore inactive.
  • Row-program/read decoder 16D controls the odd read, and program lines. During a read cycle, decoder 16D generates the odd read lines, such as,
  • decoder 16D generates the odd program lines, such as RwPrg_1 , RwPrg_3,
  • the operation of decoder 16D is controlled by a plurality of signals, a read-odd (RdOdd) signal and a program-odd (PrgOdd) signal.
  • RdOdd read-odd
  • PrgOdd program-odd
  • the unit cells 52 on the odd RwRd lines are activated.
  • the RwRd and RwPrg lines of decoder 16D are all low and therefore inactive.
  • the RdEven signal is in opposite polarity to the RdOdd signal
  • the PrgEven signal is in opposite polarity to the PrgOdd signal
  • readout circuit 14 alternately reads unit cells 52 on the even and odd numbered RwRd lines Preferably, the unit cells 52 on the even numbered RwRd lines are read first, and then the unit cells 52 on the odd numbered RwRd lines
  • an integrate-even (IntEven) signal activates integration of unit cells 52 on the even Int lines
  • the IntEven signal is inactive during the readout of the unit cells 52 on the even RwRd lines
  • a reset-even (RstEven) signal activates reset of unit cells 52 on the even Rst lines
  • the Rst signal is inactive during the readout of the unit cells 52 on the even RwRd lines
  • An integrate-odd (IntOdd) signal and a reset-odd (RstOdd) signal perform similar functions for the unit cells 52 on the odd lines
  • FIG. 9 an illustration of row-program loader 58, Fig 10, a timing diagram depicting the single row-programming utilization of loader 58, and Figure 1 1 , a timing diagram of even-field lines programming Elements similar to previous embodiments are similarly labeled and will not be described hereinbelow
  • Fig 9 the flow depicted in Fig 9 is similar to that depicted in Fig 3, and functions similar to that described hereinabove in reference to Fig 3
  • unit cell 52 has separate ColPrg lines and ColSense lines, and hence t ⁇ states are not required and thus not depicted in Fig 9
  • the timing depicted in Figs. 10 and 1 1 is similar to that depicted in Figs. 4 and 5, respectively, and functions similar to that described hereinabove in reference to those figures.
  • Fig. 1 1 illustrates both a PrgEven signal and a PrgOdd signal
  • Fig. 5 depicts only a Prg signal. Nevertheless, while the
  • PrgEven signal is high, the PrgOdd signal is low, and visa versa, and thus the appropriate high signal (PrgEven signal) functions similarly to that of the Prg signal as described in connection with Fig. 5, and is thus applicable to Fig. 1 1.
  • the programming cycle for the odd-row field is similar to the even-row field, although if the total number of lines is odd, it may be a bit shorter since there is one line less to program
  • Example 6 For the case described in Examples 3 and 4, but for an interlaced readout image sensor. Based upon formula (20) it takes 101.40768 ⁇ sec to program the array's even-row field.
  • Fig. 12 a timing diagram of the programming and integration cycle of array 50 for interlaced readout. Note that the even and odd fields are programmed in tandem, one after the other.
  • Example 7 Image sensor similar to the one described Example 3, and in Example 5 but of interlaced readout type is subject to 10 program/integrate cycles
  • the frame rate is 30 frames per second, and the field rate is 60 fields per second
  • T FL 16 666 msec
  • the time consumed by 10 program cycles is 1 014 msec, which leaves 15 652 msec for integration Since there 10 cycles, there are 1023 different charge integrations possible, and stepped up to 15 652 msec

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

La présente invention porte sur un réseau de capteurs qui produit une image saisie à la fin d'une base de temps. Le réseau comprend une pluralité de cellules individuelles qui détectent l'image au moyen de plusieurs intégrations de charge dans les limites de la base de temps et un système de commande qui commande séparément chaque cellule individuelle. Les cellules individuelles sont des cellules individuelles à plusieurs intégrations de charge programmables ayant des modes d'intégration et de non intégration du photocourant. Le système de commande comprend un moyen qui permet de commander plusieurs intégrations de charge dans une seule saisie de base de temps de chaque cellule individuelle, indépendamment des intégrations de charge des autres cellules individuelles.
EP00949865A 1999-07-29 2000-07-24 Architecture de capteur d'image assurant la commande d'integration de charge par pixel Withdrawn EP1574036A2 (fr)

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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4969792B2 (ja) * 2005-04-14 2012-07-04 浜松ホトニクス株式会社 固体撮像装置
WO2007031808A1 (fr) * 2005-09-14 2007-03-22 Nokia Corporation Systeme et procede destines a mettre en oeuvre une stabilisation d'image en mode rafale commandee par mouvement
US7956914B2 (en) 2007-08-07 2011-06-07 Micron Technology, Inc. Imager methods, apparatuses, and systems providing a skip mode with a wide dynamic range operation
CA2709969C (fr) * 2007-12-21 2015-11-03 Photonis Netherlands B.V. Reseau de detecteur d'image, reseau de detecteur d'image intensifie, dispositif de reseau de detecteur d'image a bombardement electronique ainsi qu'element sensible de pixel pour une utilisation dans un tel reseau de detecteur d'image
JP2012175234A (ja) 2011-02-18 2012-09-10 Sony Corp 撮像装置、撮像素子、および撮像制御方法、並びにプログラム
EP2547097A1 (fr) * 2011-07-15 2013-01-16 Thomson Licensing Procédé de commande d'un capteur d'images électronique
US9723233B2 (en) 2012-04-18 2017-08-01 Brightway Vision Ltd. Controllable gated sensor

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5795771A (en) * 1980-12-05 1982-06-14 Fuji Photo Film Co Ltd Solid-state image pickup device
US4635126A (en) * 1981-12-18 1987-01-06 Canon Kabushiki Kaisha Image pick-up system
US4583002A (en) * 1983-06-06 1986-04-15 Fuji Photo Film Co., Ltd. Imaging sensor with automatic sensitivity control comprising voltage multiplying means
JPS62112491A (ja) * 1985-11-11 1987-05-23 Nippon Kogaku Kk <Nikon> 固体撮像素子の駆動方法
JP2920924B2 (ja) * 1989-01-12 1999-07-19 ソニー株式会社 Ｃｃｄカメラ
US5576762A (en) * 1990-11-07 1996-11-19 Canon Kabushiki Kaisha Solid-state image pickup device
KR100281788B1 (ko) * 1992-03-18 2001-02-15 이데이 노부유끼 고체 촬상 장치
EP0583143B1 (fr) * 1992-08-10 2001-04-18 Sony Corporation Amélioration du contrôle du temps d'un obturateur électronique dans une caméra vidéo
US5452004A (en) * 1993-06-17 1995-09-19 Litton Systems, Inc. Focal plane array imaging device with random access architecture
JP3088591B2 (ja) * 1993-06-17 2000-09-18 松下電器産業株式会社 固体撮像装置および駆動方法
JPH077651A (ja) * 1993-06-18 1995-01-10 Sony Corp 露光制御回路
JPH08298624A (ja) * 1995-04-25 1996-11-12 Sony Corp Ｃｃｄ撮像装置
JP3360512B2 (ja) * 1996-01-09 2002-12-24 ソニー株式会社 固体撮像素子およびその読み出し方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0110110A3 *

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