EP1547088A1 - Systeme de commande des changements de mode dans un convertisseur abaisseur de tension - Google Patents

Systeme de commande des changements de mode dans un convertisseur abaisseur de tension

Info

Publication number
EP1547088A1
EP1547088A1 EP03754491A EP03754491A EP1547088A1 EP 1547088 A1 EP1547088 A1 EP 1547088A1 EP 03754491 A EP03754491 A EP 03754491A EP 03754491 A EP03754491 A EP 03754491A EP 1547088 A1 EP1547088 A1 EP 1547088A1
Authority
EP
European Patent Office
Prior art keywords
transistor
charge
stand
node
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03754491A
Other languages
German (de)
English (en)
Other versions
EP1547088A4 (fr
Inventor
Stefano Sivero
Riccardo Riva Reggiori
Fabio Tassan Caser
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from IT000794A external-priority patent/ITTO20020794A1/it
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of EP1547088A1 publication Critical patent/EP1547088A1/fr
Publication of EP1547088A4 publication Critical patent/EP1547088A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

Definitions

  • the invention relates to voltage converters. More particularly, the invention relates to the management and control of an on-chip voltage down-converter that steps down an external power supply to a lower, internal power supply for memory devices.
  • Microprocessors typically operate at higher voltage levels than memories, for example.
  • the voltage from the external power supply must be down-converted.
  • FIG. 1 illustrates one example of a prior art voltage down-converter.
  • Amplifier 2 drives the gate of p-channel metal-oxide semiconductor (MOS) transistor 4.
  • MOS metal-oxide semiconductor
  • the source of transistor 4 connects to external power source 6 and the drain of transistor 4 connects to load circuit 8.
  • the voltage across load circuit 8 drops as current consumption in circuit 8 increases, and when the voltage drops below that of reference generator circuit 10 then amplifier 2 lowers the voltage across the gate of transistor 4.
  • Transistor 4 increases in conductivity as its gate voltage decreases and consequently supplies load circuit 8 with current.
  • FIG. 2 illustrates another example of a prior art voltage down-converter.
  • N-channel MOS transistor 20 has a low threshold voltage and is configured as a source follower.
  • driver transistor 20 is a natural MOS built on a substrate without a special implant and with a very large aspect ratio (W/L).
  • Replica transistor 22 is coupled to driver transistor 20 and has a smaller aspect ratio than transistor 20.
  • Amplifier 24 and resistors 26 complete a control loop with transistor 22.
  • Amplifier 24 controls the gate of transistor 22 and keeps the voltage at node 28 in a desired range. Consequently transistor 20 provides current through node 30 when voltage at node 28 drops below a predetermined level.
  • FIG. 3 illustrates a more detailed version of the voltage converter in FIG. 2.
  • Replica circuit 40 has a similar function to that of transistor 22 in FIG. 2.
  • Stand-by circuit 42 and active circuit 44 perform the function of driver transistor 20 in FIG. 2.
  • the prior art voltage converter in FIG. 3 has two operation modes: stand-by and active. In stand-by mode, current leakage to the load is very low. In active mode the transistors are on and provide up to the maximum level of current.
  • the invention provides a system to manage the switching between active to stand-by transition and stand-by to active transition.
  • the system to manage switching between active and stand-by and stand-by to active modes has two transitions.
  • the first transition is the stand-by to active transition.
  • the load current for the internal, stepped- down power is initially furnished by a load capacitor, acting as a charge tank, on the internal power node.
  • a replica transistor for the active mode Prior to entering active mode, a replica transistor for the active mode is biased to charge a capacitor.
  • a switch biases the driver transistor to the node with the capacitor that was charged by the replica transistor, thus activating the driver transistor and increasing the current to the load circuit.
  • the second transition of the system is the active to stand-by transition.
  • the transition is indicated by the fall of an enable signal.
  • a delay signal is interjected between the fall of the enable signal and the time at which stand-by mode is entered.
  • the delay signal provides time for a driver transistor gate to be discharged and a node to be charged towards stand-by values.
  • Comparators charge and discharge the gate and node as long as the delay signal is high.
  • a switch disconnects the driver transistor from the power supply node when the enable signal falls so that current stops flowing from the driver transistor while the comparator discharges the gate of the driver transistor.
  • the system enters stand-by mode at the end of the delay signal.
  • FIG. 1 is a schematic diagram of a prior art voltage down-converter.
  • FIG. 2 is a schematic diagram of a prior art voltage down-converter.
  • FIG. 3 is a more detailed schematic diagram of the prior art voltage down-converter in FIG. 2
  • FIG. 4 is a schematic diagram of one part of a voltage down-converter system for transition from stand-by to active modes.
  • FIG. 5 is a diagram of timing signals used for transition from active to stand-by modes.
  • FIG. 6 is a detailed schematic diagram of the system in FIG. 4 including circuitry for transition from active to stand-by modes.
  • FIG. 7 is a flow diagram illustrating a method of transitioning from active to stand- by modes according to one embodiment of the invention.
  • FIG. 4 is a schematic diagram illustrating one embodiment of the invention.
  • Circuit 50 replaces active circuit 44 of FIG. 3 and is provided to illustrate the transition from standby to active mode.
  • Transistor 52 serves as a replica transistor while transistor 54 serves as a driver.
  • External power supply 56 couples to both transistors 52 and 54. In stand-by mode, switches 58, 60 and 62 are off, while switch 64 is on.
  • Transistor 52 is biased by current from transistor 66 and charges node 68, which in one embodiment includes capacitor 70, to approximately 2V. In one embodiment capacitor 70 is 400pF. Node 72 is kept one threshold lower, or approximately 800 mV. The gate of transistor 54 is therefore 800mV lower than its source, which is coupled to internal voltage source NCC 74, and therefore off. Additionally, switch 62 prevents current from flowing through transistor 54 to the load circuit (not shown).
  • transistors in the invention are p-channel MOS transistors.
  • Switches 58, 60 and 62 are turned on and switch 64 turns off in order to transition to active mode.
  • Transistor 54 is decoupled from node 72 and is coupled to node 68, which is at approximately 2V.
  • Transistor 54 activates and may conduct current through the now coupled transistor 76 to the load circuit (not shown). With switches 58, 60 and 62 on, and switch 64 off, circuit 50 is in active mode.
  • FIG. 5 illustrates a timing diagram with enable, delay and enable-delayed signals.
  • Enable signal 78 is low during stand-by mode 80.
  • Enable signal 78 rises to communicate the transition from stand-by mode 80 to active mode 82. In the prior art, a falling enable signal would communicate the transition from active to stand-by mode.
  • the invention provides a delay before transitioning from active to stand-by modes. In one embodiment, the delay is approximately 300ns.
  • Delay signal 84 is high during to-stand-by mode 86 and off in standby mode 88.
  • Enable-delayed signal 90 rises at the beginning of active mode 82 and remains high until the end of to-stand-by mode 86.
  • FIG. 6 is a schematic diagram illustrating one embodiment of the invention.
  • FIG. 6 is a schematic diagram illustrating one embodiment of the invention.
  • Circuit 100 replaces active circuit 44 of FIG. 3 and is provided to illustrate the transition from active to stand-by mode.
  • Transistor 102 serves as a replica transistor while transistor 104 serves as a driver.
  • External power 106 couples to both transistors 102 and 104.
  • switches 108, 110 and 112 are on, while switch 114 is off.
  • switches 108, 110, and 112 turn off.
  • Switch 114 is off during active mode 82 and remains off until the fall of enable-delayed signal 90 (i.e., switch 114 remains off until stand-by mode 88), at which time switch 114 turns on.
  • Current from transistor 116 biases transistor 102.
  • Node 118 is disconnected from the gate of transistor 104.
  • Comparators 120 and 122 are activated during to-stand-by mode 86 (shown in FIG. 5) with delay signal 84. With switches 110 and 114 off during to-stand-by mode 86, comparator 120 compares the voltage at node 124 with node 126 and discharges node 124 toward ground as long as the potential at node 124 is greater than that at node 126. Comparator 122 charges node 118 toward a predetermined value, which in one embodiment is approximately 2N. When enable-delayed signal 90 falls at the end of to-stand-by mode 86 (see FIG. 5), switch 114 turns on and couples the gate of transistor 104 to node 126 and shuts off transistor 104.
  • FIG. 7 is a flow diagram illustrating the method of transitioning from active to standby modes.
  • switching off the driver transistor While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Electronic Switches (AREA)

Abstract

L'invention concerne un convertisseur abaisseur de tension, comprenant un mode de réserve et un mode actif, pour une mémoire comprenant les composants suivants : un noeud de charge (68) conçu pour recevoir une charge ; un premier transistor (54) comprenant une première grille, ce premier transistor étant conçu pour fournir un courant de charge à la mémoire ; un premier commutateur (58) couplé au noeud de charge et à la première grille, ce premier commutateur étant conçu pour appliquer la charge du noeud de charge à la première grille pendant la transition entre le mode de réserve et le mode actif ; un second transistor (66) couplé à la première grille, ce second transistor étant conçu pour polariser le premier transistor à un état inactif pendant le mode de réserve ; un second commutateur (64) couplé au premier transistor et au second transistor, ce second commutateur étant conçu pour appliquer, au niveau du second transistor, une différence de tension à la première grille pendant le mode de réserve.
EP03754491A 2002-09-12 2003-09-10 Systeme de commande des changements de mode dans un convertisseur abaisseur de tension Withdrawn EP1547088A4 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US407646 1989-09-15
ITTO20020794 2002-09-12
IT000794A ITTO20020794A1 (it) 2002-09-12 2002-09-12 Sitema per controllare le transizioni dalla modalita'
US10/407,646 US6785183B2 (en) 2002-09-12 2003-04-03 System for controlling the stand-by to active and active to stand-by transitions of a VCC regulator for a flash memory device
PCT/US2003/028441 WO2004025657A1 (fr) 2002-09-12 2003-09-10 Systeme de commande des changements de mode dans un convertisseur abaisseur de tension

Publications (2)

Publication Number Publication Date
EP1547088A1 true EP1547088A1 (fr) 2005-06-29
EP1547088A4 EP1547088A4 (fr) 2007-05-02

Family

ID=31995805

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03754491A Withdrawn EP1547088A4 (fr) 2002-09-12 2003-09-10 Systeme de commande des changements de mode dans un convertisseur abaisseur de tension

Country Status (9)

Country Link
EP (1) EP1547088A4 (fr)
JP (1) JP2005539345A (fr)
KR (1) KR20050049488A (fr)
CN (1) CN100435238C (fr)
AU (1) AU2003272315A1 (fr)
CA (1) CA2498608A1 (fr)
NO (1) NO20051560L (fr)
TW (1) TWI291803B (fr)
WO (1) WO2004025657A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011258033A (ja) * 2010-06-10 2011-12-22 Panasonic Corp 定電圧回路
US10345838B1 (en) * 2018-06-26 2019-07-09 Nxp B.V. Voltage regulation circuits with separately activated control loops

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0454170A2 (fr) * 1990-04-27 1991-10-30 Nec Corporation Appareil abaisseur de tension incorporé dans des circuits à grande intégration
US6292015B1 (en) * 1998-05-26 2001-09-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2800502B2 (ja) * 1991-10-15 1998-09-21 日本電気株式会社 半導体メモリ装置
JPH06162772A (ja) * 1992-11-25 1994-06-10 Sharp Corp 電源電圧降圧回路
JP3591107B2 (ja) * 1996-01-19 2004-11-17 富士通株式会社 電源降圧回路及び半導体装置
US5898605A (en) * 1997-07-17 1999-04-27 Smarandoiu; George Apparatus and method for simplified analog signal record and playback
JP3147079B2 (ja) * 1998-04-14 2001-03-19 日本電気株式会社 半導体回路
US6661279B2 (en) * 2001-04-11 2003-12-09 Kabushiki Kaisha Toshiba Semiconductor integrated circuit which outputs first internal power supply voltage and second internal power supply voltage lower than first internal supply power voltage

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0454170A2 (fr) * 1990-04-27 1991-10-30 Nec Corporation Appareil abaisseur de tension incorporé dans des circuits à grande intégration
US6292015B1 (en) * 1998-05-26 2001-09-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
KENICHI IMAMIYA ET AL: "A 130-mm, 256-Mbit NAND Flash with Shallow Trench Isolation Technology" IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 34, no. 11, November 1999 (1999-11), XP011061107 ISSN: 0018-9200 *
See also references of WO2004025657A1 *

Also Published As

Publication number Publication date
KR20050049488A (ko) 2005-05-25
CN100435238C (zh) 2008-11-19
TW200417124A (en) 2004-09-01
EP1547088A4 (fr) 2007-05-02
NO20051560L (no) 2005-03-23
TWI291803B (en) 2007-12-21
WO2004025657A1 (fr) 2004-03-25
CA2498608A1 (fr) 2004-03-25
JP2005539345A (ja) 2005-12-22
AU2003272315A1 (en) 2004-04-30
CN1685437A (zh) 2005-10-19

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