1291803 玖、發明說明： 【發明所屬之技術領域】 之ΐ = = _轉換器。特別關於晶片上降壓轉換器 V電、轉換器將外部電源供應下降為較低之内 邛電源ί、應以供記憶體裝置之用。 【先前技術】 半導體系統涉及需要廣泛範兩 二 ’、 国包源之電路。微處理养輕 冗憶體典型以較高電壓位準摔 ^ ^ +知怍為使外電源能與微處理 益與其圮憶體相容，自外電 Γ私席之電壓供應必須降壓轉換。 圖m明習知技藝電虔降厂堅轉換器之一例。放大器2驅動 P-溝道金氧丰導體_s)電晶體4之間極。電晶體4之源極連 接外電源6，及晶體4之没極連接至負荷電路8。跨負荷電路 8之電壓當電路8中電流消耗增加時下降，及當電塵下降至 參考產生ϋ電㈣之電壓以下時’放大器2降低其跨電晶體 4閘極之電壓。電晶體4在其閘極電壓降低時導電率增加， 及隨後以電流供應負荷電路8。 圖2說明習知技藝電壓向下轉換器之另一例。ν溝道⑽ 電晶體20有一低門限電壓，其構型為源極跟隨器。在一例 中，驅動器電晶體20係一自然^4(；^建立在基板上並無特殊 植入，及有一極低之長寬比（W/L卜複製電晶體22耦合至驅 動器電晶體20，及有一較電晶體2〇為小之長寬比。放大器 24及電阻器26與電晶體22完成一控制迴路。放大器24控制 電晶體22之閘極並保持節點28之電壓在理想範圍。結果， 當節點28之電遷低於預定位轉時，電晶體2〇通過節點％提 87836 1291803 供電流。 圖3說明圖2之電壓轉換器之更 圖2中雷曰駚00 士上 八複版[路40與 二中電:體22有相似·之功能。等待電路42及主動電路料 二=中驅動器電晶體2。之功能。圖3之習知技藝 換益具有二作業模式··等待及啟動。在等待模式中， 至負荷之電流甚低。在啟翻指斗； 电 電流位準之電流：在啟動換式’電晶體導電及提供最大 上述叹。十之問題為在驅動器及參考部分間需要—完美 之匹配。另一問題為溫度及處理變化必須由複製電路：償 。，外，一參考電路始終開㉟，因為跟隨器需要一偏壓以 便知作》取後’在習知技藝之電麼降麼轉換器發生—問題 ’在啟動與等待模式間切換時問題發生。習知技藝電壓降 恩轉換器可能無法達到對電流步進之良好響應。該習知技 藝之電壓降壓轉換器亦可能在切換模式時有—危險電 鋒。 【發明内容】 本發明提供理及在啟動待轉移及等待-啟 動轉移之間切換。管理啟動與等待及等待至啟動模式間之 切換系統有二種轉移。第—種轉移為等待至啟動轉移。在 -實施例中，#内部降壓電源之負荷電流最初由負荷電容 器提供，其在内部電源節點作為一電荷槽。進入啟動模式 之珂，啟動模式之一複製電晶體被偏壓以將電容器充電。 當内部電源供應節點之電壓降低至一決定位準時，一開關 以由複製電晶體充電之電容器將驅動器電晶體偏壓至節點 87836 1291803 ’因而啟動驅動器電晶體及增加電流至負荷電路。 系統之第二種轉移為啟動至等待轉移。該轉移由一啟動 信號之下降指出。在一實施例中，多由啟動 σ Κ ^ 1 J ^ 延遲^號進入啟動信 5虎之降低與專待模式進 本 ) %進入之4間之間。該延遲信號提供等 待時間以供驅動器電晶體之閘極放電，及節點有待充電至 等：值。當延遲信號為高時’比較器將閘極及節點充電及 放电。-開關自電源供應節點在啟動信號降低時脫離，俾 電"“了止驅動器电晶體流動，而比較器將驅動器電晶體放 電。系統在延遲信號之終端進入等待模式。 【實施方式】 精於此技藝人士可瞭解，本發明已下之敘述僅供說明而 無限至之意。本發明其他實施例在精於此技藝人士讀本揭 示後可甚為明顯。 圖4為略圖，說明本發明一實施例。電路5〇取代圖3之 啟動毛路44，並備以說明自等待至啟動模式之轉移。電晶 體52供作一複製電晶體，而電晶體54作為一驅動器。外電 源仪應56耦合至二電晶體52及54。在等待模式時，開關58 ，60及62關閉，開關64開啟。精於此技藝人士當瞭解，開 關在開啟時導電，纟關閉時不導電。電晶體52被自電晶體 66之电流所偏壓’並使在一實施例中包括電容器之節點 68充電至2 V。在一實施例中，電容器7〇為4〇〇 pF。節點72 保持在低一門限或約8〇() mV。電晶體54之閘極因此較其源 極低800 mv，源極耦合至内部電壓源vcc 74，因此為關閉 。此外’開關62阻止電流通過電晶體54至負荷電路（未示出） 87836 1291803 在貫施例中，本發明中之電晶體為P-溝道MOS電晶體。 ^ 8 6〇及62為開啟，開關64為關閉以便轉移至啟動 吴^ f曰曰體54自節點72去麵合並搞合至節點68(約為2 V) :體M啟動並可傳導電流通過現在為輕合之電晶體76 立何電路（未示出）。當開關58,⑼及㈣開啟時，開關 64為關閉，電路50為啟動模式。 圖5說明以啟動，延遲及啟動-延遲信號說明-時序圖。 動4。娩78在等待杈式8〇時為低。啟動信號π上升以通知 自等待模式8G轉移至啟動模式82。在習知技藝巾，__下降 之啟動信號將通知自啟動轉移至等待模式。本發明在自啟 動換式轉移至等待模式之前提供—延遲。在—實施例中， 該延遲，為300 nse延遲信號料在至等待模式_間為高 ’及在等待模式88時為關閉。啟動延遲信號90在啟動模式 82開始時上升’―直料高料待模式％之終止。 圖6為-略圖，說明本發明之—實施例。圖6為圖艸電路 更詳細之說明電路1〇〇取但圖3之啟動電路44及備以說明自 啟動模式轉移至等待膜式。電晶體1〇2作為一複製電晶體， 而電晶體刚則為—驅動器電晶體。外部電源⑺咏合至電 晶體1〇2和1〇4。在啟動模式時，電晶體108, 11〇及112為導 電，開關114為不導電。當與系統1〇〇有關之電路（未示出） 自啟動信號78(示於圖5)接收—低輸人時，開關⑽，⑴及 112不導電。開關114在啟動模式82期間不導電，—直保持 不導電直到啟動延遲信號9〇(開關U4保持不導電直到等待 模式88)已降低’此時’開關114導電。自電晶體ιΐ6之電流 87836 1291803 卽點118自電晶體_之閉極脫接 將電晶體102偏壓 ->TJ /〇7〇 ^ - 比較器12〇及122在等待模式％期間（如圖5)被一延遲产 號86所激勵’因開關11G，U4在等待模式％時為不導電，。 比較器m將節點124電麼與節點126之電麼比較，並將節勢 ⑽電至地電位，直到節點124之電位高於節點126之電位 。比較器122將節點118充電直到—預定值，其在—實施例 中約為2 V。當啟動_延遲信號9〇在等待模式％(圖5)之終止 降低時，開關114導電及耦合電晶體1〇4之閘極至節點126 以使電晶體1〇4不導電。 圖7為流程圖，說明自啟動模式轉移至等待模式之方法。 在區塊15G時，在自啟動至等待模式轉移期間，接收一至等 待信號。區塊155時，將驅動器電晶體自負荷電路去耦合。 區塊160時，將驅動電晶體閘極電壓與第一預定節點電壓比 較，並將閘極放電至地電位，直到閘極電壓大於預定之節 點電壓。區塊165時，比較第二預定節點之電壓與一預定電 壓，並將第二預定節點充電直到預定電壓為止。區塊17〇 時，開關將驅動器電晶體不導電。 當本發明之實施例及應用已如上述，精於此技藝人士當 理解上述許多修改為可行而不致有悖本發明之精神與範圍 。因此本發明不受限制，但附錄中申請專科範圍之精神除 外。 【圖式簡單說明】 圖1為習知技藝之降壓轉換器略圖。 圖2為習知技藝之降壓轉換器略圖。 87836 1291803 θ 3為圖2之習知技藝之降轉換器詳細圖解。 圖4為自等帶模式轉移至啟動模式之降壓轉換器系統之 一部分略圖。 圖5為用以自啟私絲 圖6為円r 至等待模式之時序信號。 圖6為圖4糸統之詳， 之電路。 、’圖解’包括自啟動轉移至等待模式 法之流程圖 【圖式代表符號說明】 2 放大器 4 電晶體源極 6 外電壓源 8 負荷電路 10 產生器電路 20 驅動器電晶體 22 電晶體閘極 24 放大器 26 電阻器 28 節點 3 0 節點 40 複製電晶體 42 等待電路 44 啟動電路 78 啟動信號 87836 1291803 80 等待模式 82 啟動模式 84 延遲信號 86 等待模式 88 等待模式 90 啟動延遲信號 100 電路 102 電晶體 104 電晶體 106 外部電源 108 開關 110 開關 112 開關 114 開關 116 電晶體 120 比較器 122 比較器 124 節點 126 節點 118 節點 87836 -12 -1291803 玖, invention description: [Technical field to which the invention pertains] ΐ = = _ converter. In particular, on the on-wafer buck converter V, the converter reduces the external power supply to a lower level. The power supply should be used for memory devices. [Prior Art] A semiconductor system involves a circuit that requires a wide range of applications. Micro-processing and light-keeping The redundant body is typically at a higher voltage level. ^ ^ + knowing that the external power supply can be compatible with the micro-processing benefits and the memory supply from the external power supply must be step-down conversion. Figure m shows an example of a well-known art technologist. Amplifier 2 drives the P-channel MOS conductor _s) between the transistors 4. The source of the transistor 4 is connected to the external power source 6, and the pole of the crystal 4 is connected to the load circuit 8. The voltage across the load circuit 8 drops as the current consumption in the circuit 8 increases, and when the electric dust drops below the voltage at which the reference generates the charge (4), the amplifier 2 lowers the voltage across its gate 4 of the transistor. The transistor 4 increases in conductivity as its gate voltage decreases, and then supplies the load circuit 8 with current. Figure 2 illustrates another example of a conventional art voltage down converter. The ν-channel (10) transistor 20 has a low threshold voltage and is configured as a source follower. In one example, the driver transistor 20 is a natural device (4) built on the substrate without special implantation, and has a very low aspect ratio (W/L Bu replication transistor 22 is coupled to the driver transistor 20, And having a smaller aspect ratio than the transistor 2. The amplifier 24 and the resistor 26 and the transistor 22 complete a control loop. The amplifier 24 controls the gate of the transistor 22 and maintains the voltage of the node 28 in a desired range. When the electromigration of the node 28 is lower than the predetermined bit rotation, the transistor 2〇 supplies the current through the node % 87836 1291803. Fig. 3 illustrates the voltage converter of Fig. 2 in the second picture of the Thunder 00 s upper eight version [ The road 40 and the second power supply: the body 22 has a similar function. The function of the waiting circuit 42 and the active circuit material 2 = the middle driver transistor 2. The conventional technology of Fig. 3 has two working modes: waiting and starting In the standby mode, the current to the load is very low. The current is turned on; the current of the electric current level: in the start-up type 'transistor conduction and provides the maximum sigh. The ten problem is between the driver and the reference part. Need - perfect match. Another problem is warm And the processing changes must be made by the replica circuit: repayment. In addition, a reference circuit is always open 35, because the follower needs a bias voltage so that it can be known as "after the 'in the conventional technology, the converter occurs." The problem occurs when switching between the start and wait modes. The conventional voltage drop converter may not be able to achieve a good response to the current step. The voltage buck converter of the prior art may also have a dangerous power front when switching modes. SUMMARY OF THE INVENTION The present invention provides for switching between activating a pending transfer and a wait-to-start transition. There are two types of switching between a management start-up and a wait-and-wait-to-start mode. The first type of transfer is a wait-to-start transfer. In the embodiment, the load current of the #internal buck power supply is initially provided by the load capacitor, which acts as a charge tank at the internal power supply node. After entering the startup mode, one of the startup modes is replicated to bias the transistor to capacitor Charging. When the voltage of the internal power supply node drops to a certain level, a switch will be driven by a capacitor charged by the replica transistor. The transistor is biased to node 87836 1291803' thus starting the driver transistor and adding current to the load circuit. The second transfer of the system is from start-up to wait for transfer. The transfer is indicated by a drop in the start signal. In one embodiment, The start σ Κ ^ 1 J ^ delay ^ number enters the start letter 5 tiger's reduction and the special mode enters this) between the 4%. The delayed signal provides the waiting time for the gate discharge of the driver transistor, and The node has to be charged to the equal value: when the delay signal is high, the comparator charges and discharges the gate and the node. - The switch is disconnected from the power supply node when the start signal is lowered, and the drive transistor flows. And the comparator discharges the driver transistor. The system enters the standby mode at the terminal of the delayed signal. [Embodiment] It will be apparent to those skilled in the art that the description of the present invention is for illustrative purposes only and is infinitely intended. Other embodiments of the invention will be apparent from the disclosure of this disclosure. Figure 4 is a schematic view showing an embodiment of the present invention. Circuit 5 replaces the starter hair path 44 of Figure 3 and is provided to illustrate the transition from wait to start mode. The electric crystal 52 is used as a replica transistor, and the transistor 54 serves as a driver. The external power meter should be coupled 56 to the two transistors 52 and 54. In the standby mode, switches 58, 60 and 62 are closed and switch 64 is open. It is understood by those skilled in the art that the switch conducts when it is turned on, and does not conduct when it is turned off. The transistor 52 is biased by the current from the transistor 66 and charges the node 68 including the capacitor to 2 V in one embodiment. In one embodiment, the capacitor 7 is 4 〇〇 pF. Node 72 remains at a low threshold or approximately 8 〇 () mV. The gate of transistor 54 is therefore 800 mV lower than its source and the source is coupled to internal voltage source vcc 74 and is therefore off. Further, the switch 62 blocks current from passing through the transistor 54 to the load circuit (not shown). 87836 1291803 In the embodiment, the transistor in the present invention is a P-channel MOS transistor. ^ 8 6〇 and 62 are on, switch 64 is off to transfer to start-up. The body 54 is removed from node 72 and merged to node 68 (approximately 2 V): body M starts and conducts current through Now it is the circuit of the light-emitting transistor 76 (not shown). When switches 58, (9), and (d) are turned "on", switch 64 is off and circuit 50 is in the start mode. Figure 5 illustrates the start-up, delay, and start-delay signal descriptions - timing diagrams. Move 4. Delivery 78 is low when waiting for 8杈. The start signal π rises to notify the transition from the standby mode 8G to the start mode 82. In the conventional art towel, the __ falling start signal will notify the self-start to shift to the standby mode. The present invention provides a delay before the self-starting transition to the standby mode. In the embodiment, the delay is 300 nse delayed signal is high during wait mode _ and is off when waiting mode 88. The start delay signal 90 rises at the beginning of the start mode 82' - the end of the high feed mode %. Figure 6 is a schematic view of an embodiment of the present invention. Fig. 6 is a diagram showing the circuit of Fig. 3 in more detail, but the start circuit 44 of Fig. 3 is prepared to illustrate the transition from the start mode to the wait mode. The transistor 1〇2 acts as a replica transistor, and the transistor is just the driver transistor. The external power supply (7) is coupled to the transistors 1〇2 and 1〇4. In the startup mode, transistors 108, 11A and 112 are conductive and switch 114 is non-conductive. When a circuit (not shown) associated with system 1 is received from start signal 78 (shown in Figure 5) - low inputs, switches (10), (1) and 112 are not conducting. Switch 114 is non-conductive during start mode 82, - remains inactive until the start delay signal 9 〇 (switch U4 remains non-conductive until wait mode 88) has been lowered 'at this time' switch 114 is conducting. The current from the transistor ιΐ6 87836 1291803 卽 point 118 from the transistor _ the closed-pole disconnection will bias the transistor 102 -> TJ / 〇 7 〇 ^ - Comparator 12 〇 and 122 during the wait mode % (Figure 5) Excited by a delayed production number 86. Due to the switch 11G, U4 is non-conductive when waiting for mode %. Comparator m compares node 124 with the power of node 126 and energizes the potential (10) to ground potential until the potential of node 124 is higher than the potential of node 126. Comparator 122 charges node 118 until a predetermined value, which is -2 V in the embodiment. When the start_delay signal 9 is delayed in the wait mode % (Fig. 5), the switch 114 conducts and couples the gate of the transistor 1〇4 to the node 126 to make the transistor 1〇4 non-conductive. Figure 7 is a flow chart illustrating a method of transitioning from a startup mode to a standby mode. At block 15G, a to wait signal is received during the self-start to wait mode transition. At block 155, the driver transistor is decoupled from the load circuit. At block 160, the drive transistor gate voltage is compared to a first predetermined node voltage and the gate is discharged to ground potential until the gate voltage is greater than a predetermined node voltage. At block 165, the voltage of the second predetermined node is compared to a predetermined voltage and the second predetermined node is charged until a predetermined voltage. At block 17〇, the switch will not drive the driver transistor. While the embodiments and applications of the present invention have been described above, it will be apparent to those skilled in the art that Therefore, the present invention is not limited, except for the spirit of applying for the scope of the specialist in the appendix. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a buck converter of the prior art. 2 is a schematic diagram of a buck converter of the prior art. 87836 1291803 θ 3 is a detailed illustration of the conventional down converter of FIG. Figure 4 is a partial schematic diagram of a buck converter system that transitions from the isoband mode to the startup mode. Figure 5 is a timing signal for self-opening. Figure 6 shows the timing signal from 円r to standby mode. Figure 6 is a circuit diagram of the details of Figure 4. , 'Illustration' includes a flow chart from the start-up transfer to the wait mode method. [Illustration of symbolic representation] 2 Amplifier 4 Transistor source 6 External voltage source 8 Load circuit 10 Generator circuit 20 Driver transistor 22 Crystal gate 24 Amplifier 26 Resistor 28 Node 3 0 Node 40 Replicate Transistor 42 Waiting Circuit 44 Start Circuit 78 Start Signal 87836 1291803 80 Wait Mode 82 Start Mode 84 Delay Signal 86 Wait Mode 88 Wait Mode 90 Start Delay Signal 100 Circuit 102 Transistor 104 Crystal 106 External Power Supply 108 Switch 110 Switch 112 Switch 114 Switch 116 Crystal 120 Comparator 122 Comparator 124 Node 126 Node 118 Node 87836 -12 -