CN100435238C - System for controlling mode changes in a voltage down-converter - Google Patents
System for controlling mode changes in a voltage down-converter Download PDFInfo
- Publication number
- CN100435238C CN100435238C CNB038234637A CN03823463A CN100435238C CN 100435238 C CN100435238 C CN 100435238C CN B038234637 A CNB038234637 A CN B038234637A CN 03823463 A CN03823463 A CN 03823463A CN 100435238 C CN100435238 C CN 100435238C
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- China
- Prior art keywords
- transistor
- electric charge
- couple
- voltage
- node
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- Expired - Fee Related
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
Abstract
A voltage down-converter system, with a stand-by mode and an active mode, for a memory device with the following components. A charge node (68) is configured to receive a charge. A first transistor (54) has a first gate and the first transistor is configured to supply a load current to the memory device. A first switch (58) is coupled to the charge node and the first gate, the first switch being configured to apply the charge in the charge node to the first gate during transition from stand-by to active modes. A second transistor (66) is coupled to the first gate and configured to bias the first transistor to an inactive state during stand-by mode. A second switch (64) is coupled to the first gate and the second transistor, the second switch being configured to apply a voltage difference at the second transistor to the first gate during the stand-by mode.
Description
Technical field
The present invention relates to electric pressure converter.More particularly, the present invention relates to manage and control the on-chip voltage down converter of the lower internal electric source that external power source progressively is reduced to that is used for memory storage.
Background technology
Semiconductor system relates to the circuit that needs broad range of power.For example, microprocessor is operated under the voltage level higher than storer usually.For example, in order to make external power source and microprocessor and storer fit thereof, must reduce the voltage of conversion from external power source.
Fig. 1 has illustrated the example of a prior art step-down controller.Amplifier 2 drives the grid of p-channel mos (MOS) transistor 4.The source electrode of transistor 4 is connected to external power source 6, and the drain electrode of transistor 4 is connected to load circuit 8.The voltage of striding load circuit 8 and drops to reference to the voltage of generator circuit 10 when following when voltage when the current drain in the circuit 8 increases and descend, and amplifier 2 reduces the voltage of striding transistor 4 grids.Conductance increased when transistor 4 reduced at its grid voltage, thereby, to load circuit 8 supplying electric currents.
Fig. 2 illustrates another example of prior art step-down controller.N-passage MOS transistor 20 has low starting voltage, and it is configured and is source follower.In one example, driver transistor 20 is based upon natural MOS on the substrate for need not special implantation, and has very big length breadth ratio (W/L).Replica transistor 22 is couple to driver transistor 20, and has the length breadth ratio more less than transistor 20.Amplifier 24 and resistor 26 are finished control loop with transistor 22.The grid of amplifier 24 oxide-semiconductor control transistors 22 also will remain in the ideal range at the voltage at node 28 places.Thereby when the voltage at node 28 places dropped under the predeterminated level, transistor 20 provided the electric current by node 30.
The more detailed version of electric pressure converter in Fig. 3 key diagram 2.Duplicate circuit 40 have with Fig. 2 in the functionally similar function of transistor 22.Wait for the function of driver transistor 20 in circuit 42 and activity circuit 44 execution graphs 2.Prior art electric pressure converter among Fig. 3 has two kinds of operator schemes: standby mode and activity pattern.In standby mode, the electric current that leaks into load seldom.In activity pattern, electric current up to maximum horizontal is opened and provided to transistor.
A problem of above-mentioned design is need be in the Perfect Matchings between driver and the reference section.Another problem is to come compensation temperature and processing variation by duplicate circuit.Equally, the operation because follower needs bias voltage is so reference circuit is opened all the time.At last, when between activity and standby mode, switching, go wrong in the existing step-down controller.Existing step-down controller possibly can't reach the good response to current generation (current step).Existing step-down controller also may be uprushed by dangerous voltage when switch mode.
Summary of the invention
The invention provides a kind of management activity change to standby mode with etc. the system by the time switched between the active transition.Management movable and wait for and the activity by the time of grade between the system switched have two kinds of transformations.First kind changes into etc. by the time movable transformation.In one embodiment, on the internal electric source node, supply with the inner load current that progressively reduces power supply by load capacitor (serving as the electric charge groove) at first.Before entering activity pattern, the replica transistor of bias voltage activity pattern is to charge to capacitor.When the internal electric source voltages at nodes is reduced to predeterminated level, switch is biased into node with the capacitor by replica transistor charging with driver transistor, thereby activates driver transistor and be increased to the electric current of load circuit.
Second kind of system changes the movable wait transformation of arriving into.Described transformation is indicated by the reduction of enabling signal.In one embodiment, in the reduction of enabling signal and enter between time of standby mode and insert inhibit signal.Described inhibit signal is for a driver transistor gate to be discharged and treat to provide the time to a node of wait value charging.As long as when inhibit signal is high, comparer will carry out charge and discharge to grid and node.When enabling signal reduced, a switch made driver transistor disconnect from power supply node, made electric current stop the outflow from driver transistor, and comparer discharges to the grid of driver transistor simultaneously.System enters standby mode at the inhibit signal end.
Description of drawings
Fig. 1 is the synoptic diagram of prior art step-down controller.
Fig. 2 is the synoptic diagram of prior art step-down controller.
Fig. 3 is the more detailed synoptic diagram of the prior art step-down controller among Fig. 2.
Fig. 4 is for being converted to the synoptic diagram of a part of the step-down controller system of activity pattern from standby mode.
Fig. 5 is the figure that is used for the timing signal from the active transition to the standby mode.
Fig. 6 is the detailed maps that comprises Fig. 4 system of the circuit that is used for from the active transition to the standby mode.
Fig. 7 is for illustrating the process flow diagram of the method from the active transition to the standby mode according to an embodiment of the invention.
Embodiment
One of ordinary skill in the art will recognize that following description of the present invention only is illustrative and limits the present invention unintentionally by any way.The those skilled in the art who benefits from this disclosure will easily understand other embodiments of the invention.
Fig. 4 is the synoptic diagram of explanation one embodiment of the invention.Circuit 50 replaces the activity circuit 44 of Fig. 3, and provide circuit 50 with explanation from waiting transformation of activity pattern by the time.Transistor 52 is as replica transistor, and transistor 54 is as driver.External power source 56 is couple to transistor 52 and 54.When being in standby mode, switch 58,60 and 62 cuts out, and switch 64 is opened.One of ordinary skill in the art will understand, and switch is conduction when opening, and is non-conductive when closing.Transistor 52 is by the electric current institute bias voltage from transistor 66, and will comprise in one embodiment that the node 68 of capacitor 70 is charged to about 2V.In one embodiment, capacitor 70 is 400pF.Node 72 remains on lower threshold value or about 800mV.Therefore, the grid of transistor 54 is than the low 800mV of its source electrode, and it is couple to internal source voltage VCC 74, and therefore for closing.In addition, switch 62 stops electric current to flow through transistor 54 to the load circuit (not shown).In one embodiment, the transistor among the present invention is a p-passage MOS transistor.
Fig. 5 explanation has the timing diagram of startup, delay and startup-inhibit signal.Enabling signal 78 is low during standby mode 80.Enabling signal 78 rises with the transformation of passing on from standby mode 80 to activity pattern 82.In the prior art, the enabling signal of decline will be passed on the transformation from the activity to the standby mode.The present invention provided delay before from the active transition to the standby mode.In one embodiment, described delay is about 300ns.Inhibit signal 84 be height during the standby mode 86, and when being in standby mode 88 for closing.Startup-inhibit signal 90 rises when the beginning of activity pattern 82, keeps high when standby mode 86 finishes always.
Fig. 6 is the synoptic diagram of explanation one embodiment of the invention.Fig. 6 is the more detailed description of circuit illustrated in fig. 4.Circuit 100 replaces the activity circuit 44 of Fig. 3, and provides circuit 100 with the transformation of explanation from the activity pattern to the standby mode.Transistor 102 is as replica transistor, and transistor 104 is then as driver.External power source 106 is couple to transistor 102 and 104.At activity pattern, switch 108,110 and 112 is unlatching, and switch 114 is for cutting out.When the circuit (not shown) relevant with system 100 when enabling signal 78 (shown in Fig. 5) receives low input, switch 108,110 and 112 cuts out.Switch 114 cuts out during activity pattern 82, and keeps closing up to startup-inhibit signal 90 reductions (that is, switch 114 keeps cutting out up to standby mode 88) always, and at this moment, switch 114 is opened.Current bias transistor 102 from transistor 116.Node 118 disconnects from the grid of transistor 104.
Comparer 120 and 122 during standby mode 86 (as shown in Figure 5) be delayed signal 84 and activate, switch 110,114 during standby mode 86 for closing, comparer 120 will compare at the voltage at node 124 places and the voltage at node 126 places, and as long as at the electromotive force at node 124 places greater than electromotive force at node 126 places, just node 124 is discharged to ground connection.To predetermined value charging, it is about 2V to comparer 122 in one embodiment with node 118.When startup-inhibit signal 90 reduced when finishing to standby mode 86 (referring to Fig. 5), switch 114 was opened and the grid of transistor 104 is couple to node 126 and turn-offs transistor 104.
Fig. 7 is the process flow diagram of the method for explanation from the active transition to the standby mode.In block 150, between the tour from the activity to the standby mode, receive one to waiting signal.In block 155, with driver transistor from the load circuit decoupling.In block 160, the drive transistor gate voltage and first predetermined node voltage are compared, and as long as grid voltage greater than predetermined node voltage, just discharges grid to ground connection.In block 165, the voltage and a predetermined voltage at the second destined node place compared, and with second destined node to charging near predetermined voltage.In block 170, cut off driver transistor.
Though shown and described when embodiments of the invention and application, be understood by those skilled in the art that be revised as more than above-mentioned modification many possible, and the inventive concepts that can not break away from this paper.Therefore, the present invention only is subjected to the restriction of aforesaid right requirement spirit.
Claims (19)
1. step-down controller system that is used for a memory storage with a wait pattern and an activity pattern, it comprises:
One is configured to receive the electric charge node of an electric charge;
One has the first transistor of a first grid, and described the first transistor is couple to described memory storage, and is configured it to supply with a load current to described memory storage;
One is couple to first switch of described electric charge node and described first grid, disposes described first switch to be applied to described electric charge the described electric charge node to described first grid during wait is converted to activity pattern;
One is couple to the transistor seconds of described first grid; With
One is couple to the second switch of described first grid and described transistor seconds, disposes described second switch to apply a voltage potential and the described the first transistor of bias voltage to cut-off state to described first grid during described standby mode.
2. system according to claim 1, it also comprises:
One is couple to the 3rd transistor of described electric charge node, and it is configured to by described transistor seconds institute's bias voltage and during standby mode described electric charge node is charged.
3. system according to claim 2, it also comprises:
One is couple to described the first transistor and to the 3rd switch of described memory storage, and it is configured to during standby mode, prevent that load current from flowing to described memory storage by described the first transistor, and during activity pattern, allow electric current to flow to described memory storage by described the first transistor.
4. system according to claim 3, wherein:
Described the first transistor and described the 3rd transistor are couple to an external power source separately.
5. system according to claim 4, wherein:
Described the first transistor is couple to an internal source voltage.
6. system according to claim 4, wherein:
Described electric charge node is a capacitor.
7. step-down controller system that is used for a memory storage with a wait pattern and an activity pattern, it comprises:
One is configured to receive the first electric charge node of one first electric charge;
One is couple to the described first electric charge node and first comparer that be configured to receive a signal, and when receiving described signal, described first electric charge and the ground connection at the described first electric charge node place are compared, and as long as described first electric charge just discharges the described first electric charge node greater than ground connection to ground connection;
One is configured to receive the second electric charge node of one second electric charge;
One is couple to the described second electric charge node and is configured to receive second comparer of described signal, and when receiving described signal, described second electric charge and a reference voltage at the described second electric charge node place are compared, and as long as described second electric charge just charges the second electric charge node less than described reference voltage to described reference voltage; With
One provides the circuit arrangement of load current to described memory storage.
8. system according to claim 7, wherein said circuit arrangement comprises
One has the first transistor of a grid, and described the first transistor is couple to the described first electric charge node, and is couple to described memory storage, and is configured it to supply with described load current to described memory storage.
9. system according to claim 8, it also comprises:
One is couple to first switch of described grid and the described second electric charge node.
10. system according to claim 9, wherein:
Dispose described first switch with from the activity pattern to the standby mode transformation disconnect and described grid of electric decoupling and the described second electric charge node when finishing.
11. system according to claim 10, it also comprises:
One is couple to the second switch of described the first transistor and described memory storage, and it is configured to disconnect when the transformation from the activity pattern to the standby mode finishes.
12. system according to claim 11, wherein:
The described first electric charge node is couple to a transistor seconds, and described transistor seconds provides signal to described first comparer.
13. system according to claim 12, wherein:
The described second electric charge node is couple to a capacitor.
14. system according to claim 13, wherein;
During being converted to standby mode, send described signal to described system from activity pattern.
15. system according to claim 14, wherein:
Described signal continues 300ns.
16. one kind in a step-down controller system that is used for memory storage, is converted to a method of waiting for pattern from an activity pattern, it comprises:
During being converted to standby mode, receive one and wait for signal from activity pattern;
One driver transistor gate voltage and one first predetermined node voltage are compared, and as long as described grid voltage greater than described predetermined node voltage, discharges described grid to ground connection; With
From the described driver transistor of described memory storage decoupling zero.
17. method according to claim 16, it also comprises:
To compare at the described voltage and a predetermined voltage at one second destined node place, and as long as described voltage just charges described second destined node less than described reference voltage to described predetermined voltage.
18. method according to claim 17, it also comprises:
With a switch from a load circuit with the decoupling of described driver transistor physics.
19. method according to claim 18, it also comprises:
The voltage that is applied to described grid by control turn-offs described driver transistor.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| ITTO2002A000794 | 2002-09-12 | ||
| IT000794A ITTO20020794A1 (en) | 2002-09-12 | 2002-09-12 | SITEMA TO CHECK THE TRANSITIONS FROM THE MODE |
| US10/407,646 US6785183B2 (en) | 2002-09-12 | 2003-04-03 | System for controlling the stand-by to active and active to stand-by transitions of a VCC regulator for a flash memory device |
| US10/407,646 | 2003-04-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1685437A CN1685437A (en) | 2005-10-19 |
| CN100435238C true CN100435238C (en) | 2008-11-19 |
Family
ID=31995805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB038234637A Expired - Fee Related CN100435238C (en) | 2002-09-12 | 2003-09-10 | System for controlling mode changes in a voltage down-converter |
Country Status (9)
| Country | Link |
|---|---|
| EP (1) | EP1547088A4 (en) |
| JP (1) | JP2005539345A (en) |
| KR (1) | KR20050049488A (en) |
| CN (1) | CN100435238C (en) |
| AU (1) | AU2003272315A1 (en) |
| CA (1) | CA2498608A1 (en) |
| NO (1) | NO20051560L (en) |
| TW (1) | TWI291803B (en) |
| WO (1) | WO2004025657A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011258033A (en) * | 2010-06-10 | 2011-12-22 | Panasonic Corp | Constant voltage circuit |
| US10345838B1 (en) * | 2018-06-26 | 2019-07-09 | Nxp B.V. | Voltage regulation circuits with separately activated control loops |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5327388A (en) * | 1991-10-15 | 1994-07-05 | Nec Corporation | Semiconductor memory device |
| US5408172A (en) * | 1992-11-25 | 1995-04-18 | Sharp Kabushiki Kaisha | Step-down circuit for power supply voltage capable of making a quick response to an increase in load current |
| US5811861A (en) * | 1996-01-19 | 1998-09-22 | Fujitsu Limited | Semiconductor device having a power supply voltage step-down circuit |
| CN1232318A (en) * | 1998-04-14 | 1999-10-20 | 日本电气株式会社 | Semiconductor integrated circuit device |
| CN1270695A (en) * | 1997-07-17 | 2000-10-18 | 阿特梅尔股份有限公司 | Apparatus and method for simplified analog signal record and playback |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2778199B2 (en) * | 1990-04-27 | 1998-07-23 | 日本電気株式会社 | Internal step-down circuit |
| JP4390304B2 (en) * | 1998-05-26 | 2009-12-24 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
| US6661279B2 (en) * | 2001-04-11 | 2003-12-09 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit which outputs first internal power supply voltage and second internal power supply voltage lower than first internal supply power voltage |
-
2003
- 2003-09-10 AU AU2003272315A patent/AU2003272315A1/en not_active Abandoned
- 2003-09-10 KR KR1020057004232A patent/KR20050049488A/en not_active Application Discontinuation
- 2003-09-10 EP EP03754491A patent/EP1547088A4/en not_active Withdrawn
- 2003-09-10 WO PCT/US2003/028441 patent/WO2004025657A1/en active Search and Examination
- 2003-09-10 JP JP2004571981A patent/JP2005539345A/en active Pending
- 2003-09-10 CN CNB038234637A patent/CN100435238C/en not_active Expired - Fee Related
- 2003-09-10 CA CA002498608A patent/CA2498608A1/en not_active Abandoned
- 2003-09-12 TW TW092125199A patent/TWI291803B/en not_active IP Right Cessation
-
2005
- 2005-03-23 NO NO20051560A patent/NO20051560L/en not_active Application Discontinuation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5327388A (en) * | 1991-10-15 | 1994-07-05 | Nec Corporation | Semiconductor memory device |
| US5408172A (en) * | 1992-11-25 | 1995-04-18 | Sharp Kabushiki Kaisha | Step-down circuit for power supply voltage capable of making a quick response to an increase in load current |
| US5811861A (en) * | 1996-01-19 | 1998-09-22 | Fujitsu Limited | Semiconductor device having a power supply voltage step-down circuit |
| CN1270695A (en) * | 1997-07-17 | 2000-10-18 | 阿特梅尔股份有限公司 | Apparatus and method for simplified analog signal record and playback |
| CN1232318A (en) * | 1998-04-14 | 1999-10-20 | 日本电气株式会社 | Semiconductor integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1547088A1 (en) | 2005-06-29 |
| TWI291803B (en) | 2007-12-21 |
| KR20050049488A (en) | 2005-05-25 |
| AU2003272315A1 (en) | 2004-04-30 |
| TW200417124A (en) | 2004-09-01 |
| CA2498608A1 (en) | 2004-03-25 |
| EP1547088A4 (en) | 2007-05-02 |
| WO2004025657A1 (en) | 2004-03-25 |
| JP2005539345A (en) | 2005-12-22 |
| NO20051560L (en) | 2005-03-23 |
| CN1685437A (en) | 2005-10-19 |
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