EP1489621B1 - Mémoire à accès aléatoire sans transistors - Google Patents

Mémoire à accès aléatoire sans transistors Download PDF

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Publication number
EP1489621B1
EP1489621B1 EP03026609A EP03026609A EP1489621B1 EP 1489621 B1 EP1489621 B1 EP 1489621B1 EP 03026609 A EP03026609 A EP 03026609A EP 03026609 A EP03026609 A EP 03026609A EP 1489621 B1 EP1489621 B1 EP 1489621B1
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European Patent Office
Prior art keywords
voltage
memory
cells
core
chalcogenide
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Expired - Lifetime
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EP03026609A
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German (de)
English (en)
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EP1489621A1 (fr
Inventor
Yi-Chou Chen
Wen-Jer MACRONIX International Co. Ltd. Tsai
Chih-Yuan Lu
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Macronix International Co Ltd
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Macronix International Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Definitions

  • the present invention relates generally to memory devices and, more particularly, to a memory cell structure not requiring access transistors.
  • Typical memory cells include a steering element, e.g., one or more transistors, to access each cell.
  • the access transistors which may also be diodes, provide access for the word lines to the bit lines of the memory cell. That is, the access transistors act as a pass gate to provide access for the word line to the bit line in order to read and write data to a memory cell.
  • the current/voltage required to program the chalcogenide memory cells is relatively high as compared to the operating current/voltage.
  • the access transistors may not be able to handle the programming voltages, thereby limiting the current that can be used for programming because a high current may damage the transistors or diodes acting as access transistors for the memory cells.
  • the present invention enables the access transistor, which is also referred to as a steering element, for accessing a memory core cell to be eliminated through the use of a threshold changing material that can be programmed to function as a steering element.
  • a memory core in accordance with one aspect of the present invention, includes a bit line and a word line.
  • a core cell in electrical communication with the word line and the bit line is included.
  • the core cell includes a threshold changing material. The threshold changing material is programmed to enable access to the core cell based upon a voltage applied to the word line.
  • the threshold changing material is associated with transistor like properties enabling the memory core to function as both a steering device and a memory device.
  • the threshold material is programmed by either a floating technique or a bias technique.
  • a method for providing access to a memory core cell begins with determining a threshold voltage for access to a memory core cell. Then, a threshold changing material of the memory core cell is programmed to enable access to the memory core cell at the threshold voltage. Next, a voltage is applied to a word line in communication with the memory core cell. If the voltage is at least as large as the threshold voltage, then the method includes accessing the memory core cell.
  • a method for reading a chalcogenide memory device begins with applying a read voltage to a word line.
  • the read voltage is configured to directly access the chalcogenide memory device.
  • a zero bias is applied on the bit line corresponding to the word line.
  • a value stored in the chalcogenide memory device is read.
  • the method of adjusting the V th of the present invention can be applied in numerous memory/solid state device applications.
  • One of the significant advantages of the memory core is the elimination of access transistors that function as steering elements for signals to the memory core cells.
  • US 2003 /081451 A1 discloses a non-volatile memory based on chalcogenide phase change material memory core cells. The cells are accessed with an access diode separate from the core cells.
  • WO 2004/017436 which falls under the provisions of Article 54(3) EPC, discloses a non-volatile memory element based on hydrogenated amorphous silicon.
  • the memory core cell itself may have both the function of an access and a switching device.
  • a threshold changing material a chalcogenide material is incorporated into a memory cell in order to eliminate the need for access transistors.
  • the transistor-like properties of the threshold changing material are exploited to simplify the memory cell structure by enabling the elimination of the steering element, e.g., the access transistor or P-N diode.
  • the chalcogenide memory cell may be embedded with logic circuits to form a system on a chip (SoC).
  • SoC system on a chip
  • the programming voltage associated with a threshold changing material is much lower than that of a flash read only memory (ROM).
  • the programming voltage associated with a chalcogenide memory cell is about 5 volts (V) as compared to a programming voltage of about 10 V for a flash ROM.
  • the chalcogenide memory cell is capable of functioning as both a steering device and memory device. Accordingly, the fabrication of just a chalcogenide memory cell is much easier than combining both a transistor and a chalcogenide memory cell. Additionally, where the memory cell also acts as a steering device, enables a reduction in the chip size for the same amount of memory as compared to a memory having separate steering devices and memory cells. Alternatively, a dual functioning chalcogenide memory may be able to provide more memory capacity as compared to memories having separate steering devices and memory cells. As discussed herein, a minimum-sized chalcogenide memory device is capable of passing a higher current as compared to an access transistor.
  • chalcogenide material is used as an example of a threshold changing material
  • the embodiments described herein are not limited to a chalcogenide material. That is, any suitable material having the desirable characteristics of a chalcogenide material, i.e., having stable and tunable voltage threshold (V th ) properties, may serve as a nonvolatile dual function memory cell.
  • Figure 1 is an I-V curve of chalcogenide memory cells associated with different V th .
  • the V th of chalcogenide may be adjusted by applying energy into the film. Therefore, there can be chalcogenide memory cells having different V th within a memory core. Because the device can pass high current when voltage is above V th and can block current when voltage is below V th , the device is capable of serving as an active steering device. It should be appreciated that because the V th is capable of being tuned and the V th is stable after programming, the cell can serve as a nonvolatile memory device.
  • Figure 1 illustrates a first threshold voltage (V thl ) associated with a memory cell captured by line 102 and a second threshold voltage (V th2 ) associated with a memory cell captured by line 104.
  • V thl first threshold voltage
  • V th2 second threshold voltage
  • Figure 2 is a graph representing the symmetric nature of the current (I)-voltage (V) characteristic of a chalcogenide memory device. As shown therein, line 106 illustrates the symmetrical nature between the relationship of I and V for the chalcogenide memory device.
  • FIG. 3 is a simplified schematic diagram of a memory array having dual function memory cells.
  • Memory cells 108a through 108n are illustrated in the matrix defined by word lines (WLn) WLn-1 to WLn+1 and bit lines BLn-1 to BLn+1. Since the chalcogenide memory cells function as both a memory cell and steering device, there is no need for access transistors.
  • Figures 4A through 4D illustrate exemplary plots associated with programming techniques that may be applied to a chalcogenide device.
  • Figure 4A illustrates a floating programming technique.
  • the chalcogenide memory device includes two voltage thresholds, i.e., a low voltage threshold (V th1 ) as state 1 and a high voltage threshold (V thh ) state 0.
  • the plot of Figure 4A illustrates the bias applied and the resulting bias on the cells.
  • the unselected cells are associated with a bias of -V p to +V p .
  • the selected cell is associated with a forward bias of +V p .
  • Cell 108s represents the selected cell, while the remainder of cells 108a - 108n represent the unselected cells.
  • Table 1 summarizes the programming method for program 1 and program 0.
  • Program 1 Program 0 Selected Bit line 0 0 Other Bit line Floating Floating Selected Word line V pl V ph Other Word line Floating Floating As summarized in Table 1, the selected bit line is zero, while the selected word line is dependent upon the program or state selected, i.e., V pl or V ph .
  • Figure 4B illustrates a biased programming technique.
  • the plot of Figure 4B illustrates the bias applied.
  • a voltage bias
  • the selected cell 108s is associated with a forward bias of +V p .
  • the chalcogenide memory device includes two voltage thresholds, i.e., a low voltage threshold (V th1 ) as state 1 and a high voltage threshold (V thh ) state 0.
  • V th1 low voltage threshold
  • V thh high voltage threshold
  • Figure 4C illustrates a plot of the V/2 method.
  • the plot of Figure 4C illustrates the bias applied and the resulting bias on the cell.
  • the selected cell 108s is associated with a forward bias of +V p while the remaining unselected cells are associated with a forward bias of +V p /2.
  • the chalcogenide memory device includes two voltage thresholds, i.e., a low voltage threshold (V th1 ) as state 1 and a high voltage threshold (V thh ) state 0.
  • V th1 low voltage threshold
  • V thh high voltage threshold
  • Figure 4D illustrates a plot of the V/3 method.
  • the plot of Figure 4D illustrates the bias applied and the resulting bias on the cell.
  • the selected cell 108s is associated with a forward bias of +V p while the remaining unselected cells fall into one of two characterizations, i.e., those associated with a forward bias and those associated with a reverse bias.
  • Cells 108f are associated with a forward bias of +V p /3
  • cells 108r are associated with a reverse bias of -V p /3.
  • the chalcogenide memory device includes two voltage thresholds, i.e., a low voltage threshold (V th1 ) as state 1 and a high voltage threshold (V thh ) state 0.
  • the reading methods include a floating method and a bias method.
  • the floating method refers to a bias V r that is applied between V th1 and V thh on the selected word line (or bit line) and zero bias on the selected word line (or bit line).
  • Other word lines and bit lines are floating.
  • the bias method refers to a bias V r that is applied between V th1 and V thh on the selected word line (or bit line) and zero bias on the selected word line (or bit line).
  • Other word lines and bit lines apply a certain bias of 0 ⁇ V ⁇ V th1 . Two illustrative bias methods, V/2 method and V/3 method were presented.
  • Figures 5A through 5C illustrate three exemplary methods for reading a device.
  • Each of Figures 5A-5C represents the bias applied and the resulting bias on the cells.
  • Figure 5A represents a floating method where the bias is -V r -> +V r and selected cell 108s is associated with a forward bias of +V r .
  • Figure 5B represents a V/2 reading method.
  • Selected cell 108s is associated with a forward bias of +V r .
  • the remaining unselected cells of Figure 5B are associated with a forward bias of +V r /2.
  • Figure 5C represents a V/3 reading method.
  • Selected cell 108s is associated with a forward bias of +V r .
  • the remaining unselected cells of Figure 5C are associated with either a forward bias of +V r /3 or a reverse bias of -V r /3. It should be appreciated that the unselected cells form a similar pattern as discussed above with reference to Figure 4D.
  • the present invention provides a memory core that eliminates the need for access transistors providing access to the core cells. That is, the access to the core cells may be accomplished through the programming of the core cells when the core cells incorporate a threshold changing material, in this case a chalcogenide material. In essence, the steering element is now accomplished through the programming of the threshold changing material.
  • a threshold changing material in this case a chalcogenide material.
  • the steering element is now accomplished through the programming of the threshold changing material.
  • the elimination of the access transistors also provides for simplified decode logic as signals for the access transistors are no longer necessary for the embodiments described herein.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)

Claims (11)

  1. Un noyau de mémoire, comprenant :
    - une ligne de mot ;
    - une ligne de bit ; et
    - une cellule à noyau en communication électrique avec la ligne de mot et la ligne de bit, la cellule à noyau incluant un matériau possédant une tension seuil à laquelle la résistance électrique change brusquement, comprenant un matériau du type chalcogènure, caractérisé en ce que le matériau à tension seuil variable est programmé de manière à autoriser l'accès à la cellule à noyau sur la base d'une tension appliquée à la ligne de mot et en ce que la cellule à noyau est configurée de manière à agir à la fois comme dispositif de commutation et comme dispositif de stockage.
  2. Le noyau de mémoire de la revendication 1, dans lequel la cellule à noyau est configurée de manière à créer une mémoire non volatile.
  3. Une méthode pour fournir l'accès à une mémoire, comprenant les étapes consistant à :
    - créer une zone de mémoire comprenant une pluralité de lignes de mot, une pluralité de lignes de bit et une pluralité de cellules à noyau électriquement connectées avec les lignes de mot et les lignes de bit, dans laquelle chacune des cellules à noyau contient un matériau à tension seuil variable du type chalcogènure et est configurée de manière à agir à la fois comme dispositif de commutation et comme dispositif de stockage ;
    - déterminer une tension seuil pour l'accès à la zone de mémoire ;
    - programmer les cellules à noyau sélectionnées pour permettre l'accès aux cellules à noyau sélectionnées à la tension seuil ;
    - appliquer une tension à une ligne de mot en communication avec les cellules à noyau sélectionnées ; et
    - si la tension est au moins aussi élevée que la tension seuil, avoir accès aux cellules à noyau sélectionnées.
  4. La méthode de la revendication 3, dans laquelle la programmation des cellules à noyau sélectionnées pour fournir l'accès aux cellules à noyau à la tension seuil inclut l'application d'une tension à la ligne de mot (ou à la ligne de bit) sélectionnée et d'une polarisation zéro à la ligne de bit (ou à la ligne de mot) sélectionnée, tandis que les lignes de bit et les lignes de mot non sélectionnées sont flottantes.
  5. La méthode de la revendication 3, dans laquelle la programmation des cellules à noyau sélectionnées à la tension seuil inclut l'application d'une tension à la ligne de mot (ou à la ligne de bit) sélectionnée et d'une polarisation zéro à la ligne de bit (ou à la ligne de mot) sélectionnée et l'application d'une autre tension aux lignes de bit et aux lignes de mot non sélectionnées.
  6. La méthode de la revendication 3, comprenant au surplus, si la tension est inférieure à la tension seuil, le refus de l'accès aux cellules à noyau sélectionnées.
  7. Une méthode de lecture d'un dispositif à mémoire de chalcogènure, comprenant les étapes consistant à :
    - créer une zone de mémoire comprenant une pluralité de lignes de mot, une pluralité de lignes de bit et une pluralité de cellules à noyau électriquement connectées avec les lignes de mot et les ligne de bit, dans laquelle chacune des cellules à noyau contient un matériau à tension seuil variable, comprenant un chalcogènure, et est configurée de manière à agir à la fois comme dispositif de commutation et comme dispositif de stockage ;
    - appliquer une tension de lecture aux ligne de mot sélectionnées, la tension de lecture étant choisie de manière à fournir directement l'accès aux cellules à mémoire sélectionnées ;
    - appliquer une polarisation zéro aux lignes de bit sélectionnées ;
    - appliquer une tension de lecture aux cellules à mémoire de chalcogènure sélectionnées de manière à lire une valeur stockée dans la mémoire de chalcogènure sélectionnée.
  8. La méthode de la revendication 7, comprenant au surplus, le maintien à l'état flottant à la fois des lignes de mot non sélectionnées et des lignes de bit non sélectionnées.
  9. La méthode de la revendication 7, comprenant au surplus l'application d'une tension de polarisation à la fois aux lignes de mot non sélectionnées et aux lignes de bit non sélectionnées.
  10. La méthode de la revendication 9, dans laquelle la tension de polarisation est inférieure à une tension seuil des cellules à mémoire de chalcogènure.
  11. La méthode de la revendication 9, dans laquelle la tension de polarisation est d'environ la moitié de la tension de lecture et d'environ un tiers de la tension de lecture.
EP03026609A 2003-06-18 2003-11-19 Mémoire à accès aléatoire sans transistors Expired - Lifetime EP1489621B1 (fr)

Applications Claiming Priority (2)

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US464938 2003-06-18
US10/464,938 US7236394B2 (en) 2003-06-18 2003-06-18 Transistor-free random access memory

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EP1489621A1 EP1489621A1 (fr) 2004-12-22
EP1489621B1 true EP1489621B1 (fr) 2007-01-17

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US (1) US7236394B2 (fr)
EP (1) EP1489621B1 (fr)
JP (1) JP4932140B2 (fr)
CN (1) CN100463074C (fr)
DE (1) DE60311238T2 (fr)
TW (1) TWI227056B (fr)

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WO2004017436A2 (fr) * 2002-07-26 2004-02-26 Infineon Technologies Ag Element de memoire non volatil, procedes de production associes et ensembles a element de memoire

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US7787323B2 (en) 2007-04-27 2010-08-31 Freescale Semiconductor, Inc. Level detect circuit

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CN1574067A (zh) 2005-02-02
DE60311238D1 (de) 2007-03-08
JP4932140B2 (ja) 2012-05-16
TWI227056B (en) 2005-01-21
EP1489621A1 (fr) 2004-12-22
TW200501402A (en) 2005-01-01
US7236394B2 (en) 2007-06-26
US20040257872A1 (en) 2004-12-23
CN100463074C (zh) 2009-02-18
JP2005011495A (ja) 2005-01-13
DE60311238T2 (de) 2007-05-16

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