EP1471537B1 - TCAM Speicher und Betriebsverfahren - Google Patents

TCAM Speicher und Betriebsverfahren Download PDF

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Publication number
EP1471537B1
EP1471537B1 EP04003242A EP04003242A EP1471537B1 EP 1471537 B1 EP1471537 B1 EP 1471537B1 EP 04003242 A EP04003242 A EP 04003242A EP 04003242 A EP04003242 A EP 04003242A EP 1471537 B1 EP1471537 B1 EP 1471537B1
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EP
European Patent Office
Prior art keywords
tcam
cells
search line
line pair
defective
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Expired - Fee Related
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EP04003242A
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English (en)
French (fr)
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EP1471537A1 (de
Inventor
Tae-gyoung 507-603 Jinsan Maeul Samsung 5cha Kang
Uk-Rae Cho
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR10-2003-0026427A external-priority patent/KR100505684B1/ko
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage

Definitions

  • the present invention relates to a ternary content addressable memory device capable of storing three states of information, and a corresponding method of operating such a device.
  • RAMs Random Access Memory
  • ROMs read only memory
  • CAMs content addressable memories
  • RAMs and ROMs use addresses to indicate specific cells within the memory cell array to access data therein
  • CAMs receive data instead of addresses.
  • the data input to the CAM is compared with data stored in all the cells simultaneously, and the matched result is the address.
  • the CAM is commonly used in applications requiring fast searches for a pattern, a list, image data, etc.
  • Binary CAM cell and ternary CAM (TCAM) cell are different types of CAMs.
  • a typical binary CAM cell is configured like a RAM cell to store one of two states of information, i.e., a logic "1" state and a logic "0" state.
  • the binary CAM cell includes a compare circuit that compares externally supplied data (hereinafter, 'search data') with data stored in the RAM cell and drives a corresponding match line to a predetermined state when the search data and the stored data are matched. Examples of the binary CAM cells are disclosed in U.S. Patent No. 4,646,271, U.S. Patent No. 4,780,845, U.S. Patent No. 5,490,102, and U.S. Patent No. 5,495,382.
  • a TCAM cell can store one of three states of information, i.e., a logic "1" state, a logic "0" state, and a "don't care” state.
  • An example of the ternary CAM cell is disclosed in U.S. Patent No. 5,319,590.
  • Fig.1 shows a conventional TCAM cell.
  • data to be stored in the CAM cell is loaded onto bit line pairs BL1, /BL1, and BL2, /BL2.
  • the word line WL is asserted active logic '1' turning on n-channel access transistors Q1, Q2, Q3 and Q4.
  • the data carried on the complementary bit line pairs is thereby written into the two SRAM cells and the word line is de-asserted.
  • the word line is asserted an active logic '1' and the data from the SRAM cells is read onto the bit line pairs. The data then is transferred to data buses (not shown).
  • the match line is pre-charged to a logic '1' and the search data is placed on the search line pair SL1 and /SL1.
  • search data and stored data are provided in such a manner that if there is a mismatch a change occurs in the match line state.
  • the match line ML is pre-charged to a logic '1' and a mismatch discharges the match line to ground, whereas in the case of a match no change occurs in the state of the match line.
  • a mismatch will result.
  • the output of the left SRAM cell provides a logic '1' to a transistor Q6 and turning it on.
  • the search line SL1 provides a logic '1' to a transistor Q5 and turning it on. Since Q5 and Q6 are both turned on, they provide a path to discharge the match line ML to ground and thus indicate a mismatch.
  • the CAM cell stores a logic '0' in the left SRAM cell and a logic '1' in the right SRAM cell, a match condition will result.
  • the output of the left SRAM cell provides a logic '0' to the gate of transistor Q6 and leaving it turned off.
  • the search line SL1 provides a logic '1' to the gate of transistor Q5 and turning it on. Since Q5 and Q6 are serially connected, a path to ground does not exist for discharging the match line ML to ground.
  • the right SRAM cell provides a logic '1' to the transistor Q8 and turning it on.
  • the search line /SL1 provides a logic '0' to the transistor Q7 and leaving it turned off. Therefore, similarly to the left SRAM cell, transistors Q7 and Q8 do not provide a path to discharge the match line ML to ground. As a result, the match line remains pre-charged to a logic '1', indicating a match condition.
  • a "don't care" state exists.
  • the output from each SRAM cell produces a logic '0'.
  • the logic '0' is provided to the gate of transistors Q6 and Q8, ensuring that a don't care condition is detected regardless of the data provided on the search line pair SL1 and /SL1, and the match line remains unchanged.
  • TCAMs provide advantages such as speedy access for numerous applications, there are performance and reliability issues which can be improved upon. For example, if the match line is pre-charged to a logic '1' and the CAM cell stores a logic '0' in the right SRAM cell and the search line /SL1 provides a logic '1, then the voltage level of the match line ML fluctuates. This is because the voltage level floats between the transistor Q7 and the transistor Q8.
  • a CAM is rendered inoperable or unusable when there are defective cells.
  • a cell may become defective during the manufacturing process or operation of the CAM.
  • other memories such as SRAM and DRAM have provided redundant memory arrays to replace the defective memory cells.
  • a redundant memory array replaces the array with the defective cell and the data is accessed to and from the redundant memory array. Fuses are generally provided in memories having redundant arrays to switch the arrays into the memory device. When replacement is needed, the fuses for the defective rows are then blown to disable the defective rows, thereby preventing access to the defective rows.
  • An example of a redundancy scheme in a CAM is disclosed in U.S. Patent No. 6,445,628.
  • U.S. Patent No. 6,445,628 B1 discloses a TCAM device and an operation method thereof according to the preamble of present claims 1 and 14, respectively, in which discharging a match line to ground is provided upon detecting that at least one of the memory cells connected thereto is defective.
  • U.S. Patent No. 6,411,538 B1 discloses a TCAM device comprising a comparison circuit with a first plurality of MOS transistors connected between a match line and a second plurality of MOS transistors, and the second plurality of MOS transistors being connected to ground, wherein the first plurality of MOS transistors are gated by signals from the memory cells connected thereto, and the second plurality of MOS transistors are gated by signals from a search line pair.
  • the invention solves this problem by providing a TCAM device according to claim 1, and an operating method according to claim 14.
  • FIG. 2 shows a TCAM cell according to a preferred embodiment of the present invention.
  • the TCAM cell MC11 includes two SRAM cells and a comparison circuit.
  • Each SRAM cell includes two inverters (INV1, INV2 or INV3, INV4) and two access transistors (Q1, Q2 or Q3, Q4).
  • a comparison circuit includes transistors Q5 to Q8.
  • the drains of the transistors Q5 and Q7 are connected to a match line ML.
  • the gates of the transistors Q5 and Q7 are connected to the SRAM cells, respectively.
  • the sources of the transistors Q5 and Q7 are connected to the drains of the transistors Q6 and Q8 respectively.
  • the gates of the transistors Q6 and Q8 are connected to the search line pair SL1 and /SL1 respectively.
  • the sources of the transistors Q6 and Q8 are connected to a common ground. Different from the conventional TCAM cell as shown in Fig.1, the gates of the transistors Q6 and Q8 are connected to search line pair SL1 and /SL1, respectively, and the gates of the transistors Q5 and Q7 are connected to the SRAM cells, respectively. According to the configuration of the TCAM cell of this embodiment, there is no floating voltage at the connection between transistors Q5 and Q6 (or Q7 and Q8).
  • search line (SL1) provides a logic '1'
  • the left SRAM cell provides a logic '0' at node N1
  • the right SRAM cell provides logic '1' at node N2
  • the voltage level of the match line ML does not fluctuate.
  • Fig. 3 shows a block diagram of a CAM 10 in accordance with another second embodiment of the present invention.
  • CAM 10 is configured to replace defective CAM cells in the main CAM array with redundant CAM cells. Further, search line pairs of defective cells are discharged to ground.
  • CAM 10 of Fig. 3 includes a main CAM array 100, spare CAM arrays 200-1 and 200-2, a search line pre-charge circuit 300, a switching circuit 400, a read & write circuit 500, a repair signal generator 600, a decoder 800 and a priority encoder 900.
  • the main CAM array 100 has a plurality of main CAM cells.
  • Spare CAM arrays 200-1 and 200-2 have a plurality of spare CAM cells.
  • the switching circuit 400 receives repair signals RPS[1:n] from the repair signal generator 600 and switches the connections of bit line pairs and search line pairs from a defective memory cell to corresponding connections of a spare memory cell.
  • the search line pre-charge circuit 300 discharges the search line pair to ground when the corresponding search line pair is coupled to a defective CAM cell.
  • the read & write circuit 500 includes sense amplifiers and data input buffers and data output buffers, etc. (not shown).
  • the repair signal generator 600 includes fuses, which may be electrical or laser programmable fuses and stores repair information and outputs repair signals RPS[1:n] to the switching circuit 400.
  • the decoder 800 selectively drives the word lines WL based on an operation mode instruction from a memory controller (not shown).
  • the decoder 800 selectively drives one of the word lines WL when storing data information in TCAM cells of any row or when reading out data information therefrom.
  • the priority encoder 900 generates an address corresponding to currently inputted search data in response to logic states of the match lines ML.
  • Fig. 4 illustrates a more detailed block diagram of the main CAM array 100 and spare CAM arrays 200-1 and 200-2 in Fig. 3.
  • the main CAM array 100 comprises a plurality of CAM cells arranged in a matrix of rows and columns. Each CAM cell is connected to bit line pairs (for example, BL1 to /BL2 in the case of MC1m) and to a search line pair (for example, SL1 and /SL1 in the case of MC1m).
  • the detailed circuit of each CAM cell in CAM array 100 is shown in Fig. 2.
  • Spare CAM arrays 200-1 and 200-2 comprise a plurality of CAM cells arranged in a matrix of rows and column. Each spare CAM cell is connected to spare bit line pairs (for example, SBLL1 to /SBLL2 in the case of SMCL1) and to a search line pair (for example, SSLL and /SSLL in the case of SMCL1).
  • FIG. 6 shows a circuit diagram of a switching circuit 400 in Fig. 3.
  • a switching circuit 400 comprises a plurality of n-type MOS transistors and a plurality of inverters for receiving switching signals RPS [1:n] from the repair signal generator 600.
  • Search lines for example, SSLR, SLn, etc.
  • bit lines for example, SBLR1, BLn-1, etc.
  • Fig. 3 The operation of Fig. 3 to replace a defective column in the main CAM array 100 with a spare column in the spare CAM array 200-1, 200-2 is explained with an example. Assume that MCn2 in the main CAM array 100 of Fig. 4 has been determined to be defective.
  • the repair signal generator 600 provides RPS[1:n] signals to the switching circuit 400. In this case, one signal RPSn has a logic low state and the other signals RPS1 to RPSn-1 have a logic high state (see Fig. 6).
  • transistors which receive the RPS [1:n-1] signals Qsa1 to Qsan-1 and Qsbn are turned on and transistors which receive the outputs of inverters INV Qsb1 to Qsbn-1 and Qsan are turned off.
  • CAM cells MC12 to MC(n-1)2 remain connected as before via active transistors QS1 to QS(n-1).
  • the defective cell Mcn2 is switched off by inactive transistor Qsn.
  • the redundant cell SMCR2 is switched in place of defective MCn2 by active transistor Qsbn (connecting SBLR2 to DLn).
  • Fig. 5 shows a circuit diagram of a search line pre-charge circuit 300 of Fig. 3.
  • a search line pre-charge circuit 300 comprises a plurality of n-type MOS transistors Qc1 to Qc2n. Each n-type MOS transistor Qc1 to Qc2n has a gate that is connected to Vdd and a source that is connected to ground and a drain that is connected to the corresponding search line.
  • the search line pre-charge circuit 300 discharges the search line pair to ground when the corresponding search line pair is coupled to a defective CAM cell.
  • the replaced search line pair (e.g., SLn and /SLn) have a logic low state but other search line pairs SL1 to /SLn-1 have a same logic state as the asserted search data.
  • Fig. 7 shows a block diagram of a CAM 20 in accordance with another embodiment of the present invention.
  • the CAM 20 of Fig.7 is configured the same as the CAM 10 of Fig. 3 except there are differences in a search line pre-charge circuit 300-1 and a repair signal generator 600-1.
  • Fig. 8 shows a detail diagram of search line pre-charge circuit 300-1. This circuit is explained using the first transistor group for SL1 and/SL1.
  • Transistor Qp1 receives at its gate a repair control signal RPC1 from the repair signal generator 600-1, its drain is connected to search line SL1 and its source is connected to search line /SL1.
  • Transistors Qp2 and Qp3 receive at their gates the repair control signal RPC1.
  • repair signal generator 600-1 provides the repair control signals RPC[1:n] to the search line pre-charge circuit 300-1.
  • the repair control signal RPCn has a logic high state and the other repair control signals RPC1 to RPCn-1 have a logic low state.
  • transistors Qp3n-2, Qp3n-1, and Qp3n are turned on and the search line pair SLn, /SLn goes to ground.
  • Fig. 9 shows a block diagram of a CAM 30 in accordance with still another embodiment of the present invention.
  • the CAM 30 of Fig.9 includes the main CAM array 100, a spare CAM arrays 200-1 and 200-2, a main search line driver 700-1, spare search line drivers 700-2, a switching circuit 400, a read & write circuit 500, a repair signal generator 600-2, a decoder 800 and a priority encoder 900.
  • FIG. 10A shows the circuit diagram of the main search line driver 700-1.
  • the main search line driver 700-1 comprises a plurality of inverters and a plurality of NAND gates.
  • FIG. 10B shows the circuit diagram of the spare search line driver 700-2.
  • the spare search line driver 700-2 comprises a plurality of inverters and a plurality of NAND gates.
  • the main CAM array 100 has a plurality of main CAM cells.
  • Spare CAM arrays 200-1 and 200-2 have a plurality of spare CAM cells.
  • the main search line driver 700-1 outputs main search line drive signals SL1 to /SLn in response to repair control signals RPCS1 to RPCSn and search data drive signals DSLD1 to DSLDn (Fig. 10A).
  • the spare search line drivers 700-2 outputs spare search line drive signals SSLL to /SSLR in response to repair control signals RPCSL, RPCSR and search data drive signals DSLD (Fig. 10B).
  • the switching circuit 400 receives repair signals RPS[1:n] from the repair signal generator 600-2 and changes the path of the corresponding bit line pairs and search line pairs to replace a defective memory cell with a spare memory cell.
  • the read & write circuit 500 includes sense amplifiers and data input buffers and data output buffers, etc. (not shown).
  • the repair signal generator 600-2 includes fuses, which may be an electrical or laser programmable types, to store repair information.
  • the repair signal generator 600-2 outputs repair signals RPS[1:n] to the switching circuit 400, outputs repair control signals RPCS1 to RPCSn to the main search line driver 700-1, and outputs repair control signals RPCSL to RPCSR to the spare search line driver 700-2.
  • the decoder 800 selectively drives the word lines WL based on an operation mode instruction from a memory controller (not shown), for example, the decoder 800 selectively drives one of the word lines WL when storing data information in TCAM cells of any row or reading out data information therefrom.
  • the priority encoder 900 generates an address corresponding to currently inputted search data in response to logic states of the match lines ML.
  • FIG. 9 An example is used to illustrate the operation of Fig. 9 to replace a defective column in the main CAM array 100 with a spare column in the spare CAM array 200-1, 200-2.
  • the repair signal generator 600-2 provides RPS[1:n] signals to the switching circuit 400.
  • a repair signal RPSn has a logic low state and repair signals RPS1 to RPSn-1 have a logic high state in Fig. 6.
  • transistors Qsa1 to Qsan-1 and Qsbn are turned on and transistors Qsb1 to Qsbn-1 and Qsan are turned off. Referring to Fig.
  • search line pair (e.g., SLn and /SLn) have a logic low state but other search line pairs SL1 to /SLn-1 have a same logic state as the asserted search data.
  • the repair signal generator 600-2 provides repair control signals RPCSL in a logic low state for the corresponding defective cell to switch redundant cell to the bit line and data connections of the defective cell.
  • Fig. 10B shows corresponding search line drive signals SSLL and /SSLL going to a logic low state in response to a logic low RPCSL.

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)

Claims (16)

  1. Ternäres inhaltsadressierbares Speicherbauelement (TCAM-Bauelement) mit
    - einer Mehrzahl von TCAM-Zellen (MC11) zum Speichern von Daten, wobei jede TCAM-Zelle zwei Speicherzellen (210, 220) und eine Vergleichsschaltung (230) zum Vergleichen von Daten, die in den Speicherzellen gespeichert sind, mit Daten, die auf einem mit der Vergleichsschaltung verbundenen Suchleitungspaar (SL1, /SL1) zugeführt werden, umfasst;
    - einem Reparatursignalgenerator (600) zur Erzeugung von Signalen, die anzeigen, welche der Speicherzellen defekt sind; und
    - einer Vorladeschaltung (300), die mit dem Reparatursignalgenerator verbunden ist;
    dadurch gekennzeichnet, dass
    - die Vorladeschaltung (300) mit dem Suchleitungspaar (SL1, /SL1) verbunden ist, um jede Leitung des Suchleitungspaares bei Empfang eines Signals vom Reparatursignalgenerator (600) nach Masse zu entladen, das anzeigt, dass wenigstens eine der damit verbundenen Speicherzellen defekt ist.
  2. TCAM-Bauelement nach Anspruch 1, wobei die Vergleichsschaltung eine erste Mehrzahl von MOS-Transistoren (Q5, Q7) aufweist, die zwischen eine Übereinstimmungsleitung (ML) und eine zweite Mehrzahl von MOS-Transistoren (Q6, Q8) eingeschleift sind, wobei die zweite Mehrzahl von MOS-Transistoren mit Masse verbunden ist und die erste Mehrzahl von MOS-Transistoren durch Signale von damit verbundenen Speicherzellen gategesteuert wird und die zweite Mehrzahl von Transistoren durch Signale vom Suchleitungspaar gategesteuert werden.
  3. TCAM-Bauelement nach Anspruch 2, wobei die erste Mehrzahl von n-leitenden MOS-Transistoren erste und zweite NMOS-Transistoren beinhaltet, deren Drains mit der Übereinstimmungsleitung verbunden sind und deren Gates mit den Speicherzellen verbunden sind, und die zweite Mehrzahl von n-leitenden MOS-Transistoren dritte und vierte NMOS-Transistoren aufweist, deren Gates mit dem Suchleitungspaar verbunden sind, deren Sources mit Masse verbunden sind und deren Drains mit Sources der ersten und zweiten NMOS-Transistoren verbunden sind.
  4. TCAM-Bauelement nach Anspruch 2, wobei die erste und zweite Mehrzahl von MOS-Transistoren n-leitend sind und so konfiguriert sind, dass sie die Übereinstimmungsleitung bei einer Nichtübereinstimmung der Daten in den zugehörigen Speicherzellen mit den auf dem zugehörigen Suchleitungspaar vorliegenden Daten entladen oder mit Masse verbinden.
  5. TCAM-Bauelement nach einem der Ansprüche 1 bis 4, wobei die Vorladeschaltung zwei NMOS-Transistoren (Qc1, Qc2) beinhaltet, von denen jeder mit seinem Gate an einen Leistungsversorgungsknoten angeschlossen ist, mit seiner Source an Masse angeschlossen ist und mit seiner Drain an ein zugehöriges Suchleitungspaar angeschlossen ist.
  6. TCAM-Bauelement nach Anspruch 5, wobei die zwei NMOS-Transistoren der Vorladeschaltung derart bemessen sind, dass sie einen niedrigen Pegel auf dem Suchleitungspaar bereitstellen, wenn kein Signal auf dem Suchleitungspaar vorhanden ist, und den gleichen Pegel wie ein bestätigtes Signal auf dem Suchleitungspaar bereitstellen.
  7. TCAM-Bauelement nach einem der Ansprüche 1 bis 4, wobei die Vorladeschaltung eine Mehrzahl von MOS-Transistoren beinhaltet, die mit ihren Gates gemeinsam an die Signalleitung von dem Reparatursignalgenerator angeschlossen sind, wobei die Mehrzahl von MOS-Transistoren ein Paar von Transistoren (Qp2, Qp3) zum Verbinden des Suchleitungspaars mit Masse und einen Ausgleichstransistor (Qp1) zum Ausgleichen des Suchleitungspaars bei Empfang eines Aktivierungssignals auf der Signalleitung von dem Reparatursignalgenerator aufweist.
  8. TCAM-Bauelement nach einem der Ansprüche 1 bis 7, das des weiteren redundante TCAM-Zellen und einen schaltenden Schaltkreis (400) zum Schalten wenigstens einer Mehrzahl von Verbindungen von TCAM-Zellen, die als defekt bestimmt wurden, mit den redundanten TCAM-Zellen oder mit entsprechenden Verbindungen der redundanten TCAM-Zellen umfasst.
  9. TCAM-Bauelement nach Anspruch 8, wobei die redundanten TCAM-Zellen wenigstens eine Spalte von TCAM-Zellen bilden.
  10. TCAM-Bauelement nach Anspruch 8 oder 9, wobei der schaltende Schaltkreis Signale zum Schalten von Verbindungen einer Spalte von TCAM-Zellen, die defekte Zellen aufweist, mit entsprechenden Verbindungen einer Spalte von redundanten TCAM-Zellen abgibt.
  11. TCAM-Bauelement nach einem der Ansprüche 1 bis 10, das des weiteren einen Hauptsuchleitungstreiber zum Treiben von Datensignalen zu einer Mehrzahl von Suchleitungspaaren und wenigstens einen redundanten Suchleitungstreiber zum Ersetzen des Hauptsuchleitungstreibers umfasst, wenn festgestellt wird, dass wenigstens eine der mit einem zugehörigen Suchleitungspaar verbundenen Speicherzellen defekt ist.
  12. TCAM-Bauelement nach einem der Ansprüche 1 bis 11, das des weiteren eine Speichersteuereinheit zum Abgeben von Steuersignalen zum Steuern von Betriebsvorgängen des TCAM umfasst.
  13. TCAM-Bauelement nach einem der Ansprüche 1 bis 12, wobei die Speicherzellen SRAM- oder DRAM-Zellen sind.
  14. Verfahren zum Betrieb eines ternären inhaltsadressierbaren Speicherbauelements (TCAM-Bauelements), bei dem
    - in Speicherzellen (MC111) des TCAM-Bauelements gespeicherte Daten mit Daten verglichen werden, die auf einem Suchleitungspaar (SL1, /SL1) zugeführt werden, das mit einer Vergleichsschaltung (230) verbunden ist, und
    - Reparatursignale (RPS[1:n]) erzeugt werden, die anzeigen, welche der Speicherzellen defekt sind,
    dadurch gekennzeichnet, dass
    - jede Leitung des Suchleitungspaars (SL1, /SL1) nach Masse entladen wird, wenn die Reparatursignale (RPS[1:n]) anzeigen, dass wenigstens eine der damit verbundenen Speicherzellen defekt ist.
  15. Verfahren nach Anspruch 14, das des weiteren ein Schalten wenigstens einer Mehrzahl von Verbindungen von TCAM-Zellen, die als defekt bestimmt wurden, zu redundanten TCAM-Zellen umfasst.
  16. Verfahren nach Anspruch 15, wobei die Mehrzahl von Verbindungen von TCAM-Zellen zu einer Spalte von redundanten TCAM-Zellen gehört.
EP04003242A 2003-04-25 2004-02-13 TCAM Speicher und Betriebsverfahren Expired - Fee Related EP1471537B1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2003-0026427A KR100505684B1 (ko) 2003-04-25 2003-04-25 칼럼 결함 복구가 가능한 캠 및 캄럼 결함 복구 방법
KR2003026427 2003-04-25
US10/644,145 US7002822B2 (en) 2003-04-25 2003-08-20 Content addressable memory device
US644145 2003-08-20

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EP1471537A1 EP1471537A1 (de) 2004-10-27
EP1471537B1 true EP1471537B1 (de) 2006-07-26

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US (1) US7274580B2 (de)
EP (1) EP1471537B1 (de)
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CN100527275C (zh) 2009-08-12
US20060062038A1 (en) 2006-03-23
DE602004001623T2 (de) 2007-08-09
EP1471537A1 (de) 2004-10-27
US7274580B2 (en) 2007-09-25
CN1540669A (zh) 2004-10-27
JP2004327028A (ja) 2004-11-18

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