EP1450417A1 - LED grande puissance présentant des proprietés thermiques améliorées - Google Patents

LED grande puissance présentant des proprietés thermiques améliorées Download PDF

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Publication number
EP1450417A1
EP1450417A1 EP04100448A EP04100448A EP1450417A1 EP 1450417 A1 EP1450417 A1 EP 1450417A1 EP 04100448 A EP04100448 A EP 04100448A EP 04100448 A EP04100448 A EP 04100448A EP 1450417 A1 EP1450417 A1 EP 1450417A1
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Prior art keywords
contact
semiconductor layer
submount
active region
contacts
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EP04100448A
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German (de)
English (en)
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Yu-Chen Shen
Daniel A. Steigerwald
Paul S. Martin
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Lumileds LLC
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Lumileds LLC
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Publication of EP1450417A1 publication Critical patent/EP1450417A1/fr
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Definitions

  • the present invention relates to high-powered light emitting diodes, more particularly to improving the thermal properties of high-powered light emitting diodes with flip-chip architecture.
  • LEDs Light emitting diodes
  • An important class of light emitting diodes is fabricated from one or more Group III elements, such as gallium, indium, or aluminum, and the group V element of nitrogen. These "III-nitride” LEDs are capable of emitting light in the green, blue, or even ultraviolet regime of the spectrum, and thus have many promising applications.
  • Other suitable materials systems for fabrication of light emitting diodes include the III-phosphide, III-arsenide and II-VI materials systems.
  • LEDs are often fabricated by epitaxially depositing an n-type region, an active region and a p-type region on a substrate.
  • Contacts typically metal, are formed on the n-type region and the p-type region. During operation, the contacts provide current to the n- and p-sides of the device.
  • the growth substrate is often removed after growth, an n-contact is deposited on the exposed n-type region, and a p-contact is deposited on the p-type region.
  • a portion of the active region and the p-type region are etched away, exposing a portion of the n-type region.
  • the p-contact is formed on the remaining portion of the p-type region and the n-contact is formed on the exposed portion of the n-type region, such that both contacts are formed on the same side of the device.
  • the light may be extracted from the device through the contacts or through the side of the device without the contacts.
  • Devices that extract light through the contacts are generally disfavored because in order to provide enough current to the device, the typically metal contacts must be thick enough that they are essentially opaque.
  • Devices that extract light through the side of the device without the contacts are referred to as flip chips. III-nitride devices are often grown on sapphire substrates and included in devices in flip chip configuration.
  • a light emitting device includes a first semiconductor layer of a first conductivity type, an active region, and a second semiconductor layer of a second conductivity type.
  • First and second contacts are connected to the first and second semiconductor layers. In some embodiments at least one of the first and second contacts has a thickness greater than 3.5 microns.
  • a first heat extraction layer is connected to one of the first and second contacts.
  • one of the first and second contacts is connected to a submount by a solder interconnect having a length greater than a width.
  • an underfill is disposed between a submount and a growth substrate.
  • the thickness, area, and materials used in the first and second contacts, the heat extraction layer, the solder interconnect, and the underfill may be selected to reduce the average temperature and temperature gradient in the device.
  • Figure 1 illustrates a III-nitride flip chip light emitting device according to embodiments of the present invention. Aspects of the flip chip design illustrated in Figure 1 are described in more detail in U.S. Patent No. 6,486,499, issued November 26, 2002, titled “III-Nitride Light-Emitting Device With Increased Light Generating Capability,” and incorporated herein in its entirety by this reference.
  • flip chip 10 die 45 is manufactured, then flipped and mounted on submount 62 such that light is extracted from the device through growth substrate 14. The manufacture of the flip chip light emitting diode 10 starts with the die 45.
  • Die 45 is manufactured initially by epitaxially depositing semiconductor material on a substrate by molecular beam epitaxy, metal-organic chemical vapor deposition, or any other suitable epitaxial technique. Metals are then deposited and patterned on the semiconductor material to form contacts. An interconnect material is then used to connect the submount 62 to die 45.
  • Substrate 14 such as sapphire, SiC, GaP, or GaAs, is chosen to have a high index of refraction and transparency to the selected wavelength of light, as well as suitable crystal growing properties.
  • First semiconductor region 18, active region 21, and second semiconductor region 25 are deposited substantially simultaneously.
  • group III elements, for example gallium, and group V elements, for example nitrogen, are deposited substantially simultaneously.
  • Aluminum and indium are added in these semiconductor layers to engineer the band structure.
  • First semiconductor region 18 may be n-doped with an n-type dopant, such as silicon, and second semiconductor region 25 may be p-doped with a p-type dopant, for example magnesium.
  • Each of regions 18 and 25 may contain multiple layers of the same or different composition, thickness, and dopant concentration.
  • Active region 21 generally contains multiple quantum wells (MQW) which are capable of generating light through radiative recombination of electrons and holes.
  • the quantum wells of active region 21 are designed to provide spatial confinement of the electrons and holes, thus enhancing the efficiency of the LED.
  • a first contact 29 is formed overlying second semiconductor region 25.
  • the functions of first contact 29 include providing electrical contact to second semiconductor layer 25.
  • First contact 29 can be formed using metals, metal alloys and metal oxides.
  • First contact 29 can include several layers of various thickness and layout.
  • a first solderable layer 30 is deposited and patterned to form a contact with the solder 58-1-i.
  • a dielectric (such as spin-on-glass, SOG) 33 is deposited partially overlying first solderable layer 30.
  • Dielectric 33 is formed with several openings to accommodate electrical contacts.
  • the functions of dielectric 33 include providing electrical insulation for first contact 29 and holding solder balls in place.
  • the thickness of dielectric 33 may be between about 0.03 micron and about 3 microns.
  • a second contact 37 is formed by etching away a portion of first contact 29, second semiconductor layer 25 and active region 21. Second contact 37 is then formed directly over the cleared portion of first semiconductor region 18.
  • the functions of second contact 37 include providing an electrical contact for first semiconductor region 18.
  • Second contact 37 can be formed using metals, metal alloys, and metal oxides.
  • a second solderable layer 31 is deposited over contact 37 and patterned. The second solderable layer is used as a contact layer to the solder ball 58-2.
  • a dielectric 41 is deposited partially overlying second solderable layer 31. Dielectric 41 has openings for accommodating electrical contacts.
  • the functions of dielectric 41 include providing electrical insulation for second contact 37.
  • the thickness of dielectric 41 may be between about 0.03 micron and about 3 microns.
  • Dielectric 33 and dielectric 41 can be the same dielectric layer.
  • a submount structure 62 includes a SiO 2 layer 70, a Si layer 66, and a solderable layer 79.
  • Bonding pads 74-1 and 74-2 are deposited overlying semiconductor oxide layer 70, corresponding to first contact 29 and second contact 37, respectively.
  • Bonding pads 74-1 and 74-2 can be formed, for example, from aluminum or silver.
  • Insulating layers 82-1 and 82-2 are formed overlying bonding pads 74-1 and 74-2 with openings to accommodate solder balls. Insulating layers 82-1 and 82-2 can be formed, for example, from alloys of silicon and nitrogen. Circuitry or other additional features may be included within or attached to submount 62 in order to enable enhanced functionality. For example, Zener diodes maybe included for protection from electrostatic discharge (ESD).
  • Die 45 is electrically and physically connected to submount 62 using solder balls 58-1-i and solder ball 58-2.
  • Solder ball 58-2 provides an electrical contact to second contact 37 through solderable layer 31, and solder balls 58-1-i provide electrical contact to first contact 29 through solderable layer 30.
  • a suitable choice for the material of solder balls 58-1-i and solder ball 58-2 is, for example, a PbSn alloy.
  • Figure 1 illustrates four solder balls connecting contact 29 to the submount and one solder ball connecting contact 37 to the submount, more or fewer solder balls may be used with contact 29 and more solder balls may be used with contact 37.
  • Solder balls 58-1-i and solder ball 58-2 are soldered into the openings of dielectric layers 33 and 41 of die 45 and into the openings of insulating layers 82-1 and 82-2 of submount structure 62.
  • the device illustrated in Figure 1 generally has an area of about one square millimeter and is conventionally operated at a current less than 350 mA, which corresponds to 50A/cm 2 . At current densities less than 50A/cm 2 , the structure illustrated in Figure 1 demonstrates an acceptably long operating lifetime. Operating the device 1 at currents of 1A-3A, corresponding to a current density of 143 A/cm 2 , is desirable as it is expected to generate more light than operation at less than 50A/cm 2 ; however, at current densities greater than 143 A/cm 2 , the devices illustrated in Figure 1 fail after an unsuitably short amount of time.
  • An increase in the average temperature in the die may lead to a decrease of the confinement of carriers in the active region, reducing the recombination rates and hence the efficiency of the LED, and may cause the materials in contacts 29 and 37 or in the semiconductor layers to diffuse into other parts of the device, resulting in device failure.
  • the small ratio of the area of solder balls 58-1-i and 58-2 to the area of die 45 cause extremely large temperature gradients. Large temperature gradients can generate mechanical strain within the substrate and the semiconductor layers, which can lead to the cracking of the die.
  • modeling of device 10 demonstrated that operation of device 10 at a current density of about 50A/cm 2 with a forward voltage of 3.7 V may generate a temperature gradient of 80 K/mm. Operation of device 10 at a current of about 143 A/cm 2 with a forward voltage of 3.7 V may generate a temperature gradient of about 200K/mm, much higher than the gradient at 50A/cm 2 .
  • temperatures and thermal gradients within the device may be reduced by designing metal and substrate layers within the device to maximize dissipation of heat, by adding metal layers to the device to maximize dissipation of heat, by designing interconnect layers to maximize dissipation of heat, and by filling air gaps within the device with materials that dissipate heat.
  • Particularly good thermal gradient reduction can be achieved by forming thick thermally conductive layers that allow enough distance for heat to travel laterally to the solder as it travels vertically through the die.
  • Embodiments of the invention may be used in large junction devices, i.e. devices with an area greater than one square millimeter, or in small junction devices, i.e. devices with an area less than one square millimeter.
  • the thermal resistance per area of the device is reduced to below 10K/W-mm 2 .
  • the temperature gradient is reduced to below 30K/mm.
  • first contact 29 and second contact 37 can be a single layer of uniform composition, or may include multiple layers of the same or different composition.
  • first contact 29 and second contact 37 may include an ohmic layer, a reflective layer, a guard layer, and a heat extraction layer. Increasing the thickness of first contact 29 and second contact 37 from about 0.2 micron to about 10 microns may lower the temperature and temperature gradients within the device.
  • Figure 4A illustrates temperature contours in semiconductor layer 18 in a device with 0.2 micron thick contacts 29 and 37
  • Figure 6 illustrates temperature contours in semiconductor layer 18 in a device with 10 micron thick contacts 29 and 37.
  • the maximum temperature expected in semiconductor layer 18 is 370 K in a device with 0.2 micron thick contacts, and only 340 K in a device with 10 micron thick contacts.
  • increasing the thickness of the contacts lowers the maximum temperature rise from ambient of first semiconductor layer 18 from about 70 K to about 40 K, when the device is generating 3.7 W of heat.
  • Increasing the thickness of first contact 29 and second contact 37 may also decrease the temperature gradient at a predefined location.
  • the temperature gradient in the region immediately adjacent to the solder balls is about 40 K for a device with 0.2 micron contacts, and only about 20K for a device with 10 micron contacts.
  • the thickness of at least one of first contact 29 and second contact 37 is greater than 3.5 microns.
  • the amount of heat dissipated by the device may be further reduced by increasing the area of contacts 29 and 37, or by using metals with high thermal conductivity within first and second contact layers 29 and 37.
  • metals include Ag, Al, Au, and Cu.
  • the material used for substrate 14 is selected to have high thermal conductivity in order to dissipate heat.
  • a substrate with suitable growth properties and high thermal conductivity is silicon carbide.
  • Figure 2 illustrates an embodiment of the invention where at least one of the contacts includes a heat extraction layer.
  • a first heat extraction layer 86 is formed as part of first contact 29 adjacent to solderable layer 30, and a second heat extraction layer 90 is formed as part of second contact 37 adjacent solderable layer 31.
  • the thickness, area, and material of first and second heat extraction layers 86 and 90 are selected to spread the heat generated in the device to reduce the temperature and temperature gradients within regions 18, 21, and 25, and act as heat sinks to withdraw heat from within the device.
  • First and second heat extraction layers 86 and 90 may be metals with high thermal conductivity, such as Al (thermal conductivity about 240 W/m-K), Cu (thermal conductivity about 390 W/m-K), or Au (thermal conductivity of about 310 W/m-K), Ni, V, or stacks of multiple metals.
  • the larger the area and thickness of first and second heat extraction layers 86 and 90 the better the heat extraction properties.
  • Heat extraction layers with thicknesses greater than about 0.2 micron can give rise to favorable thermal properties.
  • first and second heat extraction layers have a thickness of 3.5 microns or more.
  • a favorable reduction of the thermal resistance and of the temperature gradient at a predefined location can be achieved if the area of first and second heat extraction layers 86 and 90 is greater than about 20% of the area of first semiconductor layer 18.
  • first and second heat extraction layers 86 and 90 are good heat conductors, the device illustrated in Figure 2 conducts heat away from die 45, thereby reducing the thermal resistance of die 45.
  • the average temperature rise from the ambient temperature (298K) of die 45 decreases by about 38% compared to the average temperature rise of die 45 in a device according to Figure 1 without heat extraction layers 86 and 90.
  • the average temperature rise from ambient of first semiconductor layer 18 in a device according to Figure 1 without first and second heat extraction layers 86 and 90 may be about 65 K.
  • the average temperature rise of first semiconductor layer 18 may be about 40 K.
  • the lowest temperature rise from ambient to a temperature in die 45 generally occurs in the area above second contact 37, mostly because active layer 21 has been etched away, thus no heat generating recombination is taking place in the region above second contact 37.
  • This lowest temperature rise is approximately the same in the architectures of Figures 1 (with 0.2 micron contacts) and Figure 2.
  • the maximum temperature is smaller in the embodiment of Figure 2, which lowers the average temperature. Since the minimum temperature remains the same, the temperature variations and thus the temperature gradients at predefined locations are smaller in the embodiment of Figure 2. In general, temperature gradients below 30 K/mm are considered desirable.
  • Figures 3A-D show embodiments of the invention where solder balls 58-1-i and solder ball 58-2 of Figure 1 are replaced by solder bars 94-j, in order to increase the area of the interconnect between die 45 and submount 62 to dissipate more heat.
  • Figure 3A shows a side view
  • Figure 3B shows a top view of the embodiment. Devices may have more or fewer solder bars than are illustrated in Figure 3B.
  • Figure 3C shows the top view of another embodiment, where the solder bars are connected to form one extended solder bar 86. Enlargement of the interconnect area decreases the average temperature, as well as the temperature gradients at predefined locations within die 45.
  • the solder bars of Figures 3A-C are used in combination with the heat extraction layers 86 and 90 of Figure 2.
  • the solder used in the solder bars is selected for high thermal conductivity, in order to maximize heat extraction through the solder.
  • Materials that have the necessary mechanical and chemical properties and have high thermal conductivity include, for example, In, Sn, and the alloys of Pb x Sn 100-x and Ag x In 100-x , wherein x can range between zero and hundred, and is preferably about 3.
  • Figures 4A and 4B illustrate temperature gradients in portions of device with solder balls and with solder bars, respectively. As illustrated in Figure 4A, solder balls form a contact with die 45 only in limited areas. The shape of these areas are usually approximately circular.
  • Figure 4A also illustrates the temperature variations within first semiconductor layer 18 of die 45, when the device is connected to a heat sink of about 300K, operating at 1A, and generating 3.7 W of heat. Temperature contours corresponding to 320 K, 340 K, 350 K, and 370 K are identified. As shown, the temperature of first semiconductor layer 18 can vary between about 320 K and 370 K. In fact, a large fraction of the die area has temperatures in the vicinity of 370 K.
  • the temperature within semiconductor layer 18 is lowest in the vicinity of contact areas with solder.
  • the temperature gradients within the device illustrated in Figure 4A are steep around the areas of contact with solder balls 58-1-i and solder ball 58-2. These steep temperature gradients can give rise to failure mechanisms such as cracking due to increased mechanical strains and unwanted change of chemical composition.
  • the structure and operating conditions of the device illustrated in Figure 4B are the same as the device illustrated in Figure 4A, except that Figure 4A's solder balls are replaced with solder bars in Figure 4B.
  • the larger contact area of the solder bar architecture lowers the temperature of semiconductor layer 18 in the device of Figure 4B to between about 320 K and about 350 K, which lowers the average temperature by about 30 percent and equivalently the average temperature rise by about 30 percent.
  • the temperature gradients are reduced because of the smaller temperature differences across die 45 and the larger area over which these changes are distributed.
  • Figure 5 illustrates an embodiment of the invention which fills the unfilled portions of the region between die 45 and submount 62 with an underfill material with high thermal conductivity.
  • the underfill material may be, for example, a gel or any other malleable material such as a paste, foam, or dust of a suitable heat conductor.
  • Underfill 98 can be introduced into the unfilled space around solder balls 58-1-i and solder ball 58-2, or solder bars 94-j. In some embodiments, the unfilled space is filled up partially, in others the unfilled space is filled completely with underfill 98. Using underfill 98 can lead to a reduction of thermal resistance and thus a reduction of the average temperature of die 45.
  • Underfill 98 should have satisfactory thermal conductivity and at the same time sufficiently low electrical conductivity to avoid unwanted electrical conduction.
  • the underfill usually has a thermal conductivity greater than about 3 W/m-K. In some embodiments, the underfill has a thermal conductivity greater than about 10 W/m-K.
  • Materials suitable for this purpose include diamond dust, boron nitride, TiO 2 paste, and certain gels.
  • An additional benefit of the embodiment is that underfill 98 prevents unwanted contaminants from entering the unfilled space of the flip chip, which could give rise to, for example, undesirable electrical pathways.
  • coupling the device to heat sinks also known as “slugs,” made of metals with high thermal conductivity, further reduces thermal resistances and temperature gradients at predefined locations.
  • Metals with high thermal conductivity include Cu and Al.
  • Figure 7 illustrates some embodiment of a flip chip LED 10 in a high-power package.
  • the high-power package includes a heat sink 204, formed from a low thermal resistance material.
  • Heat sink 204 also serves as a reflector cup, reflecting the light emitted from LED 10 towards the base of the package.
  • a further function of heat sink 204 is to accommodate and compensate the effects of the thermal expansion of the packaged LED's components.
  • LED 10 is attached to heat sink 204 with solder or die-attach-epoxy.
  • LED 10 is electrically coupled to inner leads 208 by solder balls or solder bars. Inner leads 208 are electrically coupled to outer leads 216.
  • Inner leads 208 and outer leads 216 are formed from suitably chosen metals.
  • Flip chip LED 10 is encapsulated into a transparent housing that includes an epoxy dome cover 220.
  • Cover 220 may be a lens for enhanced light extraction.
  • a soft gel 224 with high refractive index is disposed between flip chip LED 10 and epoxy dome cover 220 to enhance light extraction.
  • the packaged flip chip LED is structurally supported by a support frame 228.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)
EP04100448A 2003-02-19 2004-02-06 LED grande puissance présentant des proprietés thermiques améliorées Withdrawn EP1450417A1 (fr)

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US10/369,714 US6977396B2 (en) 2003-02-19 2003-02-19 High-powered light emitting device with improved thermal properties

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US20060097336A1 (en) 2006-05-11
JP2005294284A (ja) 2005-10-20
US7351599B2 (en) 2008-04-01
TW200501453A (en) 2005-01-01
US20040160173A1 (en) 2004-08-19

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